From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry
Date: Fri, 08 Mar 2013 11:42:27 -0700 [thread overview]
Message-ID: <513A3113.10909@wwwdotorg.org> (raw)
In-Reply-To: <513A2A6D.7080604-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 03/08/2013 11:14 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:34 PM, Stephen Warren wrote:
>> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>>> supports 11x8 type of matrix. The number of rows and columns
>>> are configurable.
>> Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
>> the following defines in the driver:
>>
>> #define KBC_MAX_GPIO 24
>> #define KBC_MAX_ROW 16
>> #define KBC_MAX_COL 8
>> #define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
>>
>> Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
>> think that makes the HW technically incompatible, since GPIO IDs 19..23
>> are invalid in this HW but valid earlier.
>>
>> Now in practice I suppose that with a correct DT keyboard map for a
>> Tegra114 device, those extra invalid GPIOs would never be referenced, so
>> this is a little nit-picky, but I still feel we should fix this.
>
> Where do we fix this? In binding document?
In the driver and .dtsi files; the rest of my message was describing how
to fix this.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry
Date: Fri, 08 Mar 2013 11:42:27 -0700 [thread overview]
Message-ID: <513A3113.10909@wwwdotorg.org> (raw)
In-Reply-To: <513A2A6D.7080604@nvidia.com>
On 03/08/2013 11:14 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:34 PM, Stephen Warren wrote:
>> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>>> supports 11x8 type of matrix. The number of rows and columns
>>> are configurable.
>> Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
>> the following defines in the driver:
>>
>> #define KBC_MAX_GPIO 24
>> #define KBC_MAX_ROW 16
>> #define KBC_MAX_COL 8
>> #define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
>>
>> Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
>> think that makes the HW technically incompatible, since GPIO IDs 19..23
>> are invalid in this HW but valid earlier.
>>
>> Now in practice I suppose that with a correct DT keyboard map for a
>> Tegra114 device, those extra invalid GPIOs would never be referenced, so
>> this is a little nit-picky, but I still feel we should fix this.
>
> Where do we fix this? In binding document?
In the driver and .dtsi files; the rest of my message was describing how
to fix this.
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Laxman Dewangan <ldewangan@nvidia.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Subject: Re: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry
Date: Fri, 08 Mar 2013 11:42:27 -0700 [thread overview]
Message-ID: <513A3113.10909@wwwdotorg.org> (raw)
In-Reply-To: <513A2A6D.7080604@nvidia.com>
On 03/08/2013 11:14 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:34 PM, Stephen Warren wrote:
>> On 03/08/2013 06:53 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
>>> supports 11x8 type of matrix. The number of rows and columns
>>> are configurable.
>> Earlier Tegra versions supported up to a 16x8 matrix. This feeds into
>> the following defines in the driver:
>>
>> #define KBC_MAX_GPIO 24
>> #define KBC_MAX_ROW 16
>> #define KBC_MAX_COL 8
>> #define KBC_MAX_KEY (KBC_MAX_ROW * KBC_MAX_COL)
>>
>> Given Tegra114 supports /fewer/ pins and rows than earlier chips, I
>> think that makes the HW technically incompatible, since GPIO IDs 19..23
>> are invalid in this HW but valid earlier.
>>
>> Now in practice I suppose that with a correct DT keyboard map for a
>> Tegra114 device, those extra invalid GPIOs would never be referenced, so
>> this is a little nit-picky, but I still feel we should fix this.
>
> Where do we fix this? In binding document?
In the driver and .dtsi files; the rest of my message was describing how
to fix this.
next prev parent reply other threads:[~2013-03-08 18:42 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-08 13:52 [PATCH 0/5] ARM: DT: tegra114: Add DT entry for different controller Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
2013-03-08 13:52 ` [PATCH 1/5] ARM: DT: tegra114: add APB DMA controller DT entry Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
[not found] ` <1362750782-15174-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 17:51 ` Stephen Warren
2013-03-08 17:51 ` Stephen Warren
2013-03-08 17:51 ` Stephen Warren
2013-03-08 18:06 ` Laxman Dewangan
2013-03-08 18:06 ` Laxman Dewangan
[not found] ` <513A2888.5020402-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 18:41 ` Stephen Warren
2013-03-08 18:41 ` Stephen Warren
2013-03-08 18:41 ` Stephen Warren
[not found] ` <513A30D3.4020700-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-03-08 18:46 ` Laxman Dewangan
2013-03-08 18:46 ` Laxman Dewangan
2013-03-08 18:46 ` Laxman Dewangan
2013-03-08 13:52 ` [PATCH 2/5] ARM: DT: tegra114: Add i2c " Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
2013-03-08 13:52 ` Laxman Dewangan
2013-03-08 13:53 ` [PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
[not found] ` <1362750782-15174-4-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 17:54 ` Stephen Warren
2013-03-08 17:54 ` Stephen Warren
2013-03-08 17:54 ` Stephen Warren
[not found] ` <513A25E4.8040504-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-03-08 18:04 ` Laxman Dewangan
2013-03-08 18:04 ` Laxman Dewangan
2013-03-08 18:04 ` Laxman Dewangan
[not found] ` <513A281B.9010702-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 18:40 ` Stephen Warren
2013-03-08 18:40 ` Stephen Warren
2013-03-08 18:40 ` Stephen Warren
[not found] ` <1362750782-15174-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 13:53 ` [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
[not found] ` <1362750782-15174-5-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 18:04 ` Stephen Warren
2013-03-08 18:04 ` Stephen Warren
2013-03-08 18:04 ` Stephen Warren
2013-03-08 18:14 ` Laxman Dewangan
2013-03-08 18:14 ` Laxman Dewangan
[not found] ` <513A2A6D.7080604-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-03-08 18:42 ` Stephen Warren [this message]
2013-03-08 18:42 ` Stephen Warren
2013-03-08 18:42 ` Stephen Warren
2013-03-08 13:53 ` [PATCH 5/5] ARM: DT: tegra114: Add spi " Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
2013-03-08 13:53 ` Laxman Dewangan
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