* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
@ 2013-04-12 6:53 ` Alison Wang
2013-04-12 11:15 ` Fabio Estevam
` (2 more replies)
2013-04-12 6:53 ` [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support Alison Wang
` (5 subsequent siblings)
6 siblings, 3 replies; 27+ messages in thread
From: Alison Wang @ 2013-04-12 6:53 UTC (permalink / raw)
To: u-boot
The Vybrid devices are a family of Freescale's latest Dual Single
Core offering with ARM Cortex A5 and CM4 based processors for
Advanced Connected Radio, Entry Infotainment, and Cluster as well
as high end industrial and general purpose applications.
This patch adds vybrid CPU support.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
Makefile | 8 +
arch/arm/cpu/armv7/vybrid-common/Makefile | 46 ++
arch/arm/cpu/armv7/vybrid-common/cpu.c | 127 ++++
arch/arm/cpu/armv7/vybrid-common/speed.c | 37 ++
arch/arm/cpu/armv7/vybrid-common/timer.c | 140 +++++
arch/arm/cpu/armv7/vybrid/Makefile | 45 ++
arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 +++
arch/arm/cpu/armv7/vybrid/clock.c | 278 +++++++++
arch/arm/cpu/armv7/vybrid/iomux.c | 42 ++
arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 128 ++++
arch/arm/cpu/armv7/vybrid/soc.c | 42 ++
arch/arm/include/asm/arch-vybrid/clock.h | 41 ++
arch/arm/include/asm/arch-vybrid/iomux.h | 323 ++++++++++
arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213 +++++++
arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 +
arch/arm/include/asm/arch-vybrid/timer.h | 405 +++++++++++++
arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 +++
arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735 +++++++++++++++++++++++
arch/arm/include/asm/global_data.h | 3 +
arch/arm/include/asm/mach-types.h | 56 ++
20 files changed, 2857 insertions(+)
create mode 100644 arch/arm/cpu/armv7/vybrid-common/Makefile
create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c
create mode 100644 arch/arm/cpu/armv7/vybrid/iomux.c
create mode 100644 arch/arm/cpu/armv7/vybrid/lowlevel_init.S
create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c
create mode 100644 arch/arm/include/asm/arch-vybrid/clock.h
create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
diff --git a/Makefile b/Makefile
index 12763ce..8a86951 100644
--- a/Makefile
+++ b/Makefile
@@ -334,6 +334,9 @@ LIBS-y += test/libtest.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
+ifeq ($(SOC),vybrid)
+LIBS-y += $(CPUDIR)/vybrid-common/libvybrid-common.o
+endif
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
@@ -467,6 +470,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin
$(obj)u-boot.imx: $(obj)u-boot.bin depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
+$(obj)u-boot.vybrid: $(obj)u-boot.bin
+ $(obj)tools/mkimage -n $(CONFIG_VYBRID_CONFIG) -T imximage \
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
@@ -855,6 +862,7 @@ clobber: tidy
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
+ @rm -f $(obj)u-boot.vybrid
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
diff --git a/arch/arm/cpu/armv7/vybrid-common/Makefile b/arch/arm/cpu/armv7/vybrid-common/Makefile
new file mode 100644
index 0000000..bee8850
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright 2012-2013 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libvybrid-common.o
+
+COBJS := timer.o
+COBJS += cpu.o
+COBJS += speed.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c
new file mode 100644
index 0000000..f99083e
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+static char *get_reset_cause(void)
+{
+ char *resetcause[32] = {"POR",
+ "Cortex A5 WDOG Timer Reset",
+ 0,
+ "CA5 WDOG reset",
+ "CM4 WDOG reset",
+ "JTAG HIGH-Z",
+ 0,
+ "External Reset",
+ "1.2V supply below 0.7V",
+ "HP regulator's LVD",
+ "ULP regulator's LVD",
+ "3.3V main supply is unstable",
+ "LP regulator's LVD",
+ 0,
+ 0,
+ 0,
+ "MDM-AP system reset request is set",
+ "Hard Fail State of System Security Monitor",
+ "SRC_SCR SW Reset is set",
+ "Platform's CSU alarm event",
+ 0,
+ 0,
+ 0,
+ 0,
+ "Anadig regulator 1.1V unstable",
+ "Anadig regulator 2.5V unstable",
+ "Anadig regulator 3.0V unstable",
+ "CMU even when FOSC freq less than 40MHz",
+ "CMU event when BUS freq is out of range",
+ "No clock is detected on FOSC",
+ "No clock is detected on SOSC",
+ "CM4 is in lockup"};
+ u32 cause;
+ int i, bit;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+
+ for (i = 0; i < 32; i++) {
+ bit = 1 << i;
+ if ((cause & bit) == bit) {
+ if (resetcause[i] != NULL)
+ return resetcause[i];
+ }
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale VyBrid %x family rev%d.%d@%d MHz\n",
+ (cpurev & 0xFFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+ rc = mcffec_initialize(bis);
+
+ return rc;
+}
+
+/* Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG_A5_BASE_ADDR);
+}
diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c b/arch/arm/cpu/armv7/vybrid-common/speed.c
new file mode 100644
index 0000000..3be85ea
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/speed.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_clocks(void)
+{
+ gd->bus_clk = vybrid_get_clock(VYBRID_BUS_CLK);
+ gd->arch.ipg_clk = vybrid_get_clock(VYBRID_IPG_CLK);
+
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = vybrid_get_clock(VYBRID_SDHC_CLK);
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c b/arch/arm/cpu/armv7/vybrid-common/timer.c
new file mode 100644
index 0000000..be990e6
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/vybrid-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->arch.tbl)
+#define timerticks (gd->arch.tbu)
+#define lastinc (gd->arch.lastinc)
+static unsigned long ltmstamp;
+
+#define CONFIG_TMR_USEPIT
+#ifdef CONFIG_TMR_USEPIT
+
+int timer_init(void)
+{
+ ulong usecs;
+ ulong ticks;
+
+ timestamp = 0;
+
+ /*
+ * nsecs conversion = (1/ipg_clk) * 10^9
+ * equivalent to 1000 / (ipg_clk / 10^6)
+ */
+ usecs = (vybrid_get_clock(VYBRID_IPG_CLK) / 1000000);
+ ticks = 1000 / usecs;
+
+ clrbits_le32(PIT_MCR, 2); /* enable PIT */
+
+ /* ticks per 10 us = 10000 us / usecs = cycles time */
+ timerticks = (10 * 1000) / ticks;
+
+ __raw_writel(0xFFFFFFFF, PIT_LDVAL1);
+ __raw_writel(0, PIT_TCTRL1);
+ __raw_writel(4, PIT_TCTRL1);
+ __raw_writel(5, PIT_TCTRL1);
+ __raw_writel(timerticks, PIT_LDVAL0);
+ __raw_writel(1, PIT_TCTRL0);
+
+ lastinc = __raw_readl(PIT_LTMR64H);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned long now, diff;
+
+ now = __raw_readl(PIT_LTMR64H);
+ diff = -(now - lastinc);
+ ltmstamp += diff;
+ while (ltmstamp > 100) {
+ timestamp++;
+ ltmstamp -= 100;
+ }
+ lastinc = now;
+
+ return timestamp - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+ ulong nsecs, tmp;
+
+ /*
+ * nsecs conversion = (1/ipg_clk) * 10^9
+ * equivalent to 1000 / (ipg_clk / 10^6)
+ */
+ if (usec < 5)
+ usec = 10;
+
+ nsecs = gd->arch.ipg_clk / 1000000;
+ nsecs = 1000 / nsecs;
+
+ /* 1 us per ticks = 1000 ns / nsecs = cycles time */
+ while (usec > 0) {
+ if (usec > 65000)
+ tmp = 65000;
+ else
+ tmp = usec;
+ usec = usec - tmp;
+
+ tmp = (tmp * 1000) / nsecs;
+
+ __raw_writel(tmp, PIT_LDVAL2);
+ __raw_writel(1, PIT_TCTRL2);
+
+ while ((__raw_readl(PIT_TFLG2) & 1) != 1)
+ ;
+ __raw_writel(0, PIT_TCTRL2);
+ __raw_writel(1, PIT_TFLG2);
+ }
+}
+#endif /* CONFIG_TMR_USEPIT */
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long long _usec2ticks(unsigned long long usec)
+{
+ return usec;
+}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/vybrid/Makefile b/arch/arm/cpu/armv7/vybrid/Makefile
new file mode 100644
index 0000000..f71e3fb
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2012-2013 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS = soc.o clock.o iomux.o
+SOBJS = lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/vybrid/asm-offsets.c b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
new file mode 100644
index 0000000..2951f78
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/vybrid-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ /* Round up to make sure size gives nice stack alignment */
+ DEFINE(CLKCTL_CCR, offsetof(struct clkctl, ccr));
+ DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
+ DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
+ DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
+ DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
+ DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
+ DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
+ DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
+ DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
+ DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
+ DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
+ DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
+ DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
+ DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
+ DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
+
+ DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
+ DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
+ DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
+ DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
+ DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
+ DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
+ DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
+ DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
+ DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
+ DEFINE(CLKCTL_CCGR8, offsetof(struct clkctl, ccgr8));
+ DEFINE(CLKCTL_CCGR9, offsetof(struct clkctl, ccgr9));
+ DEFINE(CLKCTL_CCGR10, offsetof(struct clkctl, ccgr10));
+ DEFINE(CLKCTL_CCGR11, offsetof(struct clkctl, ccgr11));
+ DEFINE(CLKCTL_CMEOR0, offsetof(struct clkctl, cmeor0));
+ DEFINE(CLKCTL_CMEOR1, offsetof(struct clkctl, cmeor1));
+ DEFINE(CLKCTL_CMEOR2, offsetof(struct clkctl, cmeor2));
+ DEFINE(CLKCTL_CMEOR3, offsetof(struct clkctl, cmeor3));
+ DEFINE(CLKCTL_CMEOR4, offsetof(struct clkctl, cmeor4));
+ DEFINE(CLKCTL_CMEOR5, offsetof(struct clkctl, cmeor5));
+ DEFINE(CLKCTL_CPPDSR, offsetof(struct clkctl, cppdsr));
+ DEFINE(CLKCTL_CCOWR, offsetof(struct clkctl, ccowr));
+ DEFINE(CLKCTL_CCPGR0, offsetof(struct clkctl, ccpgr0));
+ DEFINE(CLKCTL_CCPGR1, offsetof(struct clkctl, ccpgr1));
+ DEFINE(CLKCTL_CCPGR2, offsetof(struct clkctl, ccpgr2));
+ DEFINE(CLKCTL_CCPGR3, offsetof(struct clkctl, ccpgr3));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/vybrid/clock.c b/arch/arm/cpu/armv7/vybrid/clock.c
new file mode 100644
index 0000000..073b949
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/clock.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/clock.h>
+#include <div64.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum pll_clocks {
+ PLL1_CLOCK = 0,
+ PLL2_CLOCK,
+ PLL3_CLOCK,
+ PLL4_CLOCK,
+ PLL_CLOCKS,
+};
+
+struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+
+/* Get mcu main rate */
+static u32 get_mcu_main_clk(void)
+{
+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+ u32 ccm_ccsr, ccm_cacrr, armclk_div;
+ u32 sysclk_sel, pll_pfd_sel = 0;
+ u32 freq = 0;
+
+ ccm_ccsr = readl(&ccm->ccsr);
+ sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
+ sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+ armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
+ armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
+ armclk_div += 1;
+
+ switch (sysclk_sel) {
+ case 0:
+ freq = FASE_CLK_FREQ;
+ break;
+ case 1:
+ freq = SLOW_CLK_FREQ;
+ break;
+ case 3:
+ freq = PLL2_MAIN_FREQ;
+ break;
+ case 5:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ case 2:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
+ break;
+ case 4:
+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
+ pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
+ break;
+ default:
+ printf("unsupported system clock select\n");
+ }
+
+ if (sysclk_sel == 2) {
+ switch (pll_pfd_sel) {
+ case 0:
+ freq = PLL2_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL2_PFD1_FREQ;
+ break;
+ case 2:
+ freq = PLL2_PFD2_FREQ;
+ break;
+ case 3:
+ freq = PLL2_PFD3_FREQ;
+ break;
+ case 4:
+ freq = PLL2_PFD4_FREQ;
+ break;
+ default:
+ break;
+ }
+ } else if (sysclk_sel == 4) {
+ switch (pll_pfd_sel) {
+ case 0:
+ freq = PLL1_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL1_PFD1_FREQ;
+ break;
+ case 2:
+ freq = PLL1_PFD2_FREQ;
+ break;
+ case 3:
+ freq = PLL1_PFD3_FREQ;
+ break;
+ case 4:
+ freq = PLL1_PFD4_FREQ;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return freq / armclk_div;
+}
+
+/* Get the rate of bus clock */
+static u32 get_bus_clk(void)
+{
+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, busclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
+ busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
+ busclk_div += 1;
+
+ return get_mcu_main_clk() / busclk_div;
+}
+
+/* Get the rate of ipg clock */
+static u32 get_ipg_clk(void)
+{
+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+ u32 ccm_cacrr, ipgclk_div;
+
+ ccm_cacrr = readl(&ccm->cacrr);
+
+ ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
+ ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
+ ipgclk_div += 1;
+
+ return get_bus_clk() / ipgclk_div;
+}
+
+/* get dspi clock rate */
+static u32 vybrid_get_dspiclk(void)
+{
+ return get_ipg_clk();
+}
+
+/* The API of get vybrid clocks */
+unsigned int vybrid_get_clock(enum vybrid_clock clk)
+{
+ switch (clk) {
+ case VYBRID_ARM_CLK:
+ return get_mcu_main_clk();
+ case VYBRID_BUS_CLK:
+ return get_bus_clk();
+ case VYBRID_IPG_CLK:
+ return get_ipg_clk();
+ case VYBRID_UART_CLK:
+ return vybrid_get_uartclk();
+ case VYBRID_DSPI_CLK:
+ return vybrid_get_dspiclk();
+ case VYBRID_SDHC_CLK:
+ return vybrid_get_sdhcclk();
+ case VYBRID_FEC_CLK:
+ return vybrid_get_fecclk();
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* Get the rate of uart clk */
+u32 vybrid_get_uartclk(void)
+{
+ return get_ipg_clk();
+}
+
+/* Get the rate of uart clk */
+u32 vybrid_get_sdhcclk(void)
+{
+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+ u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
+ u32 freq = 0;
+
+ ccm_cscmr1 = readl(&ccm->cscmr1);
+ sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
+ sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+
+ ccm_cscdr2 = readl(&ccm->cscdr2);
+ sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
+ sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
+ sdhc_clk_div += 1;
+
+ switch (sdhc_clk_sel) {
+ case 0:
+ freq = PLL3_MAIN_FREQ;
+ break;
+ case 1:
+ freq = PLL3_PFD3_FREQ;
+ break;
+ case 2:
+ freq = PLL1_PFD3_FREQ;
+ break;
+ case 3:
+ freq = get_bus_clk();
+ break;
+ }
+
+ return freq / sdhc_clk_div;
+}
+
+u32 vybrid_get_fecclk(void)
+{
+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
+ u32 ccm_cscmr2, rmii_clk_sel;
+ u32 freq = 0;
+
+ ccm_cscmr2 = readl(&ccm->cscmr2);
+ rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
+ rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
+
+ switch (rmii_clk_sel) {
+ case 0:
+ freq = ENET_EXTERNAL_CLK;
+ break;
+ case 1:
+ freq = AUDIO_EXTERNAL_CLK;
+ break;
+ case 2:
+ freq = PLL5_MAIN_FREQ;
+ break;
+ case 3:
+ freq = PLL5_MAIN_FREQ / 2;
+ break;
+ }
+
+ return freq;
+}
+
+/* Dump some core clocks */
+int do_vybrid_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ printf("\n");
+ printf("ARM %8d kHz\n",
+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000);
+ printf("BUS %8d kHz\n",
+ vybrid_get_clock(VYBRID_BUS_CLK) / 1000);
+ printf("IPG %8d kHz\n",
+ vybrid_get_clock(VYBRID_IPG_CLK) / 1000);
+
+ return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_vybrid_showclocks,
+ "display clocks",
+ ""
+);
diff --git a/arch/arm/cpu/armv7/vybrid/iomux.c b/arch/arm/cpu/armv7/vybrid/iomux.c
new file mode 100644
index 0000000..fb672e3
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/iomux.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/vybrid-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio)
+{
+ u32 value;
+
+ value = (((padio->mod & 7) << 20) | ((padio->spd & 3) << 12) | \
+ ((padio->sre & 1) << 11) | ((padio->ode & 1) << 10) | \
+ ((padio->hys & 1) << 9) | ((padio->dse & 7) << 6) | \
+ ((padio->pus & 3) << 4) | ((padio->pke & 1) << 3) | \
+ ((padio->pue & 1) << 2) | ((padio->obe & 1) << 1) | \
+ ((padio->ibe & 1) << 0));
+
+ __raw_writel(pad_addr, value);
+}
diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
new file mode 100644
index 0000000..c2bda4f
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/vybrid-regs.h>
+#include <generated/asm-offsets.h>
+
+/* DDR */
+.macro init_drive_strength
+.endm /* init_drive_strength */
+
+.macro setup_pll pll, freq
+.endm
+
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CLPCR
+ str r1, [r0, #CLKCTL_CLPCR]
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR0
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR1
+ str r1, [r0, #CLKCTL_CCGR1]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR2
+ str r1, [r0, #CLKCTL_CCGR2]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR3
+ str r1, [r0, #CLKCTL_CCGR3]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR4
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR5
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR6
+ str r1, [r0, #CLKCTL_CCGR6]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR7
+ str r1, [r0, #CLKCTL_CCGR7]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR8
+ str r1, [r0, #CLKCTL_CCGR8]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR9
+ str r1, [r0, #CLKCTL_CCGR9]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR10
+ str r1, [r0, #CLKCTL_CCGR10]
+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR11
+ str r1, [r0, #CLKCTL_CCGR11]
+
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r1, =CONFIG_SYS_ANADIG_528_CTRL
+ str r1, [r2, #0x30]
+ ldr r1, =CONFIG_SYS_ANADIG_ENET_CTRL
+ str r1, [r2, #0xE0]
+ ldr r1, =CONFIG_SYS_ANADIG_SYS_CTRL
+ str r1, [r2, #0x270]
+ /* check for lock */
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CCR
+ str r1, [r0, #CLKCTL_CCR]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CCSR
+ str r1, [r0, #CLKCTL_CCSR]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CACRR
+ str r1, [r0, #CLKCTL_CACRR]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR1
+ str r1, [r0, #CLKCTL_CSCMR1]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR1
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR2
+ str r1, [r0, #CLKCTL_CSCDR2]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR3
+ str r1, [r0, #CLKCTL_CSCDR3]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR2
+ str r1, [r0, #CLKCTL_CSCMR2]
+
+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR4
+ str r1, [r0, #CLKCTL_CSCDR4]
+.endm
+
+.macro setup_wdog
+ ldr r0, =WDOG_A5_BASE_ADDR
+ mov r1, #0x30
+ strh r1, [r0]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+ /* ARM errata ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+
+#ifndef CONFIG_SYS_BOOTHDR
+ init_clock
+#endif
+
+ /* r12 saved upper lr*/
+ mov pc,lr
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD: .word 0x04008008
+DDR_REFRESH_CMD: .word 0x00008010
+DDR_LMR1_W: .word 0x00338018
+DDR_LMR_CMD: .word 0xB2220000
+DDR_TIMING_W: .word 0xB02567A9
+DDR_MISC_W: .word 0x000A0104
diff --git a/arch/arm/cpu/armv7/vybrid/soc.c b/arch/arm/cpu/armv7/vybrid/soc.c
new file mode 100644
index 0000000..e73d6c4
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid/soc.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#if !(defined(CONFIG_VYBRID))
+#error "CPU_TYPE not defined"
+#endif
+
+u32 get_cpu_rev(void)
+{
+ int system_rev = 0x600000;
+ int reg = __raw_readl(ROM_SI_REV);
+
+ system_rev |= reg;
+ return system_rev;
+}
diff --git a/arch/arm/include/asm/arch-vybrid/clock.h b/arch/arm/include/asm/arch-vybrid/clock.h
new file mode 100644
index 0000000..bf95b13
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/clock.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum vybrid_clock {
+ VYBRID_ARM_CLK = 0,
+ VYBRID_BUS_CLK,
+ VYBRID_IPG_CLK,
+ VYBRID_UART_CLK,
+ VYBRID_DSPI_CLK,
+ VYBRID_SDHC_CLK,
+ VYBRID_FEC_CLK,
+};
+
+u32 vybrid_get_uartclk(void);
+u32 vybrid_get_sdhcclk(void);
+u32 vybrid_get_fecclk(void);
+unsigned int vybrid_get_clock(enum vybrid_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h b/arch/arm/include/asm/arch-vybrid/iomux.h
new file mode 100644
index 0000000..94f8b0b
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/iomux.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_VYBRID_IOMUX_H__
+#define __MACH_VYBRID_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/vybrid-pins.h>
+
+#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000)
+#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004)
+#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008)
+#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C)
+#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010)
+#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014)
+#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018)
+#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C)
+#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020)
+#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024)
+#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028)
+#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C)
+#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030)
+#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034)
+#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038)
+#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C)
+#define IOMUXC_PAD_016 (IOMUXC_BASE_ADDR + 0x0040)
+#define IOMUXC_PAD_017 (IOMUXC_BASE_ADDR + 0x0044)
+#define IOMUXC_PAD_018 (IOMUXC_BASE_ADDR + 0x0048)
+#define IOMUXC_PAD_019 (IOMUXC_BASE_ADDR + 0x004C)
+#define IOMUXC_PAD_020 (IOMUXC_BASE_ADDR + 0x0050)
+#define IOMUXC_PAD_021 (IOMUXC_BASE_ADDR + 0x0054)
+#define IOMUXC_PAD_022 (IOMUXC_BASE_ADDR + 0x0058)
+#define IOMUXC_PAD_023 (IOMUXC_BASE_ADDR + 0x005C)
+#define IOMUXC_PAD_024 (IOMUXC_BASE_ADDR + 0x0060)
+#define IOMUXC_PAD_025 (IOMUXC_BASE_ADDR + 0x0064)
+#define IOMUXC_PAD_026 (IOMUXC_BASE_ADDR + 0x0068)
+#define IOMUXC_PAD_027 (IOMUXC_BASE_ADDR + 0x006C)
+#define IOMUXC_PAD_028 (IOMUXC_BASE_ADDR + 0x0070)
+#define IOMUXC_PAD_029 (IOMUXC_BASE_ADDR + 0x0074)
+#define IOMUXC_PAD_030 (IOMUXC_BASE_ADDR + 0x0078)
+#define IOMUXC_PAD_031 (IOMUXC_BASE_ADDR + 0x007C)
+#define IOMUXC_PAD_032 (IOMUXC_BASE_ADDR + 0x0080)
+#define IOMUXC_PAD_033 (IOMUXC_BASE_ADDR + 0x0084)
+#define IOMUXC_PAD_034 (IOMUXC_BASE_ADDR + 0x0088)
+#define IOMUXC_PAD_035 (IOMUXC_BASE_ADDR + 0x008C)
+#define IOMUXC_PAD_036 (IOMUXC_BASE_ADDR + 0x0090)
+#define IOMUXC_PAD_037 (IOMUXC_BASE_ADDR + 0x0094)
+#define IOMUXC_PAD_038 (IOMUXC_BASE_ADDR + 0x0098)
+#define IOMUXC_PAD_039 (IOMUXC_BASE_ADDR + 0x009C)
+#define IOMUXC_PAD_040 (IOMUXC_BASE_ADDR + 0x00A0)
+#define IOMUXC_PAD_041 (IOMUXC_BASE_ADDR + 0x00A4)
+#define IOMUXC_PAD_042 (IOMUXC_BASE_ADDR + 0x00A8)
+#define IOMUXC_PAD_043 (IOMUXC_BASE_ADDR + 0x00AC)
+#define IOMUXC_PAD_044 (IOMUXC_BASE_ADDR + 0x00B0)
+#define IOMUXC_PAD_045 (IOMUXC_BASE_ADDR + 0x00B4)
+#define IOMUXC_PAD_046 (IOMUXC_BASE_ADDR + 0x00B8)
+#define IOMUXC_PAD_047 (IOMUXC_BASE_ADDR + 0x00BC)
+#define IOMUXC_PAD_048 (IOMUXC_BASE_ADDR + 0x00C0)
+#define IOMUXC_PAD_049 (IOMUXC_BASE_ADDR + 0x00C4)
+#define IOMUXC_PAD_050 (IOMUXC_BASE_ADDR + 0x00C8)
+#define IOMUXC_PAD_051 (IOMUXC_BASE_ADDR + 0x00CC)
+#define IOMUXC_PAD_052 (IOMUXC_BASE_ADDR + 0x00D0)
+#define IOMUXC_PAD_053 (IOMUXC_BASE_ADDR + 0x00D4)
+#define IOMUXC_PAD_054 (IOMUXC_BASE_ADDR + 0x00D8)
+#define IOMUXC_PAD_055 (IOMUXC_BASE_ADDR + 0x00DC)
+#define IOMUXC_PAD_056 (IOMUXC_BASE_ADDR + 0x00E0)
+#define IOMUXC_PAD_057 (IOMUXC_BASE_ADDR + 0x00E4)
+#define IOMUXC_PAD_058 (IOMUXC_BASE_ADDR + 0x00E8)
+#define IOMUXC_PAD_059 (IOMUXC_BASE_ADDR + 0x00EC)
+#define IOMUXC_PAD_060 (IOMUXC_BASE_ADDR + 0x00F0)
+#define IOMUXC_PAD_061 (IOMUXC_BASE_ADDR + 0x00F4)
+#define IOMUXC_PAD_062 (IOMUXC_BASE_ADDR + 0x00F8)
+#define IOMUXC_PAD_063 (IOMUXC_BASE_ADDR + 0x00FC)
+#define IOMUXC_PAD_064 (IOMUXC_BASE_ADDR + 0x0100)
+#define IOMUXC_PAD_065 (IOMUXC_BASE_ADDR + 0x0104)
+#define IOMUXC_PAD_066 (IOMUXC_BASE_ADDR + 0x0108)
+#define IOMUXC_PAD_067 (IOMUXC_BASE_ADDR + 0x010C)
+#define IOMUXC_PAD_068 (IOMUXC_BASE_ADDR + 0x0110)
+#define IOMUXC_PAD_069 (IOMUXC_BASE_ADDR + 0x0114)
+#define IOMUXC_PAD_070 (IOMUXC_BASE_ADDR + 0x0118)
+#define IOMUXC_PAD_071 (IOMUXC_BASE_ADDR + 0x011C)
+#define IOMUXC_PAD_072 (IOMUXC_BASE_ADDR + 0x0120)
+#define IOMUXC_PAD_073 (IOMUXC_BASE_ADDR + 0x0124)
+#define IOMUXC_PAD_074 (IOMUXC_BASE_ADDR + 0x0128)
+#define IOMUXC_PAD_075 (IOMUXC_BASE_ADDR + 0x012C)
+#define IOMUXC_PAD_076 (IOMUXC_BASE_ADDR + 0x0130)
+#define IOMUXC_PAD_077 (IOMUXC_BASE_ADDR + 0x0134)
+#define IOMUXC_PAD_078 (IOMUXC_BASE_ADDR + 0x0138)
+#define IOMUXC_PAD_079 (IOMUXC_BASE_ADDR + 0x013C)
+#define IOMUXC_PAD_080 (IOMUXC_BASE_ADDR + 0x0140)
+#define IOMUXC_PAD_081 (IOMUXC_BASE_ADDR + 0x0144)
+#define IOMUXC_PAD_082 (IOMUXC_BASE_ADDR + 0x0148)
+#define IOMUXC_PAD_083 (IOMUXC_BASE_ADDR + 0x014C)
+#define IOMUXC_PAD_084 (IOMUXC_BASE_ADDR + 0x0150)
+#define IOMUXC_PAD_085 (IOMUXC_BASE_ADDR + 0x0154)
+#define IOMUXC_PAD_086 (IOMUXC_BASE_ADDR + 0x0158)
+#define IOMUXC_PAD_087 (IOMUXC_BASE_ADDR + 0x015C)
+#define IOMUXC_PAD_088 (IOMUXC_BASE_ADDR + 0x0160)
+#define IOMUXC_PAD_089 (IOMUXC_BASE_ADDR + 0x0164)
+#define IOMUXC_PAD_090 (IOMUXC_BASE_ADDR + 0x0168)
+#define IOMUXC_PAD_091 (IOMUXC_BASE_ADDR + 0x016C)
+#define IOMUXC_PAD_092 (IOMUXC_BASE_ADDR + 0x0170)
+#define IOMUXC_PAD_093 (IOMUXC_BASE_ADDR + 0x0174)
+#define IOMUXC_PAD_094 (IOMUXC_BASE_ADDR + 0x0178)
+#define IOMUXC_PAD_095 (IOMUXC_BASE_ADDR + 0x017C)
+#define IOMUXC_PAD_096 (IOMUXC_BASE_ADDR + 0x0180)
+#define IOMUXC_PAD_097 (IOMUXC_BASE_ADDR + 0x0184)
+#define IOMUXC_PAD_098 (IOMUXC_BASE_ADDR + 0x0188)
+#define IOMUXC_PAD_099 (IOMUXC_BASE_ADDR + 0x018C)
+#define IOMUXC_PAD_100 (IOMUXC_BASE_ADDR + 0x0190)
+#define IOMUXC_PAD_101 (IOMUXC_BASE_ADDR + 0x0194)
+#define IOMUXC_PAD_102 (IOMUXC_BASE_ADDR + 0x0198)
+#define IOMUXC_PAD_103 (IOMUXC_BASE_ADDR + 0x019C)
+#define IOMUXC_PAD_104 (IOMUXC_BASE_ADDR + 0x01A0)
+#define IOMUXC_PAD_105 (IOMUXC_BASE_ADDR + 0x01A4)
+#define IOMUXC_PAD_106 (IOMUXC_BASE_ADDR + 0x01A8)
+#define IOMUXC_PAD_107 (IOMUXC_BASE_ADDR + 0x01AC)
+#define IOMUXC_PAD_108 (IOMUXC_BASE_ADDR + 0x01B0)
+#define IOMUXC_PAD_109 (IOMUXC_BASE_ADDR + 0x01B4)
+#define IOMUXC_PAD_110 (IOMUXC_BASE_ADDR + 0x01B8)
+#define IOMUXC_PAD_111 (IOMUXC_BASE_ADDR + 0x01BC)
+#define IOMUXC_PAD_112 (IOMUXC_BASE_ADDR + 0x01C0)
+#define IOMUXC_PAD_113 (IOMUXC_BASE_ADDR + 0x01C4)
+#define IOMUXC_PAD_114 (IOMUXC_BASE_ADDR + 0x01C8)
+#define IOMUXC_PAD_115 (IOMUXC_BASE_ADDR + 0x01CC)
+#define IOMUXC_PAD_116 (IOMUXC_BASE_ADDR + 0x01D0)
+#define IOMUXC_PAD_117 (IOMUXC_BASE_ADDR + 0x01D4)
+#define IOMUXC_PAD_118 (IOMUXC_BASE_ADDR + 0x01D8)
+#define IOMUXC_PAD_119 (IOMUXC_BASE_ADDR + 0x01DC)
+#define IOMUXC_PAD_120 (IOMUXC_BASE_ADDR + 0x01E0)
+#define IOMUXC_PAD_121 (IOMUXC_BASE_ADDR + 0x01E4)
+#define IOMUXC_PAD_122 (IOMUXC_BASE_ADDR + 0x01E8)
+#define IOMUXC_PAD_123 (IOMUXC_BASE_ADDR + 0x01EC)
+#define IOMUXC_PAD_124 (IOMUXC_BASE_ADDR + 0x01F0)
+#define IOMUXC_PAD_125 (IOMUXC_BASE_ADDR + 0x01F4)
+#define IOMUXC_PAD_126 (IOMUXC_BASE_ADDR + 0x01F8)
+#define IOMUXC_PAD_127 (IOMUXC_BASE_ADDR + 0x01FC)
+#define IOMUXC_PAD_128 (IOMUXC_BASE_ADDR + 0x0200)
+#define IOMUXC_PAD_129 (IOMUXC_BASE_ADDR + 0x0204)
+#define IOMUXC_PAD_130 (IOMUXC_BASE_ADDR + 0x0208)
+#define IOMUXC_PAD_131 (IOMUXC_BASE_ADDR + 0x020C)
+#define IOMUXC_PAD_132 (IOMUXC_BASE_ADDR + 0x0210)
+#define IOMUXC_PAD_133 (IOMUXC_BASE_ADDR + 0x0214)
+#define IOMUXC_PAD_134 (IOMUXC_BASE_ADDR + 0x0218)
+
+#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C)
+#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220)
+#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224)
+#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228)
+#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C)
+#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230)
+#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234)
+#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238)
+#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C)
+#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240)
+#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244)
+#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248)
+#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C)
+#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250)
+#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254)
+#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258)
+#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C)
+
+#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260)
+#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264)
+#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268)
+
+#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C)
+
+#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270)
+
+#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274)
+
+#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278)
+
+#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C)
+#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280)
+#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284)
+#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288)
+#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C)
+#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290)
+#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294)
+#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298)
+#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C)
+#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0)
+#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4)
+#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8)
+#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC)
+#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0)
+#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4)
+#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8)
+
+#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC)
+#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0)
+
+#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4)
+#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8)
+
+#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC)
+#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0)
+
+#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4)
+#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8)
+
+#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC)
+#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0)
+
+#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4)
+#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8)
+
+#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC)
+#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0)
+#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4)
+
+struct pad_iomux {
+ u8 mod;
+ u8 spd;
+ u8 sre;
+ u8 ode;
+ u8 hys;
+ u8 dse;
+ u8 pus;
+ u8 pke;
+ u8 pue;
+ u8 obe;
+ u8 ibe;
+};
+
+#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, \
+ dse, pus, pke, pue, obe, ibe) \
+ (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \
+ ((sre & 1) << 11) | ((ode & 1) << 10) | \
+ ((hys & 1) << 9) | ((dse & 7) << 6) | \
+ ((pus & 3) << 4) | ((pke & 1) << 3) | \
+ ((pue & 1) << 2) | ((obe & 1) << 1) | \
+ (ibe & 1)))
+
+#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \
+ (((inp & 1) << 16) | ((trim & 3) << 14) | \
+ ((hys & 1) << 9) | ((dse & 7) << 6) | \
+ ((pus & 3) << 4) | ((pke & 1) << 3) | \
+ ((pue & 1) << 2))
+
+#define MUX_MODE_ALT0 0x00
+#define MUX_MODE_ALT1 0x01
+#define MUX_MODE_ALT2 0x02
+#define MUX_MODE_ALT3 0x03
+#define MUX_MODE_ALT4 0x04
+#define MUX_MODE_ALT5 0x05
+#define MUX_MODE_ALT6 0x06
+#define MUX_MODE_ALT7 0x07
+
+#define MUX_SPD_50MHZ 0x00
+#define MUX_SPD_100MHZ 0x02
+#define MUX_SPD_200MHZ 0x03
+
+#define MUX_SRE_SLOW 0
+#define MUX_SRE_FAST 1
+
+#define MUX_ODE_CMOS 0
+#define MUX_ODE_OPEN 1
+
+#define MUX_HYS_CMOS 0
+#define MUX_HYS_SCHMITT 1
+
+#define MUX_DSE_20_OHM 7
+#define MUX_DSE_25_OHM 6
+#define MUX_DSE_30_OHM 5
+#define MUX_DSE_37_OHM 4
+#define MUX_DSE_50_OHM 3
+#define MUX_DSE_75_OHM 2
+#define MUX_DSE_150_OHM 1
+#define MUX_DSE_DIS 0
+
+#define MUX_PUS_22KOHM_UP 3
+#define MUX_PUS_100KOHM_UP 2
+#define MUX_PUS_47KOHM_UP 1
+#define MUX_PUS_100KOHM_DN 0
+
+#define MUX_PKE_EN 1
+#define MUX_PKE_DIS 0
+
+#define MUX_PUE_PULLEN 1
+#define MUX_PUE_KEEPEREN 0
+
+#define MUX_OBE_EN 1
+#define MUX_OBE_DIS 0
+
+#define MUX_IBE_EN 1
+#define MUX_IBE_DIS 0
+
+#define MUX_DDR_INPUT_DIFF 1
+#define MUX_DDR_INPUT_CMOS 0
+
+#define MUX_DDR_TRIM_150PS 3
+#define MUX_DDR_TRIM_100PS 2
+#define MUX_DDR_TRIM_50PS 1
+#define MUX_DDR_TRIM_MIN 0
+
+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio);
+
+#endif /* __MACH_VYBRID_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-vybrid/serial-vybrid.h b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
new file mode 100644
index 0000000..9575f73
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SERIAL_VYBRID_H__
+#define __SERIAL_VYBRID_H__
+
+#define UBDH 0x00
+#define UBDL 0x01
+#define UC1 0x02
+#define UC2 0x03
+#define US1 0x04
+#define US2 0x05
+#define UC3 0x06
+#define UD 0x07
+#define UMA1 0x08
+#define UMA2 0x09
+#define UC4 0x0A
+#define UC5 0x0B
+#define UED 0x0C
+#define UMODEM 0x0D
+#define UIR 0x0E
+#define UPFIFO 0x10
+#define UCFIFO 0x11
+#define USFIFO 0x12
+#define UTWFIFO 0x13
+#define UTCFIFO 0x14
+#define URWFIFO 0x15
+#define URCFIFO 0x16
+#define UC7816 0x18
+#define UIE7816 0x19
+#define UIS7816 0x1A
+#define UWP7816T0 0x1B
+#define UWP7816T1 0x1B
+#define UWN7816 0x1C
+#define UWF7816 0x1D
+#define UET78416 0x1E
+#define UTL7816 0x1F
+#define UC6 0x21
+#define UPCTH 0x22
+#define UPCTL 0x23
+#define UB1T 0x24
+#define USDTH 0x25
+#define USDTL 0x26
+#define UPRE 0x27
+#define UTPL 0x28
+#define UIE 0x29
+#define UWB 0x2A
+#define US3 0x2B
+#define US4 0x2C
+#define UPRL 0x2D
+#define URPREL 0x2E
+#define UCPW 0x2F
+#define URIDT 0x30
+#define UTIDT 0x31
+
+#define UBDH_LBKDIE (1 << 7)
+#define UBDH_RXEDGIE (1 << 6)
+#define UBDH_SBR(x) (x & 0x1F)
+
+#define UC1_LOOPS (1 << 7)
+#define UC1_SWAI (1 << 6)
+#define UC1_RSRC (1 << 5)
+#define UC1_M (1 << 4)
+#define UC1_WAKE (1 << 3)
+#define UC1_ILT (1 << 2)
+#define UC1_PE (1 << 1)
+#define UC1_PT (1 << 0)
+
+#define UC2_TIE (1 << 7)
+#define UC2_TCIE (1 << 6)
+#define UC2_RIE (1 << 5)
+#define UC2_ILIE (1 << 4)
+#define UC2_TE (1 << 3)
+#define UC2_RE (1 << 2)
+#define UC2_RWU (1 << 1)
+#define UC2_SBK (1 << 0)
+
+#define US1_TDRE (1 << 7)
+#define US1_TC (1 << 6)
+#define US1_RDRF (1 << 5)
+#define US1_IDLE (1 << 4)
+#define US1_OR (1 << 3)
+#define US1_NF (1 << 2)
+#define US1_FE (1 << 1)
+#define US1_PF (1 << 0)
+
+#define US2_LBKDIF (1 << 7)
+#define US2_RXEDGIF (1 << 6)
+#define US2_MSBF (1 << 5)
+#define US2_RXINV (1 << 4)
+#define US2_RWUID (1 << 3)
+#define US2_BRK13 (1 << 2)
+#define US2_RBKDE (1 << 1)
+#define US2_RAF (1 << 0)
+
+#define UC3_R8 (1 << 7)
+#define UC3_T8 (1 << 6)
+#define UC3_TXDIR (1 << 5)
+#define UC3_TXINV (1 << 4)
+#define UC3_ORIE (1 << 3)
+#define UC3_NEIF (1 << 2)
+#define UC3_FEIF (1 << 1)
+#define UC3_PEIE (1 << 0)
+
+#define UC4_MAEN1 (1 << 7)
+#define UC4_MAEN2 (1 << 6)
+#define UC4_M10 (1 << 5)
+#define UC4_BRFA(x) (x & 0x1F)
+
+#define UC5_TDMAS (1 << 7)
+#define UC5_RDMAS (1 << 5)
+
+#define UED_NOISY (1 << 7)
+#define UED_PARITYE (1 << 6)
+
+#define UMODEM_RXRTSE (1 << 3)
+#define UMODEM_TXRTSPOL (1 << 2)
+#define UMODEM_TXRTSE (1 << 1)
+#define UMODEM_TXCTSE (1 << 0)
+
+#define UIR_IREN (1 << 2)
+#define UIR_TNP(x) (x & 3)
+
+#define UPFIFO_TXFE (1 << 7)
+#define UPFIFO_TXFSZ(x) ((x & 7) << 4)
+#define UPFIFO_RXFE (1 << 3)
+#define UPFIFO_RXFSZ(x) ((x & 7) << 0)
+
+#define UCFIFO_TXFLUSH (1 << 7)
+#define UCFIFO_RXFLUSH (1 << 6)
+#define UCFIFO_TXOFE (1 << 1)
+#define UCFIFO_RXUFE (1 << 0)
+
+#define USFIFO_TXEMPT (1 << 7)
+#define USFIFO_RXEMPT (1 << 6)
+#define USFIFO_TXOF (1 << 1)
+#define USFIFO_RXUF (1 << 0)
+
+#define UC7816_ONACK (1 << 4)
+#define UC7816_ANACK (1 << 3)
+#define UC7816_INIT (1 << 2)
+#define UC7816_TTYPE (1 << 1)
+#define UC7816_7816E (1 << 0)
+
+#define UIE7816_WTE (1 << 7)
+#define UIE7816_CWTE (1 << 6)
+#define UIE7816_BWTE (1 << 5)
+#define UIE7816_INITDE (1 << 4)
+#define UIE7816_GTVE (1 << 2)
+#define UIE7816_TXTE (1 << 1)
+#define UIE7816_RXTE (1 << 0)
+
+#define UIS7816_WTE (1 << 7)
+#define UIS7816_CWTE (1 << 6)
+#define UIS7816_BWTE (1 << 5)
+#define UIS7816_INITDE (1 << 4)
+#define UIS7816_GTVE (1 << 2)
+#define UIS7816_TXTE (1 << 1)
+#define UIS7816_RXTE (1 << 0)
+
+#define UWP7816T1_CWI(x) ((x & 0xf) << 4)
+#define UWP7816T1_BWI(x) ((x & 0xf) << 0)
+
+#define UET78416_TXTHRESHOLD(x) ((x & 0xf) << 4)
+#define UET78416_RXTHRESHOLD(x) ((x & 0xf) << 0)
+
+#define UC6_EN709 (1 << 7)
+#define UC6_TX709 (1 << 6)
+#define UC6_CE (1 << 5)
+#define UC6_CP (1 << 4)
+
+#define UIE_WBEIE (1 << 6)
+#define UIE_ISDIE (1 << 5)
+#define UIE_PRXIE (1 << 4)
+#define UIE_PTXIE (1 << 3)
+#define UIE_PCTEIE (1 << 2)
+#define UIE_PSIE (1 << 1)
+#define UIE_TXFIE (1 << 0)
+
+#define US3_PEF (1 << 7)
+#define US3_WBEF (1 << 6)
+#define US3_ISD (1 << 5)
+#define US3_PRXF (1 << 4)
+#define US3_PTXF (1 << 3)
+#define US3_PCTEF (1 << 2)
+#define US3_PSF (1 << 1)
+#define US3_TXFF (1 << 0)
+
+#define US4_INITF (1 << 4)
+#define US4_CDET(x) ((x & 3) << 2)
+#define US4_ILCV (1 << 1)
+#define US4_FE (1 << 0)
+
+#endif /* __SERIAL_VYBRID_H__ */
diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h b/arch/arm/include/asm/arch-vybrid/sys_proto.h
new file mode 100644
index 0000000..7e2de97
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_cpu_rev(void);
+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+void sdelay(unsigned long);
+
+#endif
diff --git a/arch/arm/include/asm/arch-vybrid/timer.h b/arch/arm/include/asm/arch-vybrid/timer.h
new file mode 100644
index 0000000..55497e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/timer.h
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+struct ftm_regs {
+ u32 sc; /* 0x00 */
+ u32 cnt; /* 0x04 */
+ u32 mod; /* 0x08 */
+ u32 c0sc; /* 0x0C */
+ u32 c0v; /* 0x10 */
+ u32 c1sc; /* 0x14 */
+ u32 c1v; /* 0x18 */
+ u32 c2sc; /* 0x1C */
+ u32 c2v; /* 0x20 */
+ u32 c3sc; /* 0x24 */
+ u32 c3v; /* 0x28 */
+ u32 c4sc; /* 0x2C */
+ u32 c4v; /* 0x30 */
+ u32 c5sc; /* 0x34 */
+ u32 c5v; /* 0x38 */
+ u32 c6sc; /* 0x3C */
+ u32 c6v; /* 0x40 */
+ u32 c7sc; /* 0x44 */
+ u32 c7v; /* 0x48 */
+ u32 cntin; /* 0x4C */
+ u32 status; /* 0x50 */
+ u32 mode; /* 0x54 */
+ u32 sync; /* 0x58 */
+ u32 outinit; /* 0x5C */
+ u32 outmask; /* 0x60 */
+ u32 combine; /* 0x64 */
+ u32 deadtime; /* 0x68 */
+ u32 exttrig; /* 0x6C */
+ u32 pol; /* 0x70 */
+ u32 fms; /* 0x74 */
+ u32 filter; /* 0x78 */
+ u32 fltctrl; /* 0x7C */
+ u32 qdctrl; /* 0x80 */
+ u32 conf; /* 0x84 */
+ u32 fltpol; /* 0x88 */
+ u32 synconf; /* 0x8C */
+ u32 invctrl; /* 0x90 */
+ u32 swoctrl; /* 0x94 */
+ u32 pwmload; /* 0x98 */
+};
+
+struct pit2_regs {
+ u32 ldval; /* 0x00 */
+ u32 cval; /* 0x04 */
+ u32 tctrl; /* 0x08 */
+ u32 tflg; /* 0x0C */
+};
+
+struct pit_regs {
+ u32 mcr; /* 0x00 */
+ u32 rsvd0[55];
+ u32 ltmr64h; /* 0xE0 */
+ u32 ltmr64l; /* 0xE4 */
+ u32 rsvd1[6];
+ struct pit2_regs counter[8]; /* 0x100 */
+};
+
+struct lptmr_regs {
+ u32 csr; /* 0x00 */
+ u32 psr; /* 0x04 */
+ u32 cmr; /* 0x08 */
+ u32 cnr; /* 0x0C */
+};
+
+/* Flex Timer */
+#define FTM_SC (FTM_BASE_ADDR + 0x00)
+#define FTM_CNT (FTM_BASE_ADDR + 0x04)
+#define FTM_MOD (FTM_BASE_ADDR + 0x08)
+#define FTM_C0SC (FTM_BASE_ADDR + 0x0C)
+#define FTM_C0V (FTM_BASE_ADDR + 0x10)
+#define FTM_C1SC (FTM_BASE_ADDR + 0x14)
+#define FTM_C1V (FTM_BASE_ADDR + 0x18)
+#define FTM_C2SC (FTM_BASE_ADDR + 0x1C)
+#define FTM_C2V (FTM_BASE_ADDR + 0x20)
+#define FTM_C3SC (FTM_BASE_ADDR + 0x24)
+#define FTM_C3V (FTM_BASE_ADDR + 0x28)
+#define FTM_C4SC (FTM_BASE_ADDR + 0x2C)
+#define FTM_C4V (FTM_BASE_ADDR + 0x30)
+#define FTM_C5SC (FTM_BASE_ADDR + 0x34)
+#define FTM_C5V (FTM_BASE_ADDR + 0x38)
+#define FTM_C6SC (FTM_BASE_ADDR + 0x3C)
+#define FTM_C6V (FTM_BASE_ADDR + 0x40)
+#define FTM_C7SC (FTM_BASE_ADDR + 0x44)
+#define FTM_C7V (FTM_BASE_ADDR + 0x48)
+#define FTM_CNTIN (FTM_BASE_ADDR + 0x4C)
+#define FTM_STATUS (FTM_BASE_ADDR + 0x50)
+#define FTM_MODE (FTM_BASE_ADDR + 0x54)
+#define FTM_SYNC (FTM_BASE_ADDR + 0x58)
+#define FTM_OUTINIT (FTM_BASE_ADDR + 0x5C)
+#define FTM_OUTMASK (FTM_BASE_ADDR + 0x60)
+#define FTM_COMBINE (FTM_BASE_ADDR + 0x64)
+#define FTM_DEADTIME (FTM_BASE_ADDR + 0x68)
+#define FTM_EXTTRIG (FTM_BASE_ADDR + 0x6C)
+#define FTM_POL (FTM_BASE_ADDR + 0x70)
+#define FTM_FMS (FTM_BASE_ADDR + 0x74)
+#define FTM_FILTER (FTM_BASE_ADDR + 0x78)
+#define FTM_FLTCTRL (FTM_BASE_ADDR + 0x7C)
+#define FTM_QDCTRL (FTM_BASE_ADDR + 0x80)
+#define FTM_CONF (FTM_BASE_ADDR + 0x84)
+#define FTM_FLTPOL (FTM_BASE_ADDR + 0x88)
+#define FTM_SYNCONF (FTM_BASE_ADDR + 0x8C)
+#define FTM_INVCTRL (FTM_BASE_ADDR + 0x90)
+#define FTM_SWOCTRL (FTM_BASE_ADDR + 0x94)
+#define FTM_PWMLOAD (FTM_BASE_ADDR + 0x98)
+
+#define FTM_SC_TOF (1 << 7)
+#define FTM_SC_TOIE (1 << 6)
+#define FTM_SC_CPWMS (1 << 5)
+#define FTM_SC_CLKS(x) ((x & 3) << 3)
+#define FTM_SC_PS(x) ((x & 7) << 0)
+
+#define FTM_CNT_COUNT(x) (x & 0xFFFF)
+
+#define FTM_MOD_MOD(x) (x & 0xFFFF)
+
+#define FTM_CnSC_CHF (1 << 7)
+#define FTM_CnSC_CHIE (1 << 6)
+#define FTM_CnSC_MSB (1 << 5)
+#define FTM_CnSC_MSA (1 << 4)
+#define FTM_CnSC_ELSB (1 << 3)
+#define FTM_CnSC_ELSA (1 << 2)
+#define FTM_CnSC_DMA (1 << 0)
+
+#define FTM_CnV_VAL(x) (x & 0xFFFF)
+
+#define FTM_CNTIN_INIT(x) (x & 0xFFFF)
+
+#define FTM_STATUS_CH7F (1 << 7)
+#define FTM_STATUS_CH6F (1 << 6)
+#define FTM_STATUS_CH5F (1 << 5)
+#define FTM_STATUS_CH4F (1 << 4)
+#define FTM_STATUS_CH3F (1 << 3)
+#define FTM_STATUS_CH2F (1 << 2)
+#define FTM_STATUS_CH1F (1 << 1)
+#define FTM_STATUS_CH0F (1 << 0)
+
+#define FTM_MODE_FAULTIE (1 << 7)
+#define FTM_MODE_FAULTM(x) ((x & 3) << 5)
+#define FTM_MODE_CAPTEST (1 << 4)
+#define FTM_MODE_PWMSYNC (1 << 3)
+#define FTM_MODE_WPDIS (1 << 2)
+#define FTM_MODE_INIT (1 << 1)
+#define FTM_MODE_FTMEN (1 << 0)
+
+#define FTM_SYNC_SWSYNC (1 << 7)
+#define FTM_SYNC_TRIG2 (1 << 6)
+#define FTM_SYNC_TRIG1 (1 << 5)
+#define FTM_SYNC_TRIG0 (1 << 4)
+#define FTM_SYNC_SYNCHOM (1 << 3)
+#define FTM_SYNC_REINIT (1 << 2)
+#define FTM_SYNC_CNTMAX (1 << 1)
+#define FTM_SYNC_CNTMIN (1 << 0)
+
+#define FTM_OUTINIT_CH7OI (1 << 7)
+#define FTM_OUTINIT_CH6OI (1 << 6)
+#define FTM_OUTINIT_CH5OI (1 << 5)
+#define FTM_OUTINIT_CH4OI (1 << 4)
+#define FTM_OUTINIT_CH3OI (1 << 3)
+#define FTM_OUTINIT_CH2OI (1 << 2)
+#define FTM_OUTINIT_CH1OI (1 << 1)
+#define FTM_OUTINIT_CH0OI (1 << 0)
+
+#define FTM_OUTMASK_CH7OM (1 << 7)
+#define FTM_OUTMASK_CH6OM (1 << 6)
+#define FTM_OUTMASK_CH5OM (1 << 5)
+#define FTM_OUTMASK_CH4OM (1 << 4)
+#define FTM_OUTMASK_CH3OM (1 << 3)
+#define FTM_OUTMASK_CH2OM (1 << 2)
+#define FTM_OUTMASK_CH1OM (1 << 1)
+#define FTM_OUTMASK_CH0OM (1 << 0)
+
+#define FTM_COMBINE_FAULTEN3 (1 << 30)
+#define FTM_COMBINE_SYNCEN3 (1 << 29)
+#define FTM_COMBINE_DTEN3 (1 << 28)
+#define FTM_COMBINE_DECAP3 (1 << 27)
+#define FTM_COMBINE_DECAPEN3 (1 << 26)
+#define FTM_COMBINE_COMP3 (1 << 25)
+#define FTM_COMBINE_COMBINE3 (1 << 24)
+#define FTM_COMBINE_FAULTEN2 (1 << 22)
+#define FTM_COMBINE_SYNCEN2 (1 << 21)
+#define FTM_COMBINE_DTEN2 (1 << 20)
+#define FTM_COMBINE_DECAP2 (1 << 19)
+#define FTM_COMBINE_DECAPEN2 (1 << 18)
+#define FTM_COMBINE_COMP2 (1 << 17)
+#define FTM_COMBINE_COMBINE2 (1 << 16)
+#define FTM_COMBINE_FAULTEN1 (1 << 14)
+#define FTM_COMBINE_SYNCEN1 (1 << 13)
+#define FTM_COMBINE_DTEN1 (1 << 12)
+#define FTM_COMBINE_DECAP1 (1 << 11)
+#define FTM_COMBINE_DECAPEN1 (1 << 10)
+#define FTM_COMBINE_COMP1 (1 << 9)
+#define FTM_COMBINE_COMBINE1 (1 << 8)
+#define FTM_COMBINE_FAULTEN0 (1 << 6)
+#define FTM_COMBINE_SYNCEN0 (1 << 5)
+#define FTM_COMBINE_DTEN0 (1 << 4)
+#define FTM_COMBINE_DECAP0 (1 << 3)
+#define FTM_COMBINE_DECAPEN0 (1 << 2)
+#define FTM_COMBINE_COMP0 (1 << 1)
+#define FTM_COMBINE_COMBINE0 (1 << 0)
+
+#define FTM_DEADTIME_DTPS(x) ((x & 3) << 6)
+#define FTM_DEADTIME_DTVAL(x) ((x & 0x3F) << 0)
+
+#define FTM_EXTTRIG_TRIGF (1 << 7)
+#define FTM_EXTTRIG_INITTRIGEN (1 << 6)
+#define FTM_EXTTRIG_CH1TRIG (1 << 5)
+#define FTM_EXTTRIG_CH0TRIG (1 << 4)
+#define FTM_EXTTRIG_CH5TRIG (1 << 3)
+#define FTM_EXTTRIG_CH4TRIG (1 << 2)
+#define FTM_EXTTRIG_CH3TRIG (1 << 1)
+#define FTM_EXTTRIG_CH2TRIG (1 << 0)
+
+#define FTM_POL_POL7 (1 << 7)
+#define FTM_POL_POL6 (1 << 6)
+#define FTM_POL_POL5 (1 << 5)
+#define FTM_POL_POL4 (1 << 4)
+#define FTM_POL_POL3 (1 << 3)
+#define FTM_POL_POL2 (1 << 2)
+#define FTM_POL_POL1 (1 << 1)
+#define FTM_POL_POL0 (1 << 0)
+
+#define FTM_FMS_FAULTF (1 << 7)
+#define FTM_FMS_WPEN (1 << 6)
+#define FTM_FMS_FAULTIN (1 << 5)
+#define FTM_FMS_FAULTF3 (1 << 3)
+#define FTM_FMS_FAULTF2 (1 << 2)
+#define FTM_FMS_FAULTF1 (1 << 1)
+#define FTM_FMS_FAULTF0 (1 << 0)
+
+#define FTM_FILTER_CH3FVAL(x) ((x & 0xF) << 12)
+#define FTM_FILTER_CH2FVAL(x) ((x & 0xF) << 8)
+#define FTM_FILTER_CH1FVAL(x) ((x & 0xF) << 4)
+#define FTM_FILTER_CH0FVAL(x) ((x & 0xF) << 0)
+
+#define FTM_FLTCTRL_FFVAL(x) ((x & 0xF) << 8)
+#define FTM_FLTCTRL_FFLTR3EN (1 << 7)
+#define FTM_FLTCTRL_FFLTR2EN (1 << 6)
+#define FTM_FLTCTRL_FFLTR1EN (1 << 5)
+#define FTM_FLTCTRL_FFLTR0EN (1 << 4)
+#define FTM_FLTCTRL_FAULT3EN (1 << 3)
+#define FTM_FLTCTRL_FAULT2EN (1 << 2)
+#define FTM_FLTCTRL_FAULT1EN (1 << 1)
+#define FTM_FLTCTRL_FAULT0EN (1 << 0)
+
+#define FTM_QDCTRL_PHAFLTREN (1 << 7)
+#define FTM_QDCTRL_PHBFLTREN (1 << 6)
+#define FTM_QDCTRL_PHAPOL (1 << 5)
+#define FTM_QDCTRL_PHBPOL (1 << 4)
+#define FTM_QDCTRL_QUADMODE (1 << 3)
+#define FTM_QDCTRL_QUADIR (1 << 2)
+#define FTM_QDCTRL_TOFDIR (1 << 1)
+#define FTM_QDCTRL_QUADEN (1 << 0)
+
+#define FTM_CONF_GTBEOUT (1 << 10)
+#define FTM_CONF_GTBEEN (1 << 9)
+#define FTM_CONF_BDMMODE(x) ((x & 3) << 6)
+#define FTM_CONF_NUMTOF(x) ((x & 0x1F) << 0)
+
+#define FTM_FLTPOL_FLT3POL (1 << 3)
+#define FTM_FLTPOL_FLT2POL (1 << 2)
+#define FTM_FLTPOL_FLT1POL (1 << 1)
+#define FTM_FLTPOL_FLT0POL (1 << 0)
+
+#define FTM_SYNCONF_HWSOC (1 << 20)
+#define FTM_SYNCONF_HWINVC (1 << 19)
+#define FTM_SYNCONF_HWOM (1 << 18)
+#define FTM_SYNCONF_HWWRBUF (1 << 17)
+#define FTM_SYNCONF_HWRSTCNT (1 << 16)
+#define FTM_SYNCONF_SWSOC (1 << 12)
+#define FTM_SYNCONF_SWINVC (1 << 11)
+#define FTM_SYNCONF_SWOM (1 << 10)
+#define FTM_SYNCONF_SWWRBUF (1 << 9)
+#define FTM_SYNCONF_SWRSTCNT (1 << 8)
+#define FTM_SYNCONF_SYNCMODE (1 << 7)
+#define FTM_SYNCONF_SWOC (1 << 5)
+#define FTM_SYNCONF_INVC (1 << 4)
+#define FTM_SYNCONF_CNTINC (1 << 2)
+#define FTM_SYNCONF_HWTRIGMODE (1 << 0)
+
+#define FTM_INVCTRL_INV3EN (1 << 3)
+#define FTM_INVCTRL_INV2EN (1 << 2)
+#define FTM_INVCTRL_INV1EN (1 << 1)
+#define FTM_INVCTRL_INV0EN (1 << 0)
+
+#define FTM_SWOCTRL_CH7OCV (1 << 15)
+#define FTM_SWOCTRL_CH6OCV (1 << 14)
+#define FTM_SWOCTRL_CH5OCV (1 << 13)
+#define FTM_SWOCTRL_CH4OCV (1 << 12)
+#define FTM_SWOCTRL_CH3OCV (1 << 11)
+#define FTM_SWOCTRL_CH2OCV (1 << 10)
+#define FTM_SWOCTRL_CH1OCV (1 << 9)
+#define FTM_SWOCTRL_CH0OCV (1 << 8)
+#define FTM_SWOCTRL_CH7OC (1 << 7)
+#define FTM_SWOCTRL_CH6OC (1 << 6)
+#define FTM_SWOCTRL_CH5OC (1 << 5)
+#define FTM_SWOCTRL_CH4OC (1 << 4)
+#define FTM_SWOCTRL_CH3OC (1 << 3)
+#define FTM_SWOCTRL_CH2OC (1 << 2)
+#define FTM_SWOCTRL_CH1OC (1 << 1)
+#define FTM_SWOCTRL_CH0OC (1 << 0)
+
+#define FTM_PWMLOAD_LDOK (1 << 9)
+#define FTM_PWMLOAD_CH7SEL (1 << 7)
+#define FTM_PWMLOAD_CH6SEL (1 << 6)
+#define FTM_PWMLOAD_CH5SEL (1 << 5)
+#define FTM_PWMLOAD_CH4SEL (1 << 4)
+#define FTM_PWMLOAD_CH3SEL (1 << 3)
+#define FTM_PWMLOAD_CH2SEL (1 << 2)
+#define FTM_PWMLOAD_CH1SEL (1 << 1)
+#define FTM_PWMLOAD_CH0SEL (1 << 0)
+
+/* Periodic Interrupt Timer */
+#define PIT_MCR (PIT_BASE_ADDR + 0x00)
+#define PIT_LTMR64H (PIT_BASE_ADDR + 0xE0)
+#define PIT_LTMR64L (PIT_BASE_ADDR + 0xE4)
+#define PIT_LDVAL0 (PIT_BASE_ADDR + 0x100)
+#define PIT_CVAL0 (PIT_BASE_ADDR + 0x104)
+#define PIT_TCTRL0 (PIT_BASE_ADDR + 0x108)
+#define PIT_TFLG0 (PIT_BASE_ADDR + 0x10C)
+#define PIT_LDVAL1 (PIT_BASE_ADDR + 0x110)
+#define PIT_CVAL1 (PIT_BASE_ADDR + 0x114)
+#define PIT_TCTRL1 (PIT_BASE_ADDR + 0x118)
+#define PIT_TFLG1 (PIT_BASE_ADDR + 0x11C)
+#define PIT_LDVAL2 (PIT_BASE_ADDR + 0x120)
+#define PIT_CVAL2 (PIT_BASE_ADDR + 0x124)
+#define PIT_TCTRL2 (PIT_BASE_ADDR + 0x128)
+#define PIT_TFLG2 (PIT_BASE_ADDR + 0x12C)
+#define PIT_LDVAL3 (PIT_BASE_ADDR + 0x130)
+#define PIT_CVAL3 (PIT_BASE_ADDR + 0x134)
+#define PIT_TCTRL3 (PIT_BASE_ADDR + 0x138)
+#define PIT_TFLG3 (PIT_BASE_ADDR + 0x13C)
+#define PIT_LDVAL4 (PIT_BASE_ADDR + 0x140)
+#define PIT_CVAL4 (PIT_BASE_ADDR + 0x144)
+#define PIT_TCTRL4 (PIT_BASE_ADDR + 0x148)
+#define PIT_TFLG4 (PIT_BASE_ADDR + 0x14C)
+#define PIT_LDVAL5 (PIT_BASE_ADDR + 0x150)
+#define PIT_CVAL5 (PIT_BASE_ADDR + 0x154)
+#define PIT_TCTRL5 (PIT_BASE_ADDR + 0x158)
+#define PIT_TFLG5 (PIT_BASE_ADDR + 0x15C)
+#define PIT_LDVAL6 (PIT_BASE_ADDR + 0x160)
+#define PIT_CVAL6 (PIT_BASE_ADDR + 0x164)
+#define PIT_TCTRL6 (PIT_BASE_ADDR + 0x168)
+#define PIT_TFLG6 (PIT_BASE_ADDR + 0x16C)
+#define PIT_LDVAL7 (PIT_BASE_ADDR + 0x170)
+#define PIT_CVAL7 (PIT_BASE_ADDR + 0x174)
+#define PIT_TCTRL7 (PIT_BASE_ADDR + 0x178)
+#define PIT_TFLG7 (PIT_BASE_ADDR + 0x17C)
+
+#define PIT_MCR_MDIS (1 << 1)
+#define PIT_MCR_FRZ (1 << 0)
+
+#define PIT_TCTRL_CHN (1 << 2)
+#define PIT_TCTRL_TIE (1 << 1)
+#define PIT_TCTRL_TEN (1 << 0)
+
+#define PIT_TFLG_TIF (1 << 0)
+
+/* Low Power Timer */
+#define LPTMR_CSR (LPTMR_BASE_ADDR + 0x00)
+#define LPTMR_PSR (LPTMR_BASE_ADDR + 0x04)
+#define LPTMR_CMR (LPTMR_BASE_ADDR + 0x08)
+#define LPTMR_CNR (LPTMR_BASE_ADDR + 0x0C)
+
+#define LPTMR_CSR_TCF (1 << 7)
+#define LPTMR_CSR_TIE (1 << 6)
+#define LPTMR_CSR_TPS(x) ((x & 3) << 4)
+#define LPTMR_CSR_TPP (1 << 3)
+#define LPTMR_CSR_TFC (1 << 2)
+#define LPTMR_CSR_TMS (1 << 1)
+#define LPTMR_CSR_TEN (1 << 0)
+
+#define LPTMR_PSR_PRESCALE(x) ((x & 0x0F) << 3)
+#define LPTMR_PSR_PBYP (1 << 2)
+#define LPTMR_PSR_PCS(x) ((x & 0x03) << 0)
+
+#define LPTMR_CMR_COMPARE(x) (x & 0xFFFF)
+#define LPTMR_CNR_COUNTER(x) (x & 0xFFFF)
+
+#endif /* __ASM_ARCH_TIMER_H */
diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
new file mode 100644
index 0000000..225a1e1
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_VYBRID_PINS_H__
+#define __ASM_ARCH_VYBRID_PINS_H__
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_PORT 0x7
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define NON_PAD_I PIN_TO_PAD_MASK
+
+#define MUX_I_START 0x001C
+#define PAD_I_START 0x3F0
+#define INPUT_CTL_START 0x8C4
+#define MUX_I_END (PAD_I_START - 4)
+
+#define _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | \
+ ((pi - PAD_I_START) << PAD_I) | \
+ ((ga) << GPIO_I))
+
+#define _VYBRID_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+ _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _VYBRID_BUILD_NON_GPIO_PIN(mi, pi) \
+ _VYBRID_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
+
+enum iomux_input_select {
+ AUDMUX_P4_INPUT = 0,
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_VYBRID_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
new file mode 100644
index 0000000..51cfba5
--- /dev/null
+++ b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
@@ -0,0 +1,735 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_VYBRID_REGS_H__
+#define __ASM_ARCH_VYBRID_REGS_H__
+
+#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
+#define AIPS0_BASE_ADDR 0x40000000
+#define AIPS1_BASE_ADDR 0x40080000
+#define CSD0_BASE_ADDR 0x80000000 /* ddr 0 */
+#define CSD1_BASE_ADDR 0xa0000000 /* ddr 1 */
+
+#define IRAM_SIZE 0x00040000 /* 256 KB */
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
+#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG_A5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define WDOG_M4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
+#define ANATOP_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
+#define EWDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define ESDHC2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define QSPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define MACNET0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+#define MACNET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+
+/* WEIM CSnGCR1 */
+#define CSEN 1
+#define SWR (1 << 1)
+#define SRD (1 << 2)
+#define MUM (1 << 3)
+#define WFL (1 << 4)
+#define RFL (1 << 5)
+#define CRE (1 << 6)
+#define CREP (1 << 7)
+#define BL(x) (((x) & 0x7) << 8)
+#define WC (1 << 11)
+#define BCD(x) (((x) & 0x3) << 12)
+#define BCS(x) (((x) & 0x3) << 14)
+#define DSZ(x) (((x) & 0x7) << 16)
+#define SP (1 << 19)
+#define CSREC(x) (((x) & 0x7) << 20)
+#define AUS (1 << 23)
+#define GBC(x) (((x) & 0x7) << 24)
+#define WP (1 << 27)
+#define PSZ(x) (((x) & 0x0f << 28)
+
+/* WEIM CSnGCR2 */
+#define ADH(x) (((x) & 0x3))
+#define DAPS(x) (((x) & 0x0f << 4)
+#define DAE (1 << 8)
+#define DAP (1 << 9)
+#define MUX16_BYP (1 << 12)
+
+/* WEIM CSnRCR1 */
+#define RCSN(x) (((x) & 0x7))
+#define RCSA(x) (((x) & 0x7) << 4)
+#define OEN(x) (((x) & 0x7) << 8)
+#define OEA(x) (((x) & 0x7) << 12)
+#define RADVN(x) (((x) & 0x7) << 16)
+#define RAL (1 << 19)
+#define RADVA(x) (((x) & 0x7) << 20)
+#define RWSC(x) (((x) & 0x3f) << 24)
+
+/* WEIM CSnRCR2 */
+#define RBEN(x) (((x) & 0x7))
+#define RBE (1 << 3)
+#define RBEA(x) (((x) & 0x7) << 4)
+#define RL(x) (((x) & 0x3) << 8)
+#define PAT(x) (((x) & 0x7) << 12)
+#define APR (1 << 15)
+
+/* WEIM CSnWCR1 */
+#define WCSN(x) (((x) & 0x7))
+#define WCSA(x) (((x) & 0x7) << 3)
+#define WEN(x) (((x) & 0x7) << 6)
+#define WEA(x) (((x) & 0x7) << 9)
+#define WBEN(x) (((x) & 0x7) << 12)
+#define WBEA(x) (((x) & 0x7) << 15)
+#define WADVN(x) (((x) & 0x7) << 18)
+#define WADVA(x) (((x) & 0x7) << 21)
+#define WWSC(x) (((x) & 0x3f) << 24)
+#define WBED1 (1 << 30)
+#define WAL (1 << 31)
+
+/* WEIM CSnWCR2 */
+#define WBED 1
+
+/* WEIM WCR */
+#define BCM 1
+#define GBCD(x) (((x) & 0x3) << 1)
+#define INTEN (1 << 4)
+#define INTPOL (1 << 5)
+#define WDOG_EN (1 << 8)
+#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
+
+/* Number of GPIO pins per port */
+#define GPIO_NUM_PIN 32
+
+#define IIM_SREV 0x24
+#define ROM_SI_REV 0x80
+
+#define NFC_BUF_SIZE 0x1000
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x25
+#define CHIP_REV_3_0 0x30
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+struct clkctl {
+ u32 ccr; /* 0x00 */
+ u32 csr; /* 0x04 */
+ u32 ccsr; /* 0x08 */
+ u32 cacrr; /* 0x0C */
+ u32 cscmr1; /* 0x10 */
+ u32 cscdr1; /* 0x14 */
+ u32 cscdr2; /* 0x18 */
+ u32 cscdr3; /* 0x1C */
+ u32 cscmr2; /* 0x20 */
+ u32 cscdr4; /* 0x24 */
+ u32 ctor; /* 0x28 */
+ u32 clpcr; /* 0x2C */
+ u32 cisr; /* 0x30 */
+ u32 cimr; /* 0x34 */
+ u32 ccosr; /* 0x38 */
+ u32 cgpr; /* 0x3C */
+ u32 ccgr0; /* 0x40 */
+ u32 ccgr1; /* 0x44 */
+ u32 ccgr2; /* 0x48 */
+ u32 ccgr3; /* 0x4C */
+ u32 ccgr4; /* 0x50 */
+ u32 ccgr5; /* 0x54 */
+ u32 ccgr6; /* 0x58 */
+ u32 ccgr7; /* 0x5C */
+ u32 ccgr8; /* 0x60 */
+ u32 ccgr9; /* 0x64 */
+ u32 ccgr10; /* 0x68 */
+ u32 ccgr11; /* 0x6C */
+ u32 cmeor0; /* 0x70 */
+ u32 cmeor1; /* 0x74 */
+ u32 cmeor2; /* 0x78 */
+ u32 cmeor3; /* 0x7C */
+ u32 cmeor4; /* 0x80 */
+ u32 cmeor5; /* 0x84 */
+ u32 cppdsr; /* 0x88 */
+ u32 ccowr; /* 0x8C */
+ u32 ccpgr0; /* 0x90 */
+ u32 ccpgr1; /* 0x94 */
+ u32 ccpgr2; /* 0x98 */
+ u32 ccpgr3; /* 0x9C */
+};
+
+/* WEIM registers */
+struct weim {
+ u32 cs0gcr1;
+ u32 cs0gcr2;
+ u32 cs0rcr1;
+ u32 cs0rcr2;
+ u32 cs0wcr1;
+ u32 cs0wcr2;
+ u32 cs1gcr1;
+ u32 cs1gcr2;
+ u32 cs1rcr1;
+ u32 cs1rcr2;
+ u32 cs1wcr1;
+ u32 cs1wcr2;
+ u32 cs2gcr1;
+ u32 cs2gcr2;
+ u32 cs2rcr1;
+ u32 cs2rcr2;
+ u32 cs2wcr1;
+ u32 cs2wcr2;
+ u32 cs3gcr1;
+ u32 cs3gcr2;
+ u32 cs3rcr1;
+ u32 cs3rcr2;
+ u32 cs3wcr1;
+ u32 cs3wcr2;
+ u32 cs4gcr1;
+ u32 cs4gcr2;
+ u32 cs4rcr1;
+ u32 cs4rcr2;
+ u32 cs4wcr1;
+ u32 cs4wcr2;
+ u32 cs5gcr1;
+ u32 cs5gcr2;
+ u32 cs5rcr1;
+ u32 cs5rcr2;
+ u32 cs5wcr1;
+ u32 cs5wcr2;
+ u32 wcr;
+ u32 wiar;
+ u32 ear;
+};
+
+struct anadig {
+ u32 usb1_pll_ctrl;
+ u32 usb2_pll_ctrl;
+ u32 pll_528_ctrl;
+ u32 pll_528_ss;
+ u32 pll_528_num;
+ u32 pll_528_denom;
+ u32 pll_aud_ctrl;
+ u32 pll_aud_num;
+ u32 pll_aud_denom;
+ u32 pll_vid_ctrl;
+ u32 pll_vid_num;
+ u32 pll_vid_denom;
+ u32 pll_enet_ctrl;
+ u32 pll_pfd_480_usb1;
+ u32 pll_pfd_528;
+ u32 reg_1p1;
+ u32 reg_3p0;
+ u32 reg_2p5;
+ u32 ana_misc0;
+ u32 ana_misc1;
+ u32 tempsens0;
+ u32 usb1_vbus_det;
+ u32 usb1_vbus_chrg_det;
+ u32 usb1_vbus_detsta;
+ u32 usb1_chrg_detsta;
+ u32 usb1_loopback;
+ u32 usb1_misc;
+ u32 usb2_vbus_det;
+ u32 usb2_vbus_chrg_det;
+ u32 usb2_vbus_detsta;
+ u32 usb2_chrg_detsta;
+ u32 usb2_loopback;
+ u32 usb2_misc;
+ u32 digprog;
+ u32 pll_sys_ctrl;
+ u32 pll_sys_ss;
+ u32 pll_sys_num;
+ u32 pll_sys_denom;
+ u32 pfd_528_sys;
+ u32 pll_lock;
+};
+
+struct iomuxc {
+ u32 gpr0;
+ u32 gpr1;
+ u32 omux0;
+ u32 omux1;
+ u32 omux2;
+ u32 omux3;
+ u32 omux4;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr; /* 0x00 */
+ u32 sbmr1; /* 0x04 */
+ u32 srsr; /* 0x08 */
+ u32 secr; /* 0x0C */
+ u32 gpsr; /* 0x10 */
+ u32 sicr; /* 0x14 */
+ u32 simr; /* 0x18 */
+ u32 sbmr2; /* 0x1C */
+ u32 gpr0; /* 0x20 */
+ u32 gpr1; /* 0x24 */
+ u32 gpr2; /* 0x28 */
+ u32 gpr3; /* 0x2C */
+ u32 gpr4; /* 0x30 */
+ u32 hab0; /* 0x34 */
+ u32 hab1; /* 0x38 */
+ u32 hab2; /* 0x3C */
+ u32 hab3; /* 0x40 */
+ u32 hab4; /* 0x44 */
+ u32 hab5; /* 0x48 */
+ u32 misc0; /* 0x4C */
+ u32 misc1; /* 0x50 */
+ u32 misc2; /* 0x54 */
+ u32 misc3; /* 0x58 */
+};
+
+struct fuse_bank1_regs {
+ u32 fuse0_8[9];
+ u32 mac_addr[6];
+ u32 fuse15_31[0x11];
+};
+
+#define ANADIG_USB1_PLL_CTRL (0x10)
+#define ANADIG_USB2_PLL_CTRL (0x20)
+#define ANADIG_PLL_528_CTRL (0x30)
+#define ANADIG_PLL_528_SS (0x40)
+#define ANADIG_PLL_528_NUM (0x50)
+#define ANADIG_PLL_528_DENOM (0x60)
+#define ANADIG_PLL_AUD_CTRL (0x70)
+#define ANADIG_PLL_AUD_NUM (0x80)
+#define ANADIG_PLL_AUD_DENOM (0x90)
+#define ANADIG_PLL_VID_CTRL (0xA0)
+#define ANADIG_PLL_VID_NUM (0xB0)
+#define ANADIG_PLL_VID_DENOM (0xC0)
+#define ANADIG_PLL_ENET_CTRL (0xE0)
+#define ANADIG_PLL_PFD_480_USB1 (0xF0)
+#define ANADIG_PLL_PFD_528 (0x100)
+#define ANADIG_REG_1P1 (0x110)
+#define ANADIG_REG_3P0 (0x120)
+#define ANADIG_REG_2P5 (0x130)
+#define ANADIG_ANA_MISC0 (0x150)
+#define ANADIG_ANA_MISC1 (0x160)
+#define ANADIG_TEMPSENS0 (0x180)
+#define ANADIG_USB1_VBUS_DET (0x1A0)
+#define ANADIG_USB1_CHRG_DET (0x1B0)
+#define ANADIG_USB1_VBUS_DETSTA (0x1C0)
+#define ANADIG_UAB1_CHRG_DETSTA (0x1D0)
+#define ANADIG_USB1_LOOPBACK (0x1E0)
+#define ANADIG_USB1_MISC (0x1F0)
+#define ANADIG_USB2_VBUS_DET (0x200)
+#define ANADIG_USB2_CHRG_DET (0x210)
+#define ANADIG_USB2_VBUS_DETSTA (0x220)
+#define ANADIG_USB2_CHRG_DETSTA (0x230)
+#define ANADIG_USB2_LOOPBACK (0x240)
+#define ANADIG_USB2_MISC (0x250)
+#define ANADIG_DIGPROG (0x260)
+#define ANADIG_PLL_SYS_CTRL (0x270)
+#define ANADIG_PLL_SYS_SS (0x280)
+#define ANADIG_PLL_SYS_NUM (0x290)
+#define ANADIG_PLL_SYS_DENOM (0x2A0)
+#define ANADIG_PFD_528_SYS (0x2B0)
+#define ANADIG_PLL_LOCK (0x2C0)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
+#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
+
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
+#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
+#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
+#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
+
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
+
+#define FASE_CLK_FREQ 24000000
+#define SLOW_CLK_FREQ 32000
+#define PLL1_PFD1_FREQ 500000000
+#define PLL1_PFD2_FREQ 452000000
+#define PLL1_PFD3_FREQ 396000000
+#define PLL1_PFD4_FREQ 528000000
+#define PLL1_MAIN_FREQ 528000000
+#define PLL2_PFD1_FREQ 500000000
+#define PLL2_PFD2_FREQ 396000000
+#define PLL2_PFD3_FREQ 339000000
+#define PLL2_PFD4_FREQ 413000000
+#define PLL2_MAIN_FREQ 528000000
+#define PLL3_MAIN_FREQ 480000000
+#define PLL3_PFD3_FREQ 298000000
+#define PLL5_MAIN_FREQ 500000000
+
+#define ENET_EXTERNAL_CLK 50000000
+#define AUDIO_EXTERNAL_CLK 24576000
+
+#define DDR_CR_BASE DDR_BASE_ADDR
+#define DDR_PHY_BASE (DDR_BASE_ADDR + 0x400)
+
+#define DDR_CR000 (DDR_CR_BASE + 0x000)
+#define DDR_CR001 (DDR_CR_BASE + 0x004)
+#define DDR_CR002 (DDR_CR_BASE + 0x008)
+#define DDR_CR003 (DDR_CR_BASE + 0x00C)
+#define DDR_CR004 (DDR_CR_BASE + 0x010)
+#define DDR_CR005 (DDR_CR_BASE + 0x014)
+#define DDR_CR006 (DDR_CR_BASE + 0x018)
+#define DDR_CR007 (DDR_CR_BASE + 0x01C)
+#define DDR_CR008 (DDR_CR_BASE + 0x020)
+#define DDR_CR009 (DDR_CR_BASE + 0x024)
+
+#define DDR_CR010 (DDR_CR_BASE + 0x028)
+#define DDR_CR011 (DDR_CR_BASE + 0x02C)
+#define DDR_CR012 (DDR_CR_BASE + 0x030)
+#define DDR_CR013 (DDR_CR_BASE + 0x034)
+#define DDR_CR014 (DDR_CR_BASE + 0x038)
+#define DDR_CR015 (DDR_CR_BASE + 0x03C)
+#define DDR_CR016 (DDR_CR_BASE + 0x040)
+#define DDR_CR017 (DDR_CR_BASE + 0x044)
+#define DDR_CR018 (DDR_CR_BASE + 0x048)
+#define DDR_CR019 (DDR_CR_BASE + 0x04C)
+
+#define DDR_CR020 (DDR_CR_BASE + 0x050)
+#define DDR_CR021 (DDR_CR_BASE + 0x054)
+#define DDR_CR022 (DDR_CR_BASE + 0x058)
+#define DDR_CR023 (DDR_CR_BASE + 0x05C)
+#define DDR_CR024 (DDR_CR_BASE + 0x060)
+#define DDR_CR025 (DDR_CR_BASE + 0x064)
+#define DDR_CR026 (DDR_CR_BASE + 0x068)
+#define DDR_CR027 (DDR_CR_BASE + 0x06C)
+#define DDR_CR028 (DDR_CR_BASE + 0x070)
+#define DDR_CR029 (DDR_CR_BASE + 0x074)
+
+#define DDR_CR030 (DDR_CR_BASE + 0x078)
+#define DDR_CR031 (DDR_CR_BASE + 0x07C)
+#define DDR_CR032 (DDR_CR_BASE + 0x080)
+#define DDR_CR033 (DDR_CR_BASE + 0x084)
+#define DDR_CR034 (DDR_CR_BASE + 0x088)
+#define DDR_CR035 (DDR_CR_BASE + 0x08C)
+#define DDR_CR036 (DDR_CR_BASE + 0x090)
+#define DDR_CR037 (DDR_CR_BASE + 0x094)
+#define DDR_CR038 (DDR_CR_BASE + 0x098)
+#define DDR_CR039 (DDR_CR_BASE + 0x09C)
+
+#define DDR_CR040 (DDR_CR_BASE + 0x0A0)
+#define DDR_CR041 (DDR_CR_BASE + 0x0A4)
+#define DDR_CR042 (DDR_CR_BASE + 0x0A8)
+#define DDR_CR043 (DDR_CR_BASE + 0x0AC)
+#define DDR_CR044 (DDR_CR_BASE + 0x0B0)
+#define DDR_CR045 (DDR_CR_BASE + 0x0B4)
+#define DDR_CR046 (DDR_CR_BASE + 0x0B8)
+#define DDR_CR047 (DDR_CR_BASE + 0x0BC)
+#define DDR_CR048 (DDR_CR_BASE + 0x0C0)
+#define DDR_CR049 (DDR_CR_BASE + 0x0C4)
+
+#define DDR_CR050 (DDR_CR_BASE + 0x0C8)
+#define DDR_CR051 (DDR_CR_BASE + 0x0CC)
+#define DDR_CR052 (DDR_CR_BASE + 0x0D0)
+#define DDR_CR053 (DDR_CR_BASE + 0x0D4)
+#define DDR_CR054 (DDR_CR_BASE + 0x0D8)
+#define DDR_CR055 (DDR_CR_BASE + 0x0DC)
+#define DDR_CR056 (DDR_CR_BASE + 0x0E0)
+#define DDR_CR057 (DDR_CR_BASE + 0x0E4)
+#define DDR_CR058 (DDR_CR_BASE + 0x0E8)
+#define DDR_CR059 (DDR_CR_BASE + 0x0EC)
+
+#define DDR_CR060 (DDR_CR_BASE + 0x0F0)
+#define DDR_CR061 (DDR_CR_BASE + 0x0F4)
+#define DDR_CR062 (DDR_CR_BASE + 0x0F8)
+#define DDR_CR063 (DDR_CR_BASE + 0x0FC)
+#define DDR_CR064 (DDR_CR_BASE + 0x100)
+#define DDR_CR065 (DDR_CR_BASE + 0x104)
+#define DDR_CR066 (DDR_CR_BASE + 0x108)
+#define DDR_CR067 (DDR_CR_BASE + 0x10C)
+#define DDR_CR068 (DDR_CR_BASE + 0x110)
+#define DDR_CR069 (DDR_CR_BASE + 0x114)
+
+#define DDR_CR070 (DDR_CR_BASE + 0x118)
+#define DDR_CR071 (DDR_CR_BASE + 0x11C)
+#define DDR_CR072 (DDR_CR_BASE + 0x120)
+#define DDR_CR073 (DDR_CR_BASE + 0x124)
+#define DDR_CR074 (DDR_CR_BASE + 0x128)
+#define DDR_CR075 (DDR_CR_BASE + 0x12C)
+#define DDR_CR076 (DDR_CR_BASE + 0x130)
+#define DDR_CR077 (DDR_CR_BASE + 0x134)
+#define DDR_CR078 (DDR_CR_BASE + 0x138)
+#define DDR_CR079 (DDR_CR_BASE + 0x13C)
+
+#define DDR_CR080 (DDR_CR_BASE + 0x140)
+#define DDR_CR081 (DDR_CR_BASE + 0x144)
+#define DDR_CR082 (DDR_CR_BASE + 0x148)
+#define DDR_CR083 (DDR_CR_BASE + 0x14C)
+#define DDR_CR084 (DDR_CR_BASE + 0x150)
+#define DDR_CR085 (DDR_CR_BASE + 0x154)
+#define DDR_CR086 (DDR_CR_BASE + 0x158)
+#define DDR_CR087 (DDR_CR_BASE + 0x15C)
+#define DDR_CR088 (DDR_CR_BASE + 0x160)
+#define DDR_CR089 (DDR_CR_BASE + 0x164)
+
+#define DDR_CR090 (DDR_CR_BASE + 0x168)
+#define DDR_CR091 (DDR_CR_BASE + 0x16C)
+#define DDR_CR092 (DDR_CR_BASE + 0x170)
+#define DDR_CR093 (DDR_CR_BASE + 0x174)
+#define DDR_CR094 (DDR_CR_BASE + 0x178)
+#define DDR_CR095 (DDR_CR_BASE + 0x17C)
+#define DDR_CR096 (DDR_CR_BASE + 0x180)
+#define DDR_CR097 (DDR_CR_BASE + 0x184)
+#define DDR_CR098 (DDR_CR_BASE + 0x188)
+#define DDR_CR099 (DDR_CR_BASE + 0x18C)
+
+#define DDR_CR100 (DDR_CR_BASE + 0x190)
+#define DDR_CR101 (DDR_CR_BASE + 0x194)
+#define DDR_CR102 (DDR_CR_BASE + 0x198)
+#define DDR_CR103 (DDR_CR_BASE + 0x19C)
+#define DDR_CR104 (DDR_CR_BASE + 0x1A0)
+#define DDR_CR105 (DDR_CR_BASE + 0x1A4)
+#define DDR_CR106 (DDR_CR_BASE + 0x1A8)
+#define DDR_CR107 (DDR_CR_BASE + 0x1AC)
+#define DDR_CR108 (DDR_CR_BASE + 0x1B0)
+#define DDR_CR109 (DDR_CR_BASE + 0x1B4)
+
+#define DDR_CR110 (DDR_CR_BASE + 0x1B8)
+#define DDR_CR111 (DDR_CR_BASE + 0x1BC)
+#define DDR_CR112 (DDR_CR_BASE + 0x1C0)
+#define DDR_CR113 (DDR_CR_BASE + 0x1C4)
+#define DDR_CR114 (DDR_CR_BASE + 0x1C8)
+#define DDR_CR115 (DDR_CR_BASE + 0x1CC)
+#define DDR_CR116 (DDR_CR_BASE + 0x1D0)
+#define DDR_CR117 (DDR_CR_BASE + 0x1D4)
+#define DDR_CR118 (DDR_CR_BASE + 0x1D8)
+#define DDR_CR119 (DDR_CR_BASE + 0x1DC)
+
+#define DDR_CR120 (DDR_CR_BASE + 0x1E0)
+#define DDR_CR121 (DDR_CR_BASE + 0x1E4)
+#define DDR_CR122 (DDR_CR_BASE + 0x1E8)
+#define DDR_CR123 (DDR_CR_BASE + 0x1EC)
+#define DDR_CR124 (DDR_CR_BASE + 0x1F0)
+#define DDR_CR125 (DDR_CR_BASE + 0x1F4)
+#define DDR_CR126 (DDR_CR_BASE + 0x1F8)
+#define DDR_CR127 (DDR_CR_BASE + 0x1FC)
+#define DDR_CR128 (DDR_CR_BASE + 0x200)
+#define DDR_CR129 (DDR_CR_BASE + 0x204)
+
+#define DDR_CR130 (DDR_CR_BASE + 0x208)
+#define DDR_CR131 (DDR_CR_BASE + 0x20C)
+#define DDR_CR132 (DDR_CR_BASE + 0x210)
+#define DDR_CR133 (DDR_CR_BASE + 0x214)
+#define DDR_CR134 (DDR_CR_BASE + 0x218)
+#define DDR_CR135 (DDR_CR_BASE + 0x21C)
+#define DDR_CR136 (DDR_CR_BASE + 0x220)
+#define DDR_CR137 (DDR_CR_BASE + 0x224)
+#define DDR_CR138 (DDR_CR_BASE + 0x228)
+#define DDR_CR139 (DDR_CR_BASE + 0x22C)
+
+#define DDR_CR140 (DDR_CR_BASE + 0x230)
+#define DDR_CR141 (DDR_CR_BASE + 0x234)
+#define DDR_CR142 (DDR_CR_BASE + 0x238)
+#define DDR_CR143 (DDR_CR_BASE + 0x23C)
+#define DDR_CR144 (DDR_CR_BASE + 0x240)
+#define DDR_CR145 (DDR_CR_BASE + 0x244)
+#define DDR_CR146 (DDR_CR_BASE + 0x248)
+#define DDR_CR147 (DDR_CR_BASE + 0x24C)
+#define DDR_CR148 (DDR_CR_BASE + 0x250)
+#define DDR_CR149 (DDR_CR_BASE + 0x254)
+
+#define DDR_CR150 (DDR_CR_BASE + 0x258)
+#define DDR_CR151 (DDR_CR_BASE + 0x25C)
+#define DDR_CR152 (DDR_CR_BASE + 0x260)
+#define DDR_CR153 (DDR_CR_BASE + 0x264)
+#define DDR_CR154 (DDR_CR_BASE + 0x268)
+#define DDR_CR155 (DDR_CR_BASE + 0x26C)
+#define DDR_CR156 (DDR_CR_BASE + 0x270)
+#define DDR_CR157 (DDR_CR_BASE + 0x274)
+#define DDR_CR158 (DDR_CR_BASE + 0x278)
+#define DDR_CR159 (DDR_CR_BASE + 0x27C)
+
+#define DDR_CR160 (DDR_CR_BASE + 0x280)
+#define DDR_CR161 (DDR_CR_BASE + 0x284)
+#define DDR_CR162 (DDR_CR_BASE + 0x288)
+#define DDR_CR163 (DDR_CR_BASE + 0x28C)
+#define DDR_CR164 (DDR_CR_BASE + 0x290)
+#define DDR_CR165 (DDR_CR_BASE + 0x294)
+#define DDR_CR166 (DDR_CR_BASE + 0x298)
+#define DDR_CR167 (DDR_CR_BASE + 0x29C)
+#define DDR_CR168 (DDR_CR_BASE + 0x2A0)
+#define DDR_CR169 (DDR_CR_BASE + 0x2A4)
+
+#define DDR_CR170 (DDR_CR_BASE + 0x2A8)
+#define DDR_CR171 (DDR_CR_BASE + 0x2AC)
+#define DDR_CR172 (DDR_CR_BASE + 0x2B0)
+#define DDR_CR173 (DDR_CR_BASE + 0x2B4)
+#define DDR_CR174 (DDR_CR_BASE + 0x2B8)
+#define DDR_CR175 (DDR_CR_BASE + 0x2BC)
+#define DDR_CR176 (DDR_CR_BASE + 0x2C0)
+#define DDR_CR177 (DDR_CR_BASE + 0x2C4)
+#define DDR_CR178 (DDR_CR_BASE + 0x2C8)
+#define DDR_CR179 (DDR_CR_BASE + 0x2CC)
+
+/*
+ * PHY
+ */
+#define DDR_PHY000 (DDR_PHY_BASE + 0x000)
+#define DDR_PHY001 (DDR_PHY_BASE + 0x004)
+#define DDR_PHY002 (DDR_PHY_BASE + 0x008)
+#define DDR_PHY003 (DDR_PHY_BASE + 0x00C)
+#define DDR_PHY004 (DDR_PHY_BASE + 0x010)
+#define DDR_PHY005 (DDR_PHY_BASE + 0x014)
+#define DDR_PHY006 (DDR_PHY_BASE + 0x018)
+#define DDR_PHY007 (DDR_PHY_BASE + 0x01C)
+#define DDR_PHY008 (DDR_PHY_BASE + 0x020)
+#define DDR_PHY009 (DDR_PHY_BASE + 0x024)
+
+#define DDR_PHY010 (DDR_PHY_BASE + 0x028)
+#define DDR_PHY011 (DDR_PHY_BASE + 0x02C)
+#define DDR_PHY012 (DDR_PHY_BASE + 0x030)
+#define DDR_PHY013 (DDR_PHY_BASE + 0x034)
+#define DDR_PHY014 (DDR_PHY_BASE + 0x038)
+#define DDR_PHY015 (DDR_PHY_BASE + 0x03C)
+#define DDR_PHY016 (DDR_PHY_BASE + 0x040)
+#define DDR_PHY017 (DDR_PHY_BASE + 0x044)
+#define DDR_PHY018 (DDR_PHY_BASE + 0x048)
+#define DDR_PHY019 (DDR_PHY_BASE + 0x04C)
+
+#define DDR_PHY020 (DDR_PHY_BASE + 0x050)
+#define DDR_PHY021 (DDR_PHY_BASE + 0x054)
+#define DDR_PHY022 (DDR_PHY_BASE + 0x058)
+#define DDR_PHY023 (DDR_PHY_BASE + 0x05C)
+#define DDR_PHY024 (DDR_PHY_BASE + 0x060)
+#define DDR_PHY025 (DDR_PHY_BASE + 0x064)
+#define DDR_PHY026 (DDR_PHY_BASE + 0x068)
+#define DDR_PHY027 (DDR_PHY_BASE + 0x06C)
+#define DDR_PHY028 (DDR_PHY_BASE + 0x070)
+#define DDR_PHY029 (DDR_PHY_BASE + 0x074)
+
+#define DDR_PHY030 (DDR_PHY_BASE + 0x078)
+#define DDR_PHY031 (DDR_PHY_BASE + 0x07C)
+#define DDR_PHY032 (DDR_PHY_BASE + 0x080)
+#define DDR_PHY033 (DDR_PHY_BASE + 0x084)
+#define DDR_PHY034 (DDR_PHY_BASE + 0x088)
+#define DDR_PHY035 (DDR_PHY_BASE + 0x08C)
+#define DDR_PHY036 (DDR_PHY_BASE + 0x090)
+#define DDR_PHY037 (DDR_PHY_BASE + 0x094)
+#define DDR_PHY038 (DDR_PHY_BASE + 0x098)
+#define DDR_PHY039 (DDR_PHY_BASE + 0x09C)
+
+#define DDR_PHY040 (DDR_PHY_BASE + 0x0A0)
+#define DDR_PHY041 (DDR_PHY_BASE + 0x0A4)
+#define DDR_PHY042 (DDR_PHY_BASE + 0x0A8)
+#define DDR_PHY043 (DDR_PHY_BASE + 0x0AC)
+#define DDR_PHY044 (DDR_PHY_BASE + 0x0B0)
+#define DDR_PHY045 (DDR_PHY_BASE + 0x0B4)
+#define DDR_PHY046 (DDR_PHY_BASE + 0x0B8)
+#define DDR_PHY047 (DDR_PHY_BASE + 0x0BC)
+#define DDR_PHY048 (DDR_PHY_BASE + 0x0C0)
+#define DDR_PHY049 (DDR_PHY_BASE + 0x0C4)
+
+#define DDR_PHY050 (DDR_PHY_BASE + 0x0C8)
+#define DDR_PHY051 (DDR_PHY_BASE + 0x0CC)
+#define DDR_PHY052 (DDR_PHY_BASE + 0x0D0)
+#define DDR_PHY053 (DDR_PHY_BASE + 0x0D4)
+#define DDR_PHY054 (DDR_PHY_BASE + 0x0D8)
+#define DDR_PHY055 (DDR_PHY_BASE + 0x0DC)
+#define DDR_PHY056 (DDR_PHY_BASE + 0x0E0)
+#define DDR_PHY057 (DDR_PHY_BASE + 0x0E4)
+#define DDR_PHY058 (DDR_PHY_BASE + 0x0E8)
+#define DDR_PHY059 (DDR_PHY_BASE + 0x0EC)
+
+#define DDR_PHY060 (DDR_PHY_BASE + 0x0F0)
+#define DDR_PHY061 (DDR_PHY_BASE + 0x0F4)
+#define DDR_PHY062 (DDR_PHY_BASE + 0x0F8)
+#define DDR_PHY063 (DDR_PHY_BASE + 0x0FC)
+#define DDR_PHY064 (DDR_PHY_BASE + 0x100)
+#define DDR_PHY065 (DDR_PHY_BASE + 0x104)
+#define DDR_PHY066 (DDR_PHY_BASE + 0x108)
+#define DDR_PHY067 (DDR_PHY_BASE + 0x10C)
+#define DDR_PHY068 (DDR_PHY_BASE + 0x110)
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_VYBRID_REGS_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 37ac0da..bb7ebc2 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -29,6 +29,9 @@ struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#ifdef CONFIG_SYS_IPG
+ unsigned long ipg_clk;
+#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index a676b6d..31d67bf 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1107,6 +1107,10 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_OMAP5_SEVM 3777
#define MACH_TYPE_ARMADILLO_800EVA 3863
#define MACH_TYPE_KZM9G 4140
+#define MACH_TYPE_VYBRID_VF7XX 4145
+#define MACH_TYPE_VYBRID_VF6XX 4146
+#define MACH_TYPE_VYBRID_VF5XX 4147
+#define MACH_TYPE_VYBRID_VF4XX 4148
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -14248,6 +14252,58 @@ extern unsigned int __machine_arch_type;
# define machine_is_kzm9g() (0)
#endif
+#ifdef CONFIG_MACH_VYBRID_VF7XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VYBRID_VF7XX
+# endif
+# define machine_is_vybrid_vf7xx() \
+ (machine_arch_type == MACH_TYPE_VYBRID_VF7XX)
+#else
+# define machine_is_vybrid_vf7xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_VYBRID_VF6XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VYBRID_VF6XX
+# endif
+# define machine_is_vybrid_vf6xx() \
+ (machine_arch_type == MACH_TYPE_VYBRID_VF6XX)
+#else
+# define machine_is_vybrid_vf6xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_VYBRID_VF5XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VYBRID_VF5XX
+# endif
+# define machine_is_vybrid_vf5xx() \
+ (machine_arch_type == MACH_TYPE_VYBRID_VF5XX)
+#else
+# define machine_is_vybrid_vf5xx() (0)
+#endif
+
+#ifdef CONFIG_MACH_VYBRID_VF4XX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_VYBRID_VF4XX
+# endif
+# define machine_is_vybrid_vf4xx() \
+ (machine_arch_type == MACH_TYPE_VYBRID_VF4XX)
+#else
+# define machine_is_vybrid_vf4xx() (0)
+#endif
+
/*
* These have not yet been registered
*/
--
1.8.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-12 6:53 ` [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support Alison Wang
@ 2013-04-12 11:15 ` Fabio Estevam
2013-04-13 20:32 ` Stefano Babic
2013-04-15 3:24 ` Liu Hui-R64343
2 siblings, 0 replies; 27+ messages in thread
From: Fabio Estevam @ 2013-04-12 11:15 UTC (permalink / raw)
To: u-boot
On Fri, Apr 12, 2013 at 3:53 AM, Alison Wang <b18965@freescale.com> wrote:
> +static char *get_reset_cause(void)
> +{
> + char *resetcause[32] = {"POR",
> + "Cortex A5 WDOG Timer Reset",
> + 0,
You mix strings and an integer zero here. Shouldn't you replace the
'0' with "unknown" or "invalid" ?
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-12 6:53 ` [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support Alison Wang
2013-04-12 11:15 ` Fabio Estevam
@ 2013-04-13 20:32 ` Stefano Babic
2013-04-28 10:36 ` Wang Huan-B18965
2013-04-15 3:24 ` Liu Hui-R64343
2 siblings, 1 reply; 27+ messages in thread
From: Stefano Babic @ 2013-04-13 20:32 UTC (permalink / raw)
To: u-boot
On 12/04/2013 08:53, Alison Wang wrote:
> The Vybrid devices are a family of Freescale's latest Dual Single
> Core offering with ARM Cortex A5 and CM4 based processors for
> Advanced Connected Radio, Entry Infotainment, and Cluster as well
> as high end industrial and general purpose applications.
>
> This patch adds vybrid CPU support.
>
Hi Alison,
first: I agree with Fabio's comments - I try to no repeat his comments here.
> diff --git a/Makefile b/Makefile
> index 12763ce..8a86951 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -334,6 +334,9 @@ LIBS-y += test/libtest.o
> ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
> LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
> endif
> +ifeq ($(SOC),vybrid)
> +LIBS-y += $(CPUDIR)/vybrid-common/libvybrid-common.o
> +endif
I would like to understand there common code should be put. As you can
see, for i.MX there is a imx_common directory that is valid across
ARM-Core.
>
> ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
> LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
> @@ -467,6 +470,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> $(obj)u-boot.imx: $(obj)u-boot.bin depend
> $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
>
> +$(obj)u-boot.vybrid: $(obj)u-boot.bin
> + $(obj)tools/mkimage -n $(CONFIG_VYBRID_CONFIG) -T imximage \
> + -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
> +
I do not think we need a new rule only to have a new name. u-boot.imx
had exactly the same rule here, but we decided in the past that some
specific SOC rules should belong to the SOC (=CPU) directory without
touching the main Makefile. The same rule you put here you can find into
arch/arm/imx-common/Makefile. If the vybrid has nothing to do with
imx_common, the rule to generate the image should go into the vybrid/
directory.
> $(obj)u-boot.kwb: $(obj)u-boot.bin
> $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
> -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
> @@ -855,6 +862,7 @@ clobber: tidy
> @rm -f $(obj)u-boot.kwb
> @rm -f $(obj)u-boot.pbl
> @rm -f $(obj)u-boot.imx
> + @rm -f $(obj)u-boot.vybrid
Mainly I disagree to add a new name if we do not get a new image. The
list you see contains different images, not different names. As far as I
can see, u-boot.vybrid has the same structure and is built in the same
way as u-boot.imx.
> new file mode 100644
> index 0000000..bee8850
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)libvybrid-common.o
> +
> +COBJS := timer.o
> +COBJS += cpu.o
> +COBJS += speed.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
> +
> +all: $(obj).depend $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c
> new file mode 100644
> index 0000000..f99083e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
> @@ -0,0 +1,127 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/errno.h>
> +#include <asm/io.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +
> +#ifdef CONFIG_FSL_ESDHC
> +#include <fsl_esdhc.h>
> +#endif
> +
> +static char *get_reset_cause(void)
> +{
> + char *resetcause[32] = {"POR",
> + "Cortex A5 WDOG Timer Reset",
> + 0,
I do not think it is a good idea to pad with dummy data only to output
it later. I think it is better to use straightforward the same mechanism
we have for all other SOC, that is:
- add defines for each cause (WDOG/POR...), better check if we can reuse
/ factorize common values.
- implement get_reset_cause() in the same way (check implementation for
MX35 / MX5 / MX6..). It is much more readable.
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> + u32 cpurev;
> +
> + cpurev = get_cpu_rev();
> + printf("CPU: Freescale VyBrid %x family rev%d.%d at %d MHz\n",
> + (cpurev & 0xFFF000) >> 12,
> + (cpurev & 0x000F0) >> 4,
> + (cpurev & 0x0000F) >> 0,
Any chance to get defines for the masks you are using here ?
> +int cpu_eth_init(bd_t *bis)
> +{
> + int rc = -ENODEV;
> +
> + rc = mcffec_initialize(bis);
I admit I have mot checked deeply - but I have some limits due to the
missing documentation. Is there some good reason we cannot adapt the
well known FEC driver (we have a driver for all SOCs) to vybrid ?
> +
> +void reset_cpu(ulong addr)
> +{
> + __raw_writew(4, WDOG_A5_BASE_ADDR);
> +}
I think this is the old implementation for i.MX - replaced by the
function in imx_watchdog.c.
> diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c b/arch/arm/cpu/armv7/vybrid-common/timer.c
> new file mode 100644
> index 0000000..be990e6
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <div64.h>
> +#include <asm/arch/timer.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/vybrid-regs.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define timestamp (gd->arch.tbl)
> +#define timerticks (gd->arch.tbu)
> +#define lastinc (gd->arch.lastinc)
> +static unsigned long ltmstamp;
> +
> +#define CONFIG_TMR_USEPIT
> +#ifdef CONFIG_TMR_USEPIT
> +
> +int timer_init(void)
> +{
> + ulong usecs;
> + ulong ticks;
> +
> + timestamp = 0;
> +
> + /*
> + * nsecs conversion = (1/ipg_clk) * 10^9
> + * equivalent to 1000 / (ipg_clk / 10^6)
> + */
> + usecs = (vybrid_get_clock(VYBRID_IPG_CLK) / 1000000);
> + ticks = 1000 / usecs;
> +
> + clrbits_le32(PIT_MCR, 2); /* enable PIT */
> +
> + /* ticks per 10 us = 10000 us / usecs = cycles time */
> + timerticks = (10 * 1000) / ticks;
> +
> + __raw_writel(0xFFFFFFFF, PIT_LDVAL1);
> + __raw_writel(0, PIT_TCTRL1);
> + __raw_writel(4, PIT_TCTRL1);
> + __raw_writel(5, PIT_TCTRL1);
> + __raw_writel(timerticks, PIT_LDVAL0);
> + __raw_writel(1, PIT_TCTRL0);
General remark: do not use offset to write into register. Instead of
that, defines a C structure and access to the structure to set / read
registers. See othe i.MX implementations.
> +ulong get_timer(ulong base)
> +{
> + unsigned long now, diff;
> +
> + now = __raw_readl(PIT_LTMR64H);
> + diff = -(now - lastinc);
> + ltmstamp += diff;
> + while (ltmstamp > 100) {
> + timestamp++;
> + ltmstamp -= 100;
> + }
> + lastinc = now;
> +
> + return timestamp - base;
> +}
I am sure this can be better factorited - we had this kind of code some
times ago. We have quite the same structure for all SOCs, not only
Freescale's. Check for example the implementation in imx_common/timer.c
> +
> +/* delay x useconds AND preserve advance timstamp value */
> +void __udelay(unsigned long usec)
> +{
> + ulong nsecs, tmp;
> +
> + /*
> + * nsecs conversion = (1/ipg_clk) * 10^9
> + * equivalent to 1000 / (ipg_clk / 10^6)
> + */
> + if (usec < 5)
> + usec = 10;
> +
> + nsecs = gd->arch.ipg_clk / 1000000;
> + nsecs = 1000 / nsecs;
> +
> + /* 1 us per ticks = 1000 ns / nsecs = cycles time */
> + while (usec > 0) {
> + if (usec > 65000)
> + tmp = 65000;
I admit I have the value not understood. But again, if we have a
get_ticks() and us_to_ticks() for the SOC, udelay is standard and we
have the hope to better factorize it in future.
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +unsigned long long _usec2ticks(unsigned long long usec)
> +{
> + return usec;
> +}
Obsolete, I think, we use us_to_tick()
> +
> +struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> +
> +/* Get mcu main rate */
> +static u32 get_mcu_main_clk(void)
> +{
> + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> + u32 ccm_ccsr, ccm_cacrr, armclk_div;
> + u32 sysclk_sel, pll_pfd_sel = 0;
> + u32 freq = 0;
> +
> + ccm_ccsr = readl(&ccm->ccsr);
> + sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
> + sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
> +
> + ccm_cacrr = readl(&ccm->cacrr);
> + armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
> + armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
> + armclk_div += 1;
I see a lot of analogies with i.MX6 code.
> +
> + switch (sysclk_sel) {
> + case 0:
> + freq = FASE_CLK_FREQ;
> + break;
> + case 1:
> + freq = SLOW_CLK_FREQ;
> + break;
> + case 3:
> + freq = PLL2_MAIN_FREQ;
> + break;
> + case 5:
> + freq = PLL3_MAIN_FREQ;
> + break;
> + case 2:
> + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
> + pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
> + break;
> + case 4:
> + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
> + pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
> + break;
> + default:
> + printf("unsupported system clock select\n");
> + }
> +
> + if (sysclk_sel == 2) {
Code is quite confused. Why do you use a switch and after that you check
again for cases that are covered by the switch itself ?
> +
> +/* Get the rate of bus clock */
> +static u32 get_bus_clk(void)
> +{
> + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> + u32 ccm_cacrr, busclk_div;
> +
> + ccm_cacrr = readl(&ccm->cacrr);
> +
> + busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
> + busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
> + busclk_div += 1;
> +
> + return get_mcu_main_clk() / busclk_div;
> +}
> +
> +/* Get the rate of ipg clock */
> +static u32 get_ipg_clk(void)
> +{
> + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> + u32 ccm_cacrr, ipgclk_div;
> +
> + ccm_cacrr = readl(&ccm->cacrr);
> +
> + ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
> + ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
> + ipgclk_div += 1;
> +
> + return get_bus_clk() / ipgclk_div;
> +}
> +
> +/* get dspi clock rate */
> +static u32 vybrid_get_dspiclk(void)
> +{
> + return get_ipg_clk();
> +}
> +
> +/* The API of get vybrid clocks */
> +unsigned int vybrid_get_clock(enum vybrid_clock clk)
> +{
> + switch (clk) {
> + case VYBRID_ARM_CLK:
> + return get_mcu_main_clk();
> + case VYBRID_BUS_CLK:
> + return get_bus_clk();
> + case VYBRID_IPG_CLK:
> + return get_ipg_clk();
> + case VYBRID_UART_CLK:
> + return vybrid_get_uartclk();
> + case VYBRID_DSPI_CLK:
> + return vybrid_get_dspiclk();
Can you explain which peripheral is this ? Has vybrid a DSP inside ?
> +/* Get the rate of uart clk */
> +u32 vybrid_get_uartclk(void)
> +{
> + return get_ipg_clk();
> +}
Why do we need if we can use vybrid_get_clock(VYBRID_UART_CLK) ?
> diff --git a/arch/arm/cpu/armv7/vybrid/iomux.c b/arch/arm/cpu/armv7/vybrid/iomux.c
> new file mode 100644
> index 0000000..fb672e3
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/vybrid/iomux.c
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/vybrid-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/arch/sys_proto.h>
> +
> +void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio)
> +{
> + u32 value;
> +
> + value = (((padio->mod & 7) << 20) | ((padio->spd & 3) << 12) | \
> + ((padio->sre & 1) << 11) | ((padio->ode & 1) << 10) | \
> + ((padio->hys & 1) << 9) | ((padio->dse & 7) << 6) | \
> + ((padio->pus & 3) << 4) | ((padio->pke & 1) << 3) | \
> + ((padio->pue & 1) << 2) | ((padio->obe & 1) << 1) | \
> + ((padio->ibe & 1) << 0));
> +
> + __raw_writel(pad_addr, value);
Add defines for the magic number you introduce here.
> diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> new file mode 100644
> index 0000000..c2bda4f
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> @@ -0,0 +1,128 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <generated/asm-offsets.h>
> +
> +/* DDR */
> +.macro init_drive_strength
> +.endm /* init_drive_strength */
> +
> +.macro setup_pll pll, freq
> +.endm
> +
> +.macro init_clock
> + ldr r0, =CCM_BASE_ADDR
> +
> + ldr r1, =CONFIG_SYS_CLKCTRL_CLPCR
> + str r1, [r0, #CLKCTL_CLPCR]
> +
> + /* Gate of clocks to the peripherals first */
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR0
> + str r1, [r0, #CLKCTL_CCGR0]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR1
> + str r1, [r0, #CLKCTL_CCGR1]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR2
> + str r1, [r0, #CLKCTL_CCGR2]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR3
> + str r1, [r0, #CLKCTL_CCGR3]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR4
> + str r1, [r0, #CLKCTL_CCGR4]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR5
> + str r1, [r0, #CLKCTL_CCGR5]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR6
> + str r1, [r0, #CLKCTL_CCGR6]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR7
> + str r1, [r0, #CLKCTL_CCGR7]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR8
> + str r1, [r0, #CLKCTL_CCGR8]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR9
> + str r1, [r0, #CLKCTL_CCGR9]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR10
> + str r1, [r0, #CLKCTL_CCGR10]
> + ldr r1, =CONFIG_SYS_CLKCTL_CCGR11
> + str r1, [r0, #CLKCTL_CCGR11]
> +
Why cannot we do this in C code ? You introduce a lot of
CONFIS_SYS_CLKCTL_ in the board configuration file. This can be done in
board code, for example in board_early_init_f(), without constrain all
boards to set all of this stuff, but only what is required.
> +.section ".text.init", "x"
> +
> +.globl lowlevel_init
> +lowlevel_init:
> + /* ARM errata ID #468414 */
> + mrc 15, 0, r1, c1, c0, 1
> + orr r1, r1, #(1 << 5) /* enable L1NEON bit */
> + mcr 15, 0, r1, c1, c0, 1
> +
> +#ifndef CONFIG_SYS_BOOTHDR
This is not currently defined anyware. If you want to add CONFIG_SYS_
defines, you should also add the documentation explainig which are the
goals in the README.
> +/* Board level setting value */
> +DDR_PERCHARGE_CMD: .word 0x04008008
> +DDR_REFRESH_CMD: .word 0x00008010
> +DDR_LMR1_W: .word 0x00338018
> +DDR_LMR_CMD: .word 0xB2220000
> +DDR_TIMING_W: .word 0xB02567A9
> +DDR_MISC_W: .word 0x000A0104
They are defined, but not used. Please do not add dead code.
> +#include <common.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +
> +#include <asm/errno.h>
> +#include <asm/io.h>
> +
> +#if !(defined(CONFIG_VYBRID))
> +#error "CPU_TYPE not defined"
> +#endif
> +
> +u32 get_cpu_rev(void)
> +{
> + int system_rev = 0x600000;
Which is the meaning of this value ? It is not read from hardware
> diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h b/arch/arm/include/asm/arch-vybrid/iomux.h
> new file mode 100644
> index 0000000..94f8b0b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-vybrid/iomux.h
> @@ -0,0 +1,323 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __MACH_VYBRID_IOMUX_H__
> +#define __MACH_VYBRID_IOMUX_H__
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/vybrid-pins.h>
> +
> +#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000)
> +#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004)
> +#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008)
> +#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C)
> +#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010)
> +#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014)
> +#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018)
> +#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C)
> +#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020)
> +#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024)
> +#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028)
> +#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C)
> +#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030)
> +#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034)
> +#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038)
> +#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C)
There is not a lot of information defining IOMUXC_PAD_NUMBER with an
offset. If you see for other SOCs, the values correspond to a specific
function.
> +#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C)
> +#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220)
> +#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224)
> +#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228)
> +#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C)
> +#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230)
> +#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234)
> +#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238)
> +#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C)
> +#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240)
> +#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244)
> +#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248)
> +#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C)
> +#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250)
> +#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254)
> +#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258)
> +#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C)
> +
> +#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260)
> +#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264)
> +#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268)
> +
> +#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C)
> +
> +#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270)
> +
> +#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274)
> +
> +#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278)
> +
> +#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C)
> +#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280)
> +#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284)
> +#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288)
> +#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C)
> +#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290)
> +#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294)
> +#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298)
> +#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C)
> +#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0)
> +#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4)
> +#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8)
> +#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC)
> +#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0)
> +#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4)
> +#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8)
> +
> +#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC)
> +#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0)
> +
> +#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4)
> +#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8)
> +
> +#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC)
> +#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0)
> +
> +#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4)
> +#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8)
> +
> +#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC)
> +#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0)
> +
> +#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4)
> +#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8)
> +
> +#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC)
> +#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0)
> +#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4)
> +
> +struct pad_iomux {
> + u8 mod;
> + u8 spd;
> + u8 sre;
> + u8 ode;
> + u8 hys;
> + u8 dse;
> + u8 pus;
> + u8 pke;
> + u8 pue;
> + u8 obe;
> + u8 ibe;
> +};
Add some comments, the fields are not so self explaining
> +
> +#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, \
> + dse, pus, pke, pue, obe, ibe) \
> + (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \
> + ((sre & 1) << 11) | ((ode & 1) << 10) | \
> + ((hys & 1) << 9) | ((dse & 7) << 6) | \
> + ((pus & 3) << 4) | ((pke & 1) << 3) | \
> + ((pue & 1) << 2) | ((obe & 1) << 1) | \
> + (ibe & 1)))
> +
> +#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \
> + (((inp & 1) << 16) | ((trim & 3) << 14) | \
> + ((hys & 1) << 9) | ((dse & 7) << 6) | \
> + ((pus & 3) << 4) | ((pke & 1) << 3) | \
> + ((pue & 1) << 2))
> +
> +#define MUX_MODE_ALT0 0x00
> +#define MUX_MODE_ALT1 0x01
> +#define MUX_MODE_ALT2 0x02
> +#define MUX_MODE_ALT3 0x03
> +#define MUX_MODE_ALT4 0x04
> +#define MUX_MODE_ALT5 0x05
> +#define MUX_MODE_ALT6 0x06
> +#define MUX_MODE_ALT7 0x07
> +
> +#define MUX_SPD_50MHZ 0x00
> +#define MUX_SPD_100MHZ 0x02
> +#define MUX_SPD_200MHZ 0x03
> +
> +#define MUX_SRE_SLOW 0
> +#define MUX_SRE_FAST 1
> +
> +#define MUX_ODE_CMOS 0
> +#define MUX_ODE_OPEN 1
> +
> +#define MUX_HYS_CMOS 0
> +#define MUX_HYS_SCHMITT 1
> +
> +#define MUX_DSE_20_OHM 7
> +#define MUX_DSE_25_OHM 6
> +#define MUX_DSE_30_OHM 5
> +#define MUX_DSE_37_OHM 4
> +#define MUX_DSE_50_OHM 3
> +#define MUX_DSE_75_OHM 2
> +#define MUX_DSE_150_OHM 1
> +#define MUX_DSE_DIS 0
> +
> +#define MUX_PUS_22KOHM_UP 3
> +#define MUX_PUS_100KOHM_UP 2
> +#define MUX_PUS_47KOHM_UP 1
> +#define MUX_PUS_100KOHM_DN 0
> +
> +#define MUX_PKE_EN 1
> +#define MUX_PKE_DIS 0
> +
> +#define MUX_PUE_PULLEN 1
> +#define MUX_PUE_KEEPEREN 0
> +
> +#define MUX_OBE_EN 1
> +#define MUX_OBE_DIS 0
> +
> +#define MUX_IBE_EN 1
> +#define MUX_IBE_DIS 0
> +
> +#define MUX_DDR_INPUT_DIFF 1
> +#define MUX_DDR_INPUT_CMOS 0
> +
> +#define MUX_DDR_TRIM_150PS 3
> +#define MUX_DDR_TRIM_100PS 2
> +#define MUX_DDR_TRIM_50PS 1
> +#define MUX_DDR_TRIM_MIN 0
> +
> +void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio);
> +
> +#endif /* __MACH_VYBRID_IOMUX_H__ */
> diff --git a/arch/arm/include/asm/arch-vybrid/serial-vybrid.h b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> new file mode 100644
> index 0000000..9575f73
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> @@ -0,0 +1,213 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __SERIAL_VYBRID_H__
> +#define __SERIAL_VYBRID_H__
> +
> +#define UBDH 0x00
> +#define UBDL 0x01
> +#define UC1 0x02
> +#define UC2 0x03
> +#define US1 0x04
> +#define US2 0x05
> +#define UC3 0x06
> +#define UD 0x07
> +#define UMA1 0x08
> +#define UMA2 0x09
> +#define UC4 0x0A
> +#define UC5 0x0B
> +#define UED 0x0C
These are offset - please replace with C structures, thanks.
> +#define UMODEM 0x0D
> +#define UIR 0x0E
> +#define UPFIFO 0x10
> +#define UCFIFO 0x11
> +#define USFIFO 0x12
> +#define UTWFIFO 0x13
> +#define UTCFIFO 0x14
> +#define URWFIFO 0x15
> +#define URCFIFO 0x16
> +#define UC7816 0x18
> +#define UIE7816 0x19
> +#define UIS7816 0x1A
> +#define UWP7816T0 0x1B
> +#define UWP7816T1 0x1B
> +#define UWN7816 0x1C
> +#define UWF7816 0x1D
> +#define UET78416 0x1E
> +#define UTL7816 0x1F
> +#define UC6 0x21
> +#define UPCTH 0x22
> +#define UPCTL 0x23
> +#define UB1T 0x24
> +#define USDTH 0x25
> +#define USDTL 0x26
> +#define UPRE 0x27
> +#define UTPL 0x28
> +#define UIE 0x29
> +#define UWB 0x2A
> +#define US3 0x2B
> +#define US4 0x2C
> +#define UPRL 0x2D
> +#define URPREL 0x2E
> +#define UCPW 0x2F
> +#define URIDT 0x30
> +#define UTIDT 0x31
> +
> +#define UBDH_LBKDIE (1 << 7)
> +#define UBDH_RXEDGIE (1 << 6)
> +#define UBDH_SBR(x) (x & 0x1F)
> +
> +#define UC1_LOOPS (1 << 7)
> +#define UC1_SWAI (1 << 6)
> +#define UC1_RSRC (1 << 5)
> +#define UC1_M (1 << 4)
> +#define UC1_WAKE (1 << 3)
> +#define UC1_ILT (1 << 2)
> +#define UC1_PE (1 << 1)
> +#define UC1_PT (1 << 0)
> +
> +#define UC2_TIE (1 << 7)
> +#define UC2_TCIE (1 << 6)
> +#define UC2_RIE (1 << 5)
> +#define UC2_ILIE (1 << 4)
> +#define UC2_TE (1 << 3)
> +#define UC2_RE (1 << 2)
> +#define UC2_RWU (1 << 1)
> +#define UC2_SBK (1 << 0)
> +
> +#define US1_TDRE (1 << 7)
> +#define US1_TC (1 << 6)
> +#define US1_RDRF (1 << 5)
> +#define US1_IDLE (1 << 4)
> +#define US1_OR (1 << 3)
> +#define US1_NF (1 << 2)
> +#define US1_FE (1 << 1)
> +#define US1_PF (1 << 0)
> +
> +#define US2_LBKDIF (1 << 7)
> +#define US2_RXEDGIF (1 << 6)
> +#define US2_MSBF (1 << 5)
> +#define US2_RXINV (1 << 4)
> +#define US2_RWUID (1 << 3)
> +#define US2_BRK13 (1 << 2)
> +#define US2_RBKDE (1 << 1)
> +#define US2_RAF (1 << 0)
> +
> +#define UC3_R8 (1 << 7)
> +#define UC3_T8 (1 << 6)
> +#define UC3_TXDIR (1 << 5)
> +#define UC3_TXINV (1 << 4)
> +#define UC3_ORIE (1 << 3)
> +#define UC3_NEIF (1 << 2)
> +#define UC3_FEIF (1 << 1)
> +#define UC3_PEIE (1 << 0)
> +
> +#define UC4_MAEN1 (1 << 7)
> +#define UC4_MAEN2 (1 << 6)
> +#define UC4_M10 (1 << 5)
> +#define UC4_BRFA(x) (x & 0x1F)
> +
> +#define UC5_TDMAS (1 << 7)
> +#define UC5_RDMAS (1 << 5)
> +
> +#define UED_NOISY (1 << 7)
> +#define UED_PARITYE (1 << 6)
> +
> +#define UMODEM_RXRTSE (1 << 3)
> +#define UMODEM_TXRTSPOL (1 << 2)
> +#define UMODEM_TXRTSE (1 << 1)
> +#define UMODEM_TXCTSE (1 << 0)
> +
> +#define UIR_IREN (1 << 2)
> +#define UIR_TNP(x) (x & 3)
> +
> +#define UPFIFO_TXFE (1 << 7)
> +#define UPFIFO_TXFSZ(x) ((x & 7) << 4)
> +#define UPFIFO_RXFE (1 << 3)
> +#define UPFIFO_RXFSZ(x) ((x & 7) << 0)
> +
> +#define UCFIFO_TXFLUSH (1 << 7)
> +#define UCFIFO_RXFLUSH (1 << 6)
> +#define UCFIFO_TXOFE (1 << 1)
> +#define UCFIFO_RXUFE (1 << 0)
> +
> +#define USFIFO_TXEMPT (1 << 7)
> +#define USFIFO_RXEMPT (1 << 6)
> +#define USFIFO_TXOF (1 << 1)
> +#define USFIFO_RXUF (1 << 0)
> +
> +#define UC7816_ONACK (1 << 4)
> +#define UC7816_ANACK (1 << 3)
> +#define UC7816_INIT (1 << 2)
> +#define UC7816_TTYPE (1 << 1)
> +#define UC7816_7816E (1 << 0)
> +
> +#define UIE7816_WTE (1 << 7)
> +#define UIE7816_CWTE (1 << 6)
> +#define UIE7816_BWTE (1 << 5)
> +#define UIE7816_INITDE (1 << 4)
> +#define UIE7816_GTVE (1 << 2)
> +#define UIE7816_TXTE (1 << 1)
> +#define UIE7816_RXTE (1 << 0)
> +
> +#define UIS7816_WTE (1 << 7)
> +#define UIS7816_CWTE (1 << 6)
> +#define UIS7816_BWTE (1 << 5)
> +#define UIS7816_INITDE (1 << 4)
> +#define UIS7816_GTVE (1 << 2)
> +#define UIS7816_TXTE (1 << 1)
> +#define UIS7816_RXTE (1 << 0)
> +
> +#define UWP7816T1_CWI(x) ((x & 0xf) << 4)
> +#define UWP7816T1_BWI(x) ((x & 0xf) << 0)
> +
> +#define UET78416_TXTHRESHOLD(x) ((x & 0xf) << 4)
> +#define UET78416_RXTHRESHOLD(x) ((x & 0xf) << 0)
> +
> +#define UC6_EN709 (1 << 7)
> +#define UC6_TX709 (1 << 6)
> +#define UC6_CE (1 << 5)
> +#define UC6_CP (1 << 4)
> +
> +#define UIE_WBEIE (1 << 6)
> +#define UIE_ISDIE (1 << 5)
> +#define UIE_PRXIE (1 << 4)
> +#define UIE_PTXIE (1 << 3)
> +#define UIE_PCTEIE (1 << 2)
> +#define UIE_PSIE (1 << 1)
> +#define UIE_TXFIE (1 << 0)
> +
> +#define US3_PEF (1 << 7)
> +#define US3_WBEF (1 << 6)
> +#define US3_ISD (1 << 5)
> +#define US3_PRXF (1 << 4)
> +#define US3_PTXF (1 << 3)
> +#define US3_PCTEF (1 << 2)
> +#define US3_PSF (1 << 1)
> +#define US3_TXFF (1 << 0)
> +
> +#define US4_INITF (1 << 4)
> +#define US4_CDET(x) ((x & 3) << 2)
> +#define US4_ILCV (1 << 1)
> +#define US4_FE (1 << 0)
> +
> +#endif /* __SERIAL_VYBRID_H__ */
> diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h b/arch/arm/include/asm/arch-vybrid/sys_proto.h
> new file mode 100644
> index 0000000..7e2de97
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SYS_PROTO_H_
> +#define _SYS_PROTO_H_
> +
> +u32 get_cpu_rev(void);
> +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
> +void sdelay(unsigned long);
We get rid of sdelay() and we use udelay() when it is possible. I do not
know if this is the case.
> diff --git a/arch/arm/include/asm/arch-vybrid/timer.h b/arch/arm/include/asm/arch-vybrid/timer.h
> new file mode 100644
> index 0000000..55497e3
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-vybrid/timer.h
> @@ -0,0 +1,405 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_TIMER_H
> +#define __ASM_ARCH_TIMER_H
> +
> +struct ftm_regs {
> + u32 sc; /* 0x00 */
> + u32 cnt; /* 0x04 */
> + u32 mod; /* 0x08 */
> + u32 c0sc; /* 0x0C */
> + u32 c0v; /* 0x10 */
> + u32 c1sc; /* 0x14 */
> + u32 c1v; /* 0x18 */
> + u32 c2sc; /* 0x1C */
> + u32 c2v; /* 0x20 */
> + u32 c3sc; /* 0x24 */
> + u32 c3v; /* 0x28 */
> + u32 c4sc; /* 0x2C */
> + u32 c4v; /* 0x30 */
> + u32 c5sc; /* 0x34 */
> + u32 c5v; /* 0x38 */
> + u32 c6sc; /* 0x3C */
> + u32 c6v; /* 0x40 */
> + u32 c7sc; /* 0x44 */
> + u32 c7v; /* 0x48 */
> + u32 cntin; /* 0x4C */
> + u32 status; /* 0x50 */
> + u32 mode; /* 0x54 */
> + u32 sync; /* 0x58 */
> + u32 outinit; /* 0x5C */
> + u32 outmask; /* 0x60 */
> + u32 combine; /* 0x64 */
> + u32 deadtime; /* 0x68 */
> + u32 exttrig; /* 0x6C */
> + u32 pol; /* 0x70 */
> + u32 fms; /* 0x74 */
> + u32 filter; /* 0x78 */
> + u32 fltctrl; /* 0x7C */
> + u32 qdctrl; /* 0x80 */
> + u32 conf; /* 0x84 */
> + u32 fltpol; /* 0x88 */
> + u32 synconf; /* 0x8C */
> + u32 invctrl; /* 0x90 */
> + u32 swoctrl; /* 0x94 */
> + u32 pwmload; /* 0x98 */
> +};
> +
> +struct pit2_regs {
> + u32 ldval; /* 0x00 */
> + u32 cval; /* 0x04 */
> + u32 tctrl; /* 0x08 */
> + u32 tflg; /* 0x0C */
> +};
> +
> +struct pit_regs {
> + u32 mcr; /* 0x00 */
> + u32 rsvd0[55];
> + u32 ltmr64h; /* 0xE0 */
> + u32 ltmr64l; /* 0xE4 */
> + u32 rsvd1[6];
> + struct pit2_regs counter[8]; /* 0x100 */
> +};
> +
> +struct lptmr_regs {
> + u32 csr; /* 0x00 */
> + u32 psr; /* 0x04 */
> + u32 cmr; /* 0x08 */
> + u32 cnr; /* 0x0C */
> +};
Comments with offset are not very useful, drop them.
> diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> new file mode 100644
> index 0000000..225a1e1
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_ARCH_VYBRID_PINS_H__
> +#define __ASM_ARCH_VYBRID_PINS_H__
> +
> +#ifndef __ASSEMBLY__
> +
> +/*!
> + * Starting bit position within each entry of \b iomux_pins to represent the
> + * MUX control register offset
> + */
> +#define MUX_I 0
You use inconsistently doxygen comments. As I remember, there is no
decision to use it in the project, so please remove the meta chars.
> +/*!
> + * Starting bit position within each entry of \b iomux_pins to represent the
> + * PAD control register offset
> + */
> +#define PAD_I 10
> +/*!
> + * Starting bit position within each entry of \b iomux_pins to represent which
> + * mux mode is for GPIO (0-based)
> + */
> +#define GPIO_I 21
> +
> +#define MUX_IO_P 29
> +#define MUX_IO_I 24
> +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
> + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
> + ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
> +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
> +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
> +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
I prefer you use the same convention we have for other Freescale's SOC,
that is PORT starts from 1 and not from zero. Check if you can use the
macros already set for MX% / MX6.
> +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
> +#define AIPS0_BASE_ADDR 0x40000000
> +#define AIPS1_BASE_ADDR 0x40080000
> +#define CSD0_BASE_ADDR 0x80000000 /* ddr 0 */
> +#define CSD1_BASE_ADDR 0xa0000000 /* ddr 1 */
> +
> +#define IRAM_SIZE 0x00040000 /* 256 KB */
> +
> +/* AIPS 0 */
> +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
> +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
> +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
> +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
> +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
> +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
> +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
> +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
> +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
> +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
> +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
> +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
> +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
> +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
> +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
> +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
> +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
> +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
> +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
> +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
> +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
> +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
> +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
> +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
> +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
> +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
> +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
> +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
> +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
> +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
> +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
> +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
> +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
> +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
> +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
> +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
> +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
> +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
> +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
> +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
> +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
> +#define WDOG_A5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
> +#define WDOG_M4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
> +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
> +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
> +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
> +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
> +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
> +#define ANATOP_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
> +#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
> +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
> +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
> +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
> +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
> +#define EWDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
> +#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
> +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
> +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
> +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
> +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
> +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
> +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
> +
> +/* AIPS 1 */
> +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
> +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
> +#define ESDHC2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
> +#define QSPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
> +#define MACNET0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
> +#define MACNET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
> +
> +/* WEIM CSnGCR1 */
> +#define CSEN 1
> +#define SWR (1 << 1)
> +#define SRD (1 << 2)
> +#define MUM (1 << 3)
> +#define WFL (1 << 4)
> +#define RFL (1 << 5)
> +#define CRE (1 << 6)
> +#define CREP (1 << 7)
> +#define BL(x) (((x) & 0x7) << 8)
> +#define WC (1 << 11)
> +#define BCD(x) (((x) & 0x3) << 12)
> +#define BCS(x) (((x) & 0x3) << 14)
> +#define DSZ(x) (((x) & 0x7) << 16)
> +#define SP (1 << 19)
> +#define CSREC(x) (((x) & 0x7) << 20)
> +#define AUS (1 << 23)
> +#define GBC(x) (((x) & 0x7) << 24)
> +#define WP (1 << 27)
> +#define PSZ(x) (((x) & 0x0f << 28)
> +
> +/* WEIM CSnGCR2 */
> +#define ADH(x) (((x) & 0x3))
> +#define DAPS(x) (((x) & 0x0f << 4)
> +#define DAE (1 << 8)
> +#define DAP (1 << 9)
> +#define MUX16_BYP (1 << 12)
> +
> +/* WEIM CSnRCR1 */
> +#define RCSN(x) (((x) & 0x7))
> +#define RCSA(x) (((x) & 0x7) << 4)
> +#define OEN(x) (((x) & 0x7) << 8)
> +#define OEA(x) (((x) & 0x7) << 12)
> +#define RADVN(x) (((x) & 0x7) << 16)
> +#define RAL (1 << 19)
> +#define RADVA(x) (((x) & 0x7) << 20)
> +#define RWSC(x) (((x) & 0x3f) << 24)
> +
> +/* WEIM CSnRCR2 */
> +#define RBEN(x) (((x) & 0x7))
> +#define RBE (1 << 3)
> +#define RBEA(x) (((x) & 0x7) << 4)
> +#define RL(x) (((x) & 0x3) << 8)
> +#define PAT(x) (((x) & 0x7) << 12)
> +#define APR (1 << 15)
> +
> +/* WEIM CSnWCR1 */
> +#define WCSN(x) (((x) & 0x7))
> +#define WCSA(x) (((x) & 0x7) << 3)
> +#define WEN(x) (((x) & 0x7) << 6)
> +#define WEA(x) (((x) & 0x7) << 9)
> +#define WBEN(x) (((x) & 0x7) << 12)
> +#define WBEA(x) (((x) & 0x7) << 15)
> +#define WADVN(x) (((x) & 0x7) << 18)
> +#define WADVA(x) (((x) & 0x7) << 21)
> +#define WWSC(x) (((x) & 0x3f) << 24)
> +#define WBED1 (1 << 30)
> +#define WAL (1 << 31)
> +
> +/* WEIM CSnWCR2 */
> +#define WBED 1
> +
> +/* WEIM WCR */
> +#define BCM 1
> +#define GBCD(x) (((x) & 0x3) << 1)
> +#define INTEN (1 << 4)
> +#define INTPOL (1 << 5)
> +#define WDOG_EN (1 << 8)
> +#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
> +
> +/* Number of GPIO pins per port */
> +#define GPIO_NUM_PIN 32
> +
> +#define IIM_SREV 0x24
> +#define ROM_SI_REV 0x80
> +
> +#define NFC_BUF_SIZE 0x1000
> +
> +#define CHIP_REV_1_0 0x10
> +#define CHIP_REV_1_1 0x11
> +#define CHIP_REV_2_0 0x20
> +#define CHIP_REV_2_5 0x25
> +#define CHIP_REV_3_0 0x30
> +
> +#define BOARD_REV_1_0 0x0
> +#define BOARD_REV_2_0 0x1
> +
> +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
> +#include <asm/types.h>
> +
> +struct clkctl {
> + u32 ccr; /* 0x00 */
> + u32 csr; /* 0x04 */
> + u32 ccsr; /* 0x08 */
> + u32 cacrr; /* 0x0C */
> + u32 cscmr1; /* 0x10 */
> + u32 cscdr1; /* 0x14 */
> + u32 cscdr2; /* 0x18 */
> + u32 cscdr3; /* 0x1C */
> + u32 cscmr2; /* 0x20 */
> + u32 cscdr4; /* 0x24 */
> + u32 ctor; /* 0x28 */
> + u32 clpcr; /* 0x2C */
> + u32 cisr; /* 0x30 */
> + u32 cimr; /* 0x34 */
> + u32 ccosr; /* 0x38 */
> + u32 cgpr; /* 0x3C */
> + u32 ccgr0; /* 0x40 */
> + u32 ccgr1; /* 0x44 */
> + u32 ccgr2; /* 0x48 */
> + u32 ccgr3; /* 0x4C */
> + u32 ccgr4; /* 0x50 */
> + u32 ccgr5; /* 0x54 */
> + u32 ccgr6; /* 0x58 */
> + u32 ccgr7; /* 0x5C */
> + u32 ccgr8; /* 0x60 */
> + u32 ccgr9; /* 0x64 */
> + u32 ccgr10; /* 0x68 */
> + u32 ccgr11; /* 0x6C */
> + u32 cmeor0; /* 0x70 */
> + u32 cmeor1; /* 0x74 */
> + u32 cmeor2; /* 0x78 */
> + u32 cmeor3; /* 0x7C */
> + u32 cmeor4; /* 0x80 */
> + u32 cmeor5; /* 0x84 */
> + u32 cppdsr; /* 0x88 */
> + u32 ccowr; /* 0x8C */
> + u32 ccpgr0; /* 0x90 */
> + u32 ccpgr1; /* 0x94 */
> + u32 ccpgr2; /* 0x98 */
> + u32 ccpgr3; /* 0x9C */
> +};
> +
> +/* WEIM registers */
> +struct weim {
> + u32 cs0gcr1;
> + u32 cs0gcr2;
> + u32 cs0rcr1;
> + u32 cs0rcr2;
> + u32 cs0wcr1;
> + u32 cs0wcr2;
> + u32 cs1gcr1;
> + u32 cs1gcr2;
> + u32 cs1rcr1;
> + u32 cs1rcr2;
> + u32 cs1wcr1;
> + u32 cs1wcr2;
> + u32 cs2gcr1;
> + u32 cs2gcr2;
> + u32 cs2rcr1;
> + u32 cs2rcr2;
> + u32 cs2wcr1;
> + u32 cs2wcr2;
> + u32 cs3gcr1;
> + u32 cs3gcr2;
> + u32 cs3rcr1;
> + u32 cs3rcr2;
> + u32 cs3wcr1;
> + u32 cs3wcr2;
> + u32 cs4gcr1;
> + u32 cs4gcr2;
> + u32 cs4rcr1;
> + u32 cs4rcr2;
> + u32 cs4wcr1;
> + u32 cs4wcr2;
> + u32 cs5gcr1;
> + u32 cs5gcr2;
> + u32 cs5rcr1;
> + u32 cs5rcr2;
> + u32 cs5wcr1;
> + u32 cs5wcr2;
> + u32 wcr;
> + u32 wiar;
> + u32 ear;
> +};
> +
I think about if we cann avoid to duplicate another time this structure,
moving it into a common place. See MX5 struct weim.
> +struct anadig {
> + u32 usb1_pll_ctrl;
> + u32 usb2_pll_ctrl;
> + u32 pll_528_ctrl;
> + u32 pll_528_ss;
> + u32 pll_528_num;
> + u32 pll_528_denom;
> + u32 pll_aud_ctrl;
> + u32 pll_aud_num;
> + u32 pll_aud_denom;
> + u32 pll_vid_ctrl;
> + u32 pll_vid_num;
> + u32 pll_vid_denom;
> + u32 pll_enet_ctrl;
> + u32 pll_pfd_480_usb1;
> + u32 pll_pfd_528;
> + u32 reg_1p1;
> + u32 reg_3p0;
> + u32 reg_2p5;
> + u32 ana_misc0;
> + u32 ana_misc1;
> + u32 tempsens0;
> + u32 usb1_vbus_det;
> + u32 usb1_vbus_chrg_det;
> + u32 usb1_vbus_detsta;
> + u32 usb1_chrg_detsta;
> + u32 usb1_loopback;
> + u32 usb1_misc;
> + u32 usb2_vbus_det;
> + u32 usb2_vbus_chrg_det;
> + u32 usb2_vbus_detsta;
> + u32 usb2_chrg_detsta;
> + u32 usb2_loopback;
> + u32 usb2_misc;
> + u32 digprog;
> + u32 pll_sys_ctrl;
> + u32 pll_sys_ss;
> + u32 pll_sys_num;
> + u32 pll_sys_denom;
> + u32 pfd_528_sys;
> + u32 pll_lock;
> +};
> +
> +struct iomuxc {
> + u32 gpr0;
> + u32 gpr1;
> + u32 omux0;
> + u32 omux1;
> + u32 omux2;
> + u32 omux3;
> + u32 omux4;
> +};
> +
> +/* System Reset Controller (SRC) */
> +struct src {
> + u32 scr; /* 0x00 */
> + u32 sbmr1; /* 0x04 */
> + u32 srsr; /* 0x08 */
> + u32 secr; /* 0x0C */
> + u32 gpsr; /* 0x10 */
> + u32 sicr; /* 0x14 */
> + u32 simr; /* 0x18 */
> + u32 sbmr2; /* 0x1C */
> + u32 gpr0; /* 0x20 */
> + u32 gpr1; /* 0x24 */
> + u32 gpr2; /* 0x28 */
> + u32 gpr3; /* 0x2C */
> + u32 gpr4; /* 0x30 */
> + u32 hab0; /* 0x34 */
> + u32 hab1; /* 0x38 */
> + u32 hab2; /* 0x3C */
> + u32 hab3; /* 0x40 */
> + u32 hab4; /* 0x44 */
> + u32 hab5; /* 0x48 */
> + u32 misc0; /* 0x4C */
> + u32 misc1; /* 0x50 */
> + u32 misc2; /* 0x54 */
> + u32 misc3; /* 0x58 */
> +};
> +
> +struct fuse_bank1_regs {
> + u32 fuse0_8[9];
> + u32 mac_addr[6];
> + u32 fuse15_31[0x11];
> +};
> +
> +#define ANADIG_USB1_PLL_CTRL (0x10)
> +#define ANADIG_USB2_PLL_CTRL (0x20)
> +#define ANADIG_PLL_528_CTRL (0x30)
> +#define ANADIG_PLL_528_SS (0x40)
> +#define ANADIG_PLL_528_NUM (0x50)
> +#define ANADIG_PLL_528_DENOM (0x60)
> +#define ANADIG_PLL_AUD_CTRL (0x70)
> +#define ANADIG_PLL_AUD_NUM (0x80)
> +#define ANADIG_PLL_AUD_DENOM (0x90)
> +#define ANADIG_PLL_VID_CTRL (0xA0)
> +#define ANADIG_PLL_VID_NUM (0xB0)
> +#define ANADIG_PLL_VID_DENOM (0xC0)
> +#define ANADIG_PLL_ENET_CTRL (0xE0)
> +#define ANADIG_PLL_PFD_480_USB1 (0xF0)
> +#define ANADIG_PLL_PFD_528 (0x100)
> +#define ANADIG_REG_1P1 (0x110)
> +#define ANADIG_REG_3P0 (0x120)
> +#define ANADIG_REG_2P5 (0x130)
> +#define ANADIG_ANA_MISC0 (0x150)
> +#define ANADIG_ANA_MISC1 (0x160)
> +#define ANADIG_TEMPSENS0 (0x180)
> +#define ANADIG_USB1_VBUS_DET (0x1A0)
> +#define ANADIG_USB1_CHRG_DET (0x1B0)
> +#define ANADIG_USB1_VBUS_DETSTA (0x1C0)
> +#define ANADIG_UAB1_CHRG_DETSTA (0x1D0)
> +#define ANADIG_USB1_LOOPBACK (0x1E0)
> +#define ANADIG_USB1_MISC (0x1F0)
> +#define ANADIG_USB2_VBUS_DET (0x200)
> +#define ANADIG_USB2_CHRG_DET (0x210)
> +#define ANADIG_USB2_VBUS_DETSTA (0x220)
> +#define ANADIG_USB2_CHRG_DETSTA (0x230)
> +#define ANADIG_USB2_LOOPBACK (0x240)
> +#define ANADIG_USB2_MISC (0x250)
> +#define ANADIG_DIGPROG (0x260)
> +#define ANADIG_PLL_SYS_CTRL (0x270)
> +#define ANADIG_PLL_SYS_SS (0x280)
> +#define ANADIG_PLL_SYS_NUM (0x290)
> +#define ANADIG_PLL_SYS_DENOM (0x2A0)
> +#define ANADIG_PFD_528_SYS (0x2B0)
> +#define ANADIG_PLL_LOCK (0x2C0)
> +
> +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
> +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
> +
> +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
> +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
> +
> +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
> +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
> +
> +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
> +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
> +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
> +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
> +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
> +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
> +
> +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
> +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
> +
> +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
> +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
> +
> +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
> +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
> +
> +#define FASE_CLK_FREQ 24000000
> +#define SLOW_CLK_FREQ 32000
> +#define PLL1_PFD1_FREQ 500000000
> +#define PLL1_PFD2_FREQ 452000000
> +#define PLL1_PFD3_FREQ 396000000
> +#define PLL1_PFD4_FREQ 528000000
> +#define PLL1_MAIN_FREQ 528000000
> +#define PLL2_PFD1_FREQ 500000000
> +#define PLL2_PFD2_FREQ 396000000
> +#define PLL2_PFD3_FREQ 339000000
> +#define PLL2_PFD4_FREQ 413000000
> +#define PLL2_MAIN_FREQ 528000000
> +#define PLL3_MAIN_FREQ 480000000
> +#define PLL3_PFD3_FREQ 298000000
> +#define PLL5_MAIN_FREQ 500000000
> +
> +#define ENET_EXTERNAL_CLK 50000000
> +#define AUDIO_EXTERNAL_CLK 24576000
> +
> +#define DDR_CR_BASE DDR_BASE_ADDR
> +#define DDR_PHY_BASE (DDR_BASE_ADDR + 0x400)
> +
> +#define DDR_CR000 (DDR_CR_BASE + 0x000)
> +#define DDR_CR001 (DDR_CR_BASE + 0x004)
> +#define DDR_CR002 (DDR_CR_BASE + 0x008)
> +#define DDR_CR003 (DDR_CR_BASE + 0x00C)
> +#define DDR_CR004 (DDR_CR_BASE + 0x010)
> +#define DDR_CR005 (DDR_CR_BASE + 0x014)
> +#define DDR_CR006 (DDR_CR_BASE + 0x018)
> +#define DDR_CR007 (DDR_CR_BASE + 0x01C)
> +#define DDR_CR008 (DDR_CR_BASE + 0x020)
> +#define DDR_CR009 (DDR_CR_BASE + 0x024)
> +
> +#define DDR_CR010 (DDR_CR_BASE + 0x028)
> +#define DDR_CR011 (DDR_CR_BASE + 0x02C)
> +#define DDR_CR012 (DDR_CR_BASE + 0x030)
> +#define DDR_CR013 (DDR_CR_BASE + 0x034)
> +#define DDR_CR014 (DDR_CR_BASE + 0x038)
> +#define DDR_CR015 (DDR_CR_BASE + 0x03C)
> +#define DDR_CR016 (DDR_CR_BASE + 0x040)
> +#define DDR_CR017 (DDR_CR_BASE + 0x044)
> +#define DDR_CR018 (DDR_CR_BASE + 0x048)
> +#define DDR_CR019 (DDR_CR_BASE + 0x04C)
> +
> +#define DDR_CR020 (DDR_CR_BASE + 0x050)
> +#define DDR_CR021 (DDR_CR_BASE + 0x054)
> +#define DDR_CR022 (DDR_CR_BASE + 0x058)
> +#define DDR_CR023 (DDR_CR_BASE + 0x05C)
> +#define DDR_CR024 (DDR_CR_BASE + 0x060)
> +#define DDR_CR025 (DDR_CR_BASE + 0x064)
> +#define DDR_CR026 (DDR_CR_BASE + 0x068)
> +#define DDR_CR027 (DDR_CR_BASE + 0x06C)
> +#define DDR_CR028 (DDR_CR_BASE + 0x070)
> +#define DDR_CR029 (DDR_CR_BASE + 0x074)
> +
> +#define DDR_CR030 (DDR_CR_BASE + 0x078)
> +#define DDR_CR031 (DDR_CR_BASE + 0x07C)
> +#define DDR_CR032 (DDR_CR_BASE + 0x080)
> +#define DDR_CR033 (DDR_CR_BASE + 0x084)
> +#define DDR_CR034 (DDR_CR_BASE + 0x088)
> +#define DDR_CR035 (DDR_CR_BASE + 0x08C)
> +#define DDR_CR036 (DDR_CR_BASE + 0x090)
> +#define DDR_CR037 (DDR_CR_BASE + 0x094)
> +#define DDR_CR038 (DDR_CR_BASE + 0x098)
> +#define DDR_CR039 (DDR_CR_BASE + 0x09C)
> +
> +#define DDR_CR040 (DDR_CR_BASE + 0x0A0)
> +#define DDR_CR041 (DDR_CR_BASE + 0x0A4)
> +#define DDR_CR042 (DDR_CR_BASE + 0x0A8)
> +#define DDR_CR043 (DDR_CR_BASE + 0x0AC)
> +#define DDR_CR044 (DDR_CR_BASE + 0x0B0)
> +#define DDR_CR045 (DDR_CR_BASE + 0x0B4)
> +#define DDR_CR046 (DDR_CR_BASE + 0x0B8)
> +#define DDR_CR047 (DDR_CR_BASE + 0x0BC)
> +#define DDR_CR048 (DDR_CR_BASE + 0x0C0)
> +#define DDR_CR049 (DDR_CR_BASE + 0x0C4)
> +
> +#define DDR_CR050 (DDR_CR_BASE + 0x0C8)
> +#define DDR_CR051 (DDR_CR_BASE + 0x0CC)
> +#define DDR_CR052 (DDR_CR_BASE + 0x0D0)
> +#define DDR_CR053 (DDR_CR_BASE + 0x0D4)
> +#define DDR_CR054 (DDR_CR_BASE + 0x0D8)
> +#define DDR_CR055 (DDR_CR_BASE + 0x0DC)
> +#define DDR_CR056 (DDR_CR_BASE + 0x0E0)
> +#define DDR_CR057 (DDR_CR_BASE + 0x0E4)
> +#define DDR_CR058 (DDR_CR_BASE + 0x0E8)
> +#define DDR_CR059 (DDR_CR_BASE + 0x0EC)
> +
> +#define DDR_CR060 (DDR_CR_BASE + 0x0F0)
> +#define DDR_CR061 (DDR_CR_BASE + 0x0F4)
> +#define DDR_CR062 (DDR_CR_BASE + 0x0F8)
> +#define DDR_CR063 (DDR_CR_BASE + 0x0FC)
> +#define DDR_CR064 (DDR_CR_BASE + 0x100)
> +#define DDR_CR065 (DDR_CR_BASE + 0x104)
> +#define DDR_CR066 (DDR_CR_BASE + 0x108)
> +#define DDR_CR067 (DDR_CR_BASE + 0x10C)
> +#define DDR_CR068 (DDR_CR_BASE + 0x110)
> +#define DDR_CR069 (DDR_CR_BASE + 0x114)
> +
> +#define DDR_CR070 (DDR_CR_BASE + 0x118)
> +#define DDR_CR071 (DDR_CR_BASE + 0x11C)
> +#define DDR_CR072 (DDR_CR_BASE + 0x120)
> +#define DDR_CR073 (DDR_CR_BASE + 0x124)
> +#define DDR_CR074 (DDR_CR_BASE + 0x128)
> +#define DDR_CR075 (DDR_CR_BASE + 0x12C)
> +#define DDR_CR076 (DDR_CR_BASE + 0x130)
> +#define DDR_CR077 (DDR_CR_BASE + 0x134)
> +#define DDR_CR078 (DDR_CR_BASE + 0x138)
> +#define DDR_CR079 (DDR_CR_BASE + 0x13C)
> +
> +#define DDR_CR080 (DDR_CR_BASE + 0x140)
> +#define DDR_CR081 (DDR_CR_BASE + 0x144)
> +#define DDR_CR082 (DDR_CR_BASE + 0x148)
> +#define DDR_CR083 (DDR_CR_BASE + 0x14C)
> +#define DDR_CR084 (DDR_CR_BASE + 0x150)
> +#define DDR_CR085 (DDR_CR_BASE + 0x154)
> +#define DDR_CR086 (DDR_CR_BASE + 0x158)
> +#define DDR_CR087 (DDR_CR_BASE + 0x15C)
> +#define DDR_CR088 (DDR_CR_BASE + 0x160)
> +#define DDR_CR089 (DDR_CR_BASE + 0x164)
> +
> +#define DDR_CR090 (DDR_CR_BASE + 0x168)
> +#define DDR_CR091 (DDR_CR_BASE + 0x16C)
> +#define DDR_CR092 (DDR_CR_BASE + 0x170)
> +#define DDR_CR093 (DDR_CR_BASE + 0x174)
> +#define DDR_CR094 (DDR_CR_BASE + 0x178)
> +#define DDR_CR095 (DDR_CR_BASE + 0x17C)
> +#define DDR_CR096 (DDR_CR_BASE + 0x180)
> +#define DDR_CR097 (DDR_CR_BASE + 0x184)
> +#define DDR_CR098 (DDR_CR_BASE + 0x188)
> +#define DDR_CR099 (DDR_CR_BASE + 0x18C)
> +
> +#define DDR_CR100 (DDR_CR_BASE + 0x190)
> +#define DDR_CR101 (DDR_CR_BASE + 0x194)
> +#define DDR_CR102 (DDR_CR_BASE + 0x198)
> +#define DDR_CR103 (DDR_CR_BASE + 0x19C)
> +#define DDR_CR104 (DDR_CR_BASE + 0x1A0)
> +#define DDR_CR105 (DDR_CR_BASE + 0x1A4)
> +#define DDR_CR106 (DDR_CR_BASE + 0x1A8)
> +#define DDR_CR107 (DDR_CR_BASE + 0x1AC)
> +#define DDR_CR108 (DDR_CR_BASE + 0x1B0)
> +#define DDR_CR109 (DDR_CR_BASE + 0x1B4)
> +
> +#define DDR_CR110 (DDR_CR_BASE + 0x1B8)
> +#define DDR_CR111 (DDR_CR_BASE + 0x1BC)
> +#define DDR_CR112 (DDR_CR_BASE + 0x1C0)
> +#define DDR_CR113 (DDR_CR_BASE + 0x1C4)
> +#define DDR_CR114 (DDR_CR_BASE + 0x1C8)
> +#define DDR_CR115 (DDR_CR_BASE + 0x1CC)
> +#define DDR_CR116 (DDR_CR_BASE + 0x1D0)
> +#define DDR_CR117 (DDR_CR_BASE + 0x1D4)
> +#define DDR_CR118 (DDR_CR_BASE + 0x1D8)
> +#define DDR_CR119 (DDR_CR_BASE + 0x1DC)
> +
> +#define DDR_CR120 (DDR_CR_BASE + 0x1E0)
> +#define DDR_CR121 (DDR_CR_BASE + 0x1E4)
> +#define DDR_CR122 (DDR_CR_BASE + 0x1E8)
> +#define DDR_CR123 (DDR_CR_BASE + 0x1EC)
> +#define DDR_CR124 (DDR_CR_BASE + 0x1F0)
> +#define DDR_CR125 (DDR_CR_BASE + 0x1F4)
> +#define DDR_CR126 (DDR_CR_BASE + 0x1F8)
> +#define DDR_CR127 (DDR_CR_BASE + 0x1FC)
> +#define DDR_CR128 (DDR_CR_BASE + 0x200)
> +#define DDR_CR129 (DDR_CR_BASE + 0x204)
> +
> +#define DDR_CR130 (DDR_CR_BASE + 0x208)
> +#define DDR_CR131 (DDR_CR_BASE + 0x20C)
> +#define DDR_CR132 (DDR_CR_BASE + 0x210)
> +#define DDR_CR133 (DDR_CR_BASE + 0x214)
> +#define DDR_CR134 (DDR_CR_BASE + 0x218)
> +#define DDR_CR135 (DDR_CR_BASE + 0x21C)
> +#define DDR_CR136 (DDR_CR_BASE + 0x220)
> +#define DDR_CR137 (DDR_CR_BASE + 0x224)
> +#define DDR_CR138 (DDR_CR_BASE + 0x228)
> +#define DDR_CR139 (DDR_CR_BASE + 0x22C)
> +
> +#define DDR_CR140 (DDR_CR_BASE + 0x230)
> +#define DDR_CR141 (DDR_CR_BASE + 0x234)
> +#define DDR_CR142 (DDR_CR_BASE + 0x238)
> +#define DDR_CR143 (DDR_CR_BASE + 0x23C)
> +#define DDR_CR144 (DDR_CR_BASE + 0x240)
> +#define DDR_CR145 (DDR_CR_BASE + 0x244)
> +#define DDR_CR146 (DDR_CR_BASE + 0x248)
> +#define DDR_CR147 (DDR_CR_BASE + 0x24C)
> +#define DDR_CR148 (DDR_CR_BASE + 0x250)
> +#define DDR_CR149 (DDR_CR_BASE + 0x254)
> +
> +#define DDR_CR150 (DDR_CR_BASE + 0x258)
> +#define DDR_CR151 (DDR_CR_BASE + 0x25C)
> +#define DDR_CR152 (DDR_CR_BASE + 0x260)
> +#define DDR_CR153 (DDR_CR_BASE + 0x264)
> +#define DDR_CR154 (DDR_CR_BASE + 0x268)
> +#define DDR_CR155 (DDR_CR_BASE + 0x26C)
> +#define DDR_CR156 (DDR_CR_BASE + 0x270)
> +#define DDR_CR157 (DDR_CR_BASE + 0x274)
> +#define DDR_CR158 (DDR_CR_BASE + 0x278)
> +#define DDR_CR159 (DDR_CR_BASE + 0x27C)
> +
> +#define DDR_CR160 (DDR_CR_BASE + 0x280)
> +#define DDR_CR161 (DDR_CR_BASE + 0x284)
> +#define DDR_CR162 (DDR_CR_BASE + 0x288)
> +#define DDR_CR163 (DDR_CR_BASE + 0x28C)
> +#define DDR_CR164 (DDR_CR_BASE + 0x290)
> +#define DDR_CR165 (DDR_CR_BASE + 0x294)
> +#define DDR_CR166 (DDR_CR_BASE + 0x298)
> +#define DDR_CR167 (DDR_CR_BASE + 0x29C)
> +#define DDR_CR168 (DDR_CR_BASE + 0x2A0)
> +#define DDR_CR169 (DDR_CR_BASE + 0x2A4)
> +
> +#define DDR_CR170 (DDR_CR_BASE + 0x2A8)
> +#define DDR_CR171 (DDR_CR_BASE + 0x2AC)
> +#define DDR_CR172 (DDR_CR_BASE + 0x2B0)
> +#define DDR_CR173 (DDR_CR_BASE + 0x2B4)
> +#define DDR_CR174 (DDR_CR_BASE + 0x2B8)
> +#define DDR_CR175 (DDR_CR_BASE + 0x2BC)
> +#define DDR_CR176 (DDR_CR_BASE + 0x2C0)
> +#define DDR_CR177 (DDR_CR_BASE + 0x2C4)
> +#define DDR_CR178 (DDR_CR_BASE + 0x2C8)
> +#define DDR_CR179 (DDR_CR_BASE + 0x2CC)
> +
> +/*
> + * PHY
> + */
> +#define DDR_PHY000 (DDR_PHY_BASE + 0x000)
> +#define DDR_PHY001 (DDR_PHY_BASE + 0x004)
> +#define DDR_PHY002 (DDR_PHY_BASE + 0x008)
> +#define DDR_PHY003 (DDR_PHY_BASE + 0x00C)
> +#define DDR_PHY004 (DDR_PHY_BASE + 0x010)
> +#define DDR_PHY005 (DDR_PHY_BASE + 0x014)
> +#define DDR_PHY006 (DDR_PHY_BASE + 0x018)
> +#define DDR_PHY007 (DDR_PHY_BASE + 0x01C)
> +#define DDR_PHY008 (DDR_PHY_BASE + 0x020)
> +#define DDR_PHY009 (DDR_PHY_BASE + 0x024)
> +
> +#define DDR_PHY010 (DDR_PHY_BASE + 0x028)
> +#define DDR_PHY011 (DDR_PHY_BASE + 0x02C)
> +#define DDR_PHY012 (DDR_PHY_BASE + 0x030)
> +#define DDR_PHY013 (DDR_PHY_BASE + 0x034)
> +#define DDR_PHY014 (DDR_PHY_BASE + 0x038)
> +#define DDR_PHY015 (DDR_PHY_BASE + 0x03C)
> +#define DDR_PHY016 (DDR_PHY_BASE + 0x040)
> +#define DDR_PHY017 (DDR_PHY_BASE + 0x044)
> +#define DDR_PHY018 (DDR_PHY_BASE + 0x048)
> +#define DDR_PHY019 (DDR_PHY_BASE + 0x04C)
> +
> +#define DDR_PHY020 (DDR_PHY_BASE + 0x050)
> +#define DDR_PHY021 (DDR_PHY_BASE + 0x054)
> +#define DDR_PHY022 (DDR_PHY_BASE + 0x058)
> +#define DDR_PHY023 (DDR_PHY_BASE + 0x05C)
> +#define DDR_PHY024 (DDR_PHY_BASE + 0x060)
> +#define DDR_PHY025 (DDR_PHY_BASE + 0x064)
> +#define DDR_PHY026 (DDR_PHY_BASE + 0x068)
> +#define DDR_PHY027 (DDR_PHY_BASE + 0x06C)
> +#define DDR_PHY028 (DDR_PHY_BASE + 0x070)
> +#define DDR_PHY029 (DDR_PHY_BASE + 0x074)
> +
> +#define DDR_PHY030 (DDR_PHY_BASE + 0x078)
> +#define DDR_PHY031 (DDR_PHY_BASE + 0x07C)
> +#define DDR_PHY032 (DDR_PHY_BASE + 0x080)
> +#define DDR_PHY033 (DDR_PHY_BASE + 0x084)
> +#define DDR_PHY034 (DDR_PHY_BASE + 0x088)
> +#define DDR_PHY035 (DDR_PHY_BASE + 0x08C)
> +#define DDR_PHY036 (DDR_PHY_BASE + 0x090)
> +#define DDR_PHY037 (DDR_PHY_BASE + 0x094)
> +#define DDR_PHY038 (DDR_PHY_BASE + 0x098)
> +#define DDR_PHY039 (DDR_PHY_BASE + 0x09C)
> +
> +#define DDR_PHY040 (DDR_PHY_BASE + 0x0A0)
> +#define DDR_PHY041 (DDR_PHY_BASE + 0x0A4)
> +#define DDR_PHY042 (DDR_PHY_BASE + 0x0A8)
> +#define DDR_PHY043 (DDR_PHY_BASE + 0x0AC)
> +#define DDR_PHY044 (DDR_PHY_BASE + 0x0B0)
> +#define DDR_PHY045 (DDR_PHY_BASE + 0x0B4)
> +#define DDR_PHY046 (DDR_PHY_BASE + 0x0B8)
> +#define DDR_PHY047 (DDR_PHY_BASE + 0x0BC)
> +#define DDR_PHY048 (DDR_PHY_BASE + 0x0C0)
> +#define DDR_PHY049 (DDR_PHY_BASE + 0x0C4)
> +
> +#define DDR_PHY050 (DDR_PHY_BASE + 0x0C8)
> +#define DDR_PHY051 (DDR_PHY_BASE + 0x0CC)
> +#define DDR_PHY052 (DDR_PHY_BASE + 0x0D0)
> +#define DDR_PHY053 (DDR_PHY_BASE + 0x0D4)
> +#define DDR_PHY054 (DDR_PHY_BASE + 0x0D8)
> +#define DDR_PHY055 (DDR_PHY_BASE + 0x0DC)
> +#define DDR_PHY056 (DDR_PHY_BASE + 0x0E0)
> +#define DDR_PHY057 (DDR_PHY_BASE + 0x0E4)
> +#define DDR_PHY058 (DDR_PHY_BASE + 0x0E8)
> +#define DDR_PHY059 (DDR_PHY_BASE + 0x0EC)
> +
> +#define DDR_PHY060 (DDR_PHY_BASE + 0x0F0)
> +#define DDR_PHY061 (DDR_PHY_BASE + 0x0F4)
> +#define DDR_PHY062 (DDR_PHY_BASE + 0x0F8)
> +#define DDR_PHY063 (DDR_PHY_BASE + 0x0FC)
> +#define DDR_PHY064 (DDR_PHY_BASE + 0x100)
> +#define DDR_PHY065 (DDR_PHY_BASE + 0x104)
> +#define DDR_PHY066 (DDR_PHY_BASE + 0x108)
> +#define DDR_PHY067 (DDR_PHY_BASE + 0x10C)
> +#define DDR_PHY068 (DDR_PHY_BASE + 0x110)
> +
> +#endif /* __ASSEMBLER__*/
> +
> +#endif /* __ASM_ARCH_VYBRID_REGS_H__ */
> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
> index 37ac0da..bb7ebc2 100644
> --- a/arch/arm/include/asm/global_data.h
> +++ b/arch/arm/include/asm/global_data.h
> @@ -29,6 +29,9 @@ struct arch_global_data {
> #if defined(CONFIG_FSL_ESDHC)
> u32 sdhc_clk;
> #endif
> +#ifdef CONFIG_SYS_IPG
> + unsigned long ipg_clk;
> +#endif
> #ifdef CONFIG_AT91FAMILY
> /* "static data" needed by at91's clock.c */
> unsigned long cpu_clk_rate_hz;
> diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
> index a676b6d..31d67bf 100644
> --- a/arch/arm/include/asm/mach-types.h
> +++ b/arch/arm/include/asm/mach-types.h
> @@ -1107,6 +1107,10 @@ extern unsigned int __machine_arch_type;
> #define MACH_TYPE_OMAP5_SEVM 3777
> #define MACH_TYPE_ARMADILLO_800EVA 3863
> #define MACH_TYPE_KZM9G 4140
> +#define MACH_TYPE_VYBRID_VF7XX 4145
> +#define MACH_TYPE_VYBRID_VF6XX 4146
> +#define MACH_TYPE_VYBRID_VF5XX 4147
> +#define MACH_TYPE_VYBRID_VF4XX 4148
>
No, we drop this. Set instead CONFIG_MACH_TYPE in your board
configuration file.
Best regards,
Stefano Babic
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-13 20:32 ` Stefano Babic
@ 2013-04-28 10:36 ` Wang Huan-B18965
2013-04-28 10:59 ` Stefano Babic
0 siblings, 1 reply; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 10:36 UTC (permalink / raw)
To: u-boot
> On 12/04/2013 08:53, Alison Wang wrote:
> > The Vybrid devices are a family of Freescale's latest Dual Single
> > Core offering with ARM Cortex A5 and CM4 based processors for
> > Advanced Connected Radio, Entry Infotainment, and Cluster as well
> > as high end industrial and general purpose applications.
> >
> > This patch adds vybrid CPU support.
> >
>
> Hi Alison,
>
> first: I agree with Fabio's comments - I try to no repeat his comments
> here.
[Alison Wang] Thanks.
>
>
> > diff --git a/Makefile b/Makefile
> > index 12763ce..8a86951 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -334,6 +334,9 @@ LIBS-y += test/libtest.o
> > ifneq
> ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
> > LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
> > endif
> > +ifeq ($(SOC),vybrid)
> > +LIBS-y += $(CPUDIR)/vybrid-common/libvybrid-common.o
> > +endif
>
> I would like to understand there common code should be put. As you can
> see, for i.MX there is a imx_common directory that is valid across
> ARM-Core.
[Alison Wang] I'm trying to align the soc with i.mx platform and will use i.MX's imx_common directory in the next version. But there are still some issues for sharing the I.MX platform,
1. i.mx family uses GPT in timer.c. VF600 doesn't have GPT but a Periodic Interrupt Timer(PIT) which I think is totally different with GPT. Too much ifdef in the timer.c seems unacceptable. So I plan to modify the Makefile and add a pit.c file in imx_common directory for the timer on this Vybrid platform, How do you think about this idea? Thanks.
2. The SRC_SRSR register definition on VF600 is different with i.MX. To reuse the get_reset_cause() function in cpu.c, some platform related ifdef will be introduced.
For example:
#ifdef CONFIG_MVF600
case 0x00080:
return "EXTERNAL RESET";
#endif
Does this kind of ifdef acceptable? Thanks.
3. If sharing the cpu.c with I.MX, The cpu information printed will be "CPU: Freescale i.MX%s". As the Vybrid is not really the I.MX serials soc, I think the description should be Vybrid. Any suggestion for how to separate this in the cpu.c? Thanks a lot.
4. There are also some differences with the I.MX for the IOMUX. On the I.MX, there are separate registers for mux_mode and pin_ctrl, but on Vybrid, this two registers are merged into one 32bit register. I'm discussing this with Liu Hui on another mailchain. Any good suggestions? Thanks a lot.
I think after the main issues above got fixed, the Vybrid platform can be aligned with I.MX smoothly.
>
> >
> > ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
> > LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
> > @@ -467,6 +470,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> > $(obj)u-boot.imx: $(obj)u-boot.bin depend
> > $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-
> boot.imx
> >
> > +$(obj)u-boot.vybrid: $(obj)u-boot.bin
> > + $(obj)tools/mkimage -n $(CONFIG_VYBRID_CONFIG) -T imximage \
> > + -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
> > +
>
> I do not think we need a new rule only to have a new name. u-boot.imx
> had exactly the same rule here, but we decided in the past that some
> specific SOC rules should belong to the SOC (=CPU) directory without
> touching the main Makefile. The same rule you put here you can find into
> arch/arm/imx-common/Makefile. If the vybrid has nothing to do with
> imx_common, the rule to generate the image should go into the vybrid/
> directory.
[Alison Wang] I agree with you, this kind of issues will be fixed after the platform aligned with I.MX.
>
> > $(obj)u-boot.kwb: $(obj)u-boot.bin
> > $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
> > -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $<
> $@
> > @@ -855,6 +862,7 @@ clobber: tidy
> > @rm -f $(obj)u-boot.kwb
> > @rm -f $(obj)u-boot.pbl
> > @rm -f $(obj)u-boot.imx
> > + @rm -f $(obj)u-boot.vybrid
>
> Mainly I disagree to add a new name if we do not get a new image. The
> list you see contains different images, not different names. As far as I
> can see, u-boot.vybrid has the same structure and is built in the same
> way as u-boot.imx.
[Alison Wang] I agree with you, this kind of issues will be fixed after the platform aligned with I.MX.
>
> > new file mode 100644
> > index 0000000..bee8850
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
> > @@ -0,0 +1,46 @@
> > +#
> > +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> > +#
> > +# See file CREDITS for list of people who contributed to this
> > +# project.
> > +#
> > +# This program is free software; you can redistribute it and/or
> > +# modify it under the terms of the GNU General Public License as
> > +# published by the Free Software Foundation; either version 2 of
> > +# the License, or (at your option) any later version.
> > +#
> > +# This program is distributed in the hope that it will be useful,
> > +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > +# GNU General Public License for more details.
> > +#
> > +# You should have received a copy of the GNU General Public License
> > +# along with this program; if not, write to the Free Software
> > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > +# MA 02111-1307 USA
> > +#
> > +
> > +include $(TOPDIR)/config.mk
> > +
> > +LIB = $(obj)libvybrid-common.o
> > +
> > +COBJS := timer.o
> > +COBJS += cpu.o
> > +COBJS += speed.o
> > +
> > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> > +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
> > +
> > +all: $(obj).depend $(LIB)
> > +
> > +$(LIB): $(OBJS)
> > + $(call cmd_link_o_target, $(OBJS))
> > +
> >
> +########################################################################
> #
> > +
> > +# defines $(obj).depend target
> > +include $(SRCTREE)/rules.mk
> > +
> > +sinclude $(obj).depend
> > +
> >
> +########################################################################
> #
> > diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c
> b/arch/arm/cpu/armv7/vybrid-common/cpu.c
> > new file mode 100644
> > index 0000000..f99083e
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
> > @@ -0,0 +1,127 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <netdev.h>
> > +#include <asm/errno.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/sys_proto.h>
> > +
> > +#ifdef CONFIG_FSL_ESDHC
> > +#include <fsl_esdhc.h>
> > +#endif
> > +
> > +static char *get_reset_cause(void)
> > +{
> > + char *resetcause[32] = {"POR",
> > + "Cortex A5 WDOG Timer Reset",
> > + 0,
>
> I do not think it is a good idea to pad with dummy data only to output
> it later. I think it is better to use straightforward the same mechanism
> we have for all other SOC, that is:
>
> - add defines for each cause (WDOG/POR...), better check if we can reuse
> / factorize common values.
>
> - implement get_reset_cause() in the same way (check implementation for
> MX35 / MX5 / MX6..). It is much more readable.
[Alison Wang] I agree with you, this kind of issues will be fixed after the platform aligned with I.MX.
>
>
> > +#if defined(CONFIG_DISPLAY_CPUINFO)
> > +int print_cpuinfo(void)
> > +{
> > + u32 cpurev;
> > +
> > + cpurev = get_cpu_rev();
> > + printf("CPU: Freescale VyBrid %x family rev%d.%d at %d MHz\n",
> > + (cpurev & 0xFFF000) >> 12,
> > + (cpurev & 0x000F0) >> 4,
> > + (cpurev & 0x0000F) >> 0,
>
> Any chance to get defines for the masks you are using here ?
>
> > +int cpu_eth_init(bd_t *bis)
> > +{
> > + int rc = -ENODEV;
> > +
> > + rc = mcffec_initialize(bis);
>
> I admit I have mot checked deeply - but I have some limits due to the
> missing documentation. Is there some good reason we cannot adapt the
> well known FEC driver (we have a driver for all SOCs) to vybrid ?
[Alison Wang] We can adapt the well known FEC driver to vybrid. I will complete it in next version patches.
>
> > +
> > +void reset_cpu(ulong addr)
> > +{
> > + __raw_writew(4, WDOG_A5_BASE_ADDR);
> > +}
>
> I think this is the old implementation for i.MX - replaced by the
> function in imx_watchdog.c.
[Alison Wang] I agree with you, this kind of issues will be fixed after the platform aligned with I.MX.
>
> > diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c
> b/arch/arm/cpu/armv7/vybrid-common/timer.c
> > new file mode 100644
> > index 0000000..be990e6
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <div64.h>
> > +#include <asm/arch/timer.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define timestamp (gd->arch.tbl)
> > +#define timerticks (gd->arch.tbu)
> > +#define lastinc (gd->arch.lastinc)
> > +static unsigned long ltmstamp;
> > +
> > +#define CONFIG_TMR_USEPIT
> > +#ifdef CONFIG_TMR_USEPIT
> > +
> > +int timer_init(void)
> > +{
> > + ulong usecs;
> > + ulong ticks;
> > +
> > + timestamp = 0;
> > +
> > + /*
> > + * nsecs conversion = (1/ipg_clk) * 10^9
> > + * equivalent to 1000 / (ipg_clk / 10^6)
> > + */
> > + usecs = (vybrid_get_clock(VYBRID_IPG_CLK) / 1000000);
> > + ticks = 1000 / usecs;
> > +
> > + clrbits_le32(PIT_MCR, 2); /* enable PIT */
> > +
> > + /* ticks per 10 us = 10000 us / usecs = cycles time */
> > + timerticks = (10 * 1000) / ticks;
> > +
> > + __raw_writel(0xFFFFFFFF, PIT_LDVAL1);
> > + __raw_writel(0, PIT_TCTRL1);
> > + __raw_writel(4, PIT_TCTRL1);
> > + __raw_writel(5, PIT_TCTRL1);
> > + __raw_writel(timerticks, PIT_LDVAL0);
> > + __raw_writel(1, PIT_TCTRL0);
>
> General remark: do not use offset to write into register. Instead of
> that, defines a C structure and access to the structure to set / read
> registers. See othe i.MX implementations.
[Alison Wang] Agree, I will rewrite such codes.
>
> > +ulong get_timer(ulong base)
> > +{
> > + unsigned long now, diff;
> > +
> > + now = __raw_readl(PIT_LTMR64H);
> > + diff = -(now - lastinc);
> > + ltmstamp += diff;
> > + while (ltmstamp > 100) {
> > + timestamp++;
> > + ltmstamp -= 100;
> > + }
> > + lastinc = now;
> > +
> > + return timestamp - base;
> > +}
>
> I am sure this can be better factorited - we had this kind of code some
> times ago. We have quite the same structure for all SOCs, not only
> Freescale's. Check for example the implementation in imx_common/timer.c
[Alison Wang] Agree, I will rewrite this file according to your suggestions. Thanks.
>
> > +
> > +/* delay x useconds AND preserve advance timstamp value */
> > +void __udelay(unsigned long usec)
> > +{
> > + ulong nsecs, tmp;
> > +
> > + /*
> > + * nsecs conversion = (1/ipg_clk) * 10^9
> > + * equivalent to 1000 / (ipg_clk / 10^6)
> > + */
> > + if (usec < 5)
> > + usec = 10;
> > +
> > + nsecs = gd->arch.ipg_clk / 1000000;
> > + nsecs = 1000 / nsecs;
> > +
> > + /* 1 us per ticks = 1000 ns / nsecs = cycles time */
> > + while (usec > 0) {
> > + if (usec > 65000)
> > + tmp = 65000;
>
> I admit I have the value not understood. But again, if we have a
> get_ticks() and us_to_ticks() for the SOC, udelay is standard and we
> have the hope to better factorize it in future.
>
> > + * This function is derived from PowerPC code (timebase clock
> frequency).
> > + * On ARM it returns the number of timer ticks per second.
> > + */
> > +unsigned long long _usec2ticks(unsigned long long usec)
> > +{
> > + return usec;
> > +}
>
> Obsolete, I think, we use us_to_tick()
>
>
>
> > +
> > +struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> > +
> > +/* Get mcu main rate */
> > +static u32 get_mcu_main_clk(void)
> > +{
> > + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> > + u32 ccm_ccsr, ccm_cacrr, armclk_div;
> > + u32 sysclk_sel, pll_pfd_sel = 0;
> > + u32 freq = 0;
> > +
> > + ccm_ccsr = readl(&ccm->ccsr);
> > + sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
> > + sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
> > +
> > + ccm_cacrr = readl(&ccm->cacrr);
> > + armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
> > + armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
> > + armclk_div += 1;
>
> I see a lot of analogies with i.MX6 code.
[Alison Wang] The name of the registers are the same, such as ccm_caccr, ccm_ccsr. But the definitions of the registers are different between vybrid and i.mx6 platforms.
>
> > +
> > + switch (sysclk_sel) {
> > + case 0:
> > + freq = FASE_CLK_FREQ;
> > + break;
> > + case 1:
> > + freq = SLOW_CLK_FREQ;
> > + break;
> > + case 3:
> > + freq = PLL2_MAIN_FREQ;
> > + break;
> > + case 5:
> > + freq = PLL3_MAIN_FREQ;
> > + break;
> > + case 2:
> > + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
> > + pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
> > + break;
> > + case 4:
> > + pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
> > + pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
> > + break;
> > + default:
> > + printf("unsupported system clock select\n");
> > + }
> > +
> > + if (sysclk_sel == 2) {
>
> Code is quite confused. Why do you use a switch and after that you check
> again for cases that are covered by the switch itself ?
[Alison Wang] I will modify this confused code in the next version patches.
>
>
> > +
> > +/* Get the rate of bus clock */
> > +static u32 get_bus_clk(void)
> > +{
> > + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> > + u32 ccm_cacrr, busclk_div;
> > +
> > + ccm_cacrr = readl(&ccm->cacrr);
> > +
> > + busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
> > + busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
> > + busclk_div += 1;
> > +
> > + return get_mcu_main_clk() / busclk_div;
> > +}
> > +
> > +/* Get the rate of ipg clock */
> > +static u32 get_ipg_clk(void)
> > +{
> > + struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
> > + u32 ccm_cacrr, ipgclk_div;
> > +
> > + ccm_cacrr = readl(&ccm->cacrr);
> > +
> > + ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
> > + ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
> > + ipgclk_div += 1;
> > +
> > + return get_bus_clk() / ipgclk_div;
> > +}
> > +
> > +/* get dspi clock rate */
> > +static u32 vybrid_get_dspiclk(void)
> > +{
> > + return get_ipg_clk();
> > +}
> > +
> > +/* The API of get vybrid clocks */
> > +unsigned int vybrid_get_clock(enum vybrid_clock clk)
> > +{
> > + switch (clk) {
> > + case VYBRID_ARM_CLK:
> > + return get_mcu_main_clk();
> > + case VYBRID_BUS_CLK:
> > + return get_bus_clk();
> > + case VYBRID_IPG_CLK:
> > + return get_ipg_clk();
> > + case VYBRID_UART_CLK:
> > + return vybrid_get_uartclk();
> > + case VYBRID_DSPI_CLK:
> > + return vybrid_get_dspiclk();
>
> Can you explain which peripheral is this ? Has vybrid a DSP inside ?
>
> > +/* Get the rate of uart clk */
> > +u32 vybrid_get_uartclk(void)
> > +{
> > + return get_ipg_clk();
> > +}
>
> Why do we need if we can use vybrid_get_clock(VYBRID_UART_CLK) ?
[Alison Wang] Agree.
>
> > diff --git a/arch/arm/cpu/armv7/vybrid/iomux.c
> b/arch/arm/cpu/armv7/vybrid/iomux.c
> > new file mode 100644
> > index 0000000..fb672e3
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/vybrid/iomux.c
> > @@ -0,0 +1,42 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/vybrid-pins.h>
> > +#include <asm/arch/iomux.h>
> > +#include <asm/arch/sys_proto.h>
> > +
> > +void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio)
> > +{
> > + u32 value;
> > +
> > + value = (((padio->mod & 7) << 20) | ((padio->spd & 3) << 12) | \
> > + ((padio->sre & 1) << 11) | ((padio->ode & 1) << 10) | \
> > + ((padio->hys & 1) << 9) | ((padio->dse & 7) << 6) | \
> > + ((padio->pus & 3) << 4) | ((padio->pke & 1) << 3) | \
> > + ((padio->pue & 1) << 2) | ((padio->obe & 1) << 1) | \
> > + ((padio->ibe & 1) << 0));
> > +
> > + __raw_writel(pad_addr, value);
>
> Add defines for the magic number you introduce here.
[Alison Wang] I agree with you, this kind of issues will be fixed after the platform aligned with I.MX.
>
> > diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> > new file mode 100644
> > index 0000000..c2bda4f
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> > @@ -0,0 +1,128 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <config.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <generated/asm-offsets.h>
> > +
> > +/* DDR */
> > +.macro init_drive_strength
> > +.endm /* init_drive_strength */
> > +
> > +.macro setup_pll pll, freq
> > +.endm
> > +
> > +.macro init_clock
> > + ldr r0, =CCM_BASE_ADDR
> > +
> > + ldr r1, =CONFIG_SYS_CLKCTRL_CLPCR
> > + str r1, [r0, #CLKCTL_CLPCR]
> > +
> > + /* Gate of clocks to the peripherals first */
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR0
> > + str r1, [r0, #CLKCTL_CCGR0]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR1
> > + str r1, [r0, #CLKCTL_CCGR1]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR2
> > + str r1, [r0, #CLKCTL_CCGR2]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR3
> > + str r1, [r0, #CLKCTL_CCGR3]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR4
> > + str r1, [r0, #CLKCTL_CCGR4]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR5
> > + str r1, [r0, #CLKCTL_CCGR5]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR6
> > + str r1, [r0, #CLKCTL_CCGR6]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR7
> > + str r1, [r0, #CLKCTL_CCGR7]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR8
> > + str r1, [r0, #CLKCTL_CCGR8]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR9
> > + str r1, [r0, #CLKCTL_CCGR9]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR10
> > + str r1, [r0, #CLKCTL_CCGR10]
> > + ldr r1, =CONFIG_SYS_CLKCTL_CCGR11
> > + str r1, [r0, #CLKCTL_CCGR11]
> > +
>
> Why cannot we do this in C code ? You introduce a lot of
> CONFIS_SYS_CLKCTL_ in the board configuration file. This can be done in
> board code, for example in board_early_init_f(), without constrain all
> boards to set all of this stuff, but only what is required.
[Alison Wang] Agree. I will move these configurations into board_early_init_f() in the next version patches.
>
> > +.section ".text.init", "x"
> > +
> > +.globl lowlevel_init
> > +lowlevel_init:
> > + /* ARM errata ID #468414 */
> > + mrc 15, 0, r1, c1, c0, 1
> > + orr r1, r1, #(1 << 5) /* enable L1NEON bit */
> > + mcr 15, 0, r1, c1, c0, 1
> > +
> > +#ifndef CONFIG_SYS_BOOTHDR
>
> This is not currently defined anyware. If you want to add CONFIG_SYS_
> defines, you should also add the documentation explainig which are the
> goals in the README.
>
> > +/* Board level setting value */
> > +DDR_PERCHARGE_CMD: .word 0x04008008
> > +DDR_REFRESH_CMD: .word 0x00008010
> > +DDR_LMR1_W: .word 0x00338018
> > +DDR_LMR_CMD: .word 0xB2220000
> > +DDR_TIMING_W: .word 0xB02567A9
> > +DDR_MISC_W: .word 0x000A0104
>
> They are defined, but not used. Please do not add dead code.
[Alison Wang] Agree.
>
> > +#include <common.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/clock.h>
> > +#include <asm/arch/sys_proto.h>
> > +
> > +#include <asm/errno.h>
> > +#include <asm/io.h>
> > +
> > +#if !(defined(CONFIG_VYBRID))
> > +#error "CPU_TYPE not defined"
> > +#endif
> > +
> > +u32 get_cpu_rev(void)
> > +{
> > + int system_rev = 0x600000;
>
> Which is the meaning of this value ? It is not read from hardware
[Alison Wang] I will check the RM.
>
> > diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h
> b/arch/arm/include/asm/arch-vybrid/iomux.h
> > new file mode 100644
> > index 0000000..94f8b0b
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-vybrid/iomux.h
> > @@ -0,0 +1,323 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __MACH_VYBRID_IOMUX_H__
> > +#define __MACH_VYBRID_IOMUX_H__
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/vybrid-pins.h>
> > +
> > +#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000)
> > +#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004)
> > +#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008)
> > +#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C)
> > +#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010)
> > +#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014)
> > +#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018)
> > +#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C)
> > +#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020)
> > +#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024)
> > +#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028)
> > +#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C)
> > +#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030)
> > +#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034)
> > +#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038)
> > +#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C)
>
> There is not a lot of information defining IOMUXC_PAD_NUMBER with an
> offset. If you see for other SOCs, the values correspond to a specific
> function.
>
> > +#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C)
> > +#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220)
> > +#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224)
> > +#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228)
> > +#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C)
> > +#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230)
> > +#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234)
> > +#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238)
> > +#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C)
> > +#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240)
> > +#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244)
> > +#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248)
> > +#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C)
> > +#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250)
> > +#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254)
> > +#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258)
> > +#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C)
> > +
> > +#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260)
> > +#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264)
> > +#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268)
> > +
> > +#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C)
> > +
> > +#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270)
> > +
> > +#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274)
> > +
> > +#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278)
> > +
> > +#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C)
> > +#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280)
> > +#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284)
> > +#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288)
> > +#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C)
> > +#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290)
> > +#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294)
> > +#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298)
> > +#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C)
> > +#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0)
> > +#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4)
> > +#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8)
> > +#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC)
> > +#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0)
> > +#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4)
> > +#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8)
> > +
> > +#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC)
> > +#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0)
> > +
> > +#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4)
> > +#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8)
> > +
> > +#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC)
> > +#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0)
> > +
> > +#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4)
> > +#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8)
> > +
> > +#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC)
> > +#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0)
> > +
> > +#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4)
> > +#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8)
> > +
> > +#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC)
> > +#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0)
> > +#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4)
> > +
> > +struct pad_iomux {
> > + u8 mod;
> > + u8 spd;
> > + u8 sre;
> > + u8 ode;
> > + u8 hys;
> > + u8 dse;
> > + u8 pus;
> > + u8 pke;
> > + u8 pue;
> > + u8 obe;
> > + u8 ibe;
> > +};
>
> Add some comments, the fields are not so self explaining
>
> > +
> > +#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, \
> > + dse, pus, pke, pue, obe, ibe) \
> > + (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \
> > + ((sre & 1) << 11) | ((ode & 1) << 10) | \
> > + ((hys & 1) << 9) | ((dse & 7) << 6) | \
> > + ((pus & 3) << 4) | ((pke & 1) << 3) | \
> > + ((pue & 1) << 2) | ((obe & 1) << 1) | \
> > + (ibe & 1)))
> > +
> > +#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \
> > + (((inp & 1) << 16) | ((trim & 3) << 14) | \
> > + ((hys & 1) << 9) | ((dse & 7) << 6) | \
> > + ((pus & 3) << 4) | ((pke & 1) << 3) | \
> > + ((pue & 1) << 2))
> > +
> > +#define MUX_MODE_ALT0 0x00
> > +#define MUX_MODE_ALT1 0x01
> > +#define MUX_MODE_ALT2 0x02
> > +#define MUX_MODE_ALT3 0x03
> > +#define MUX_MODE_ALT4 0x04
> > +#define MUX_MODE_ALT5 0x05
> > +#define MUX_MODE_ALT6 0x06
> > +#define MUX_MODE_ALT7 0x07
> > +
> > +#define MUX_SPD_50MHZ 0x00
> > +#define MUX_SPD_100MHZ 0x02
> > +#define MUX_SPD_200MHZ 0x03
> > +
> > +#define MUX_SRE_SLOW 0
> > +#define MUX_SRE_FAST 1
> > +
> > +#define MUX_ODE_CMOS 0
> > +#define MUX_ODE_OPEN 1
> > +
> > +#define MUX_HYS_CMOS 0
> > +#define MUX_HYS_SCHMITT 1
> > +
> > +#define MUX_DSE_20_OHM 7
> > +#define MUX_DSE_25_OHM 6
> > +#define MUX_DSE_30_OHM 5
> > +#define MUX_DSE_37_OHM 4
> > +#define MUX_DSE_50_OHM 3
> > +#define MUX_DSE_75_OHM 2
> > +#define MUX_DSE_150_OHM 1
> > +#define MUX_DSE_DIS 0
> > +
> > +#define MUX_PUS_22KOHM_UP 3
> > +#define MUX_PUS_100KOHM_UP 2
> > +#define MUX_PUS_47KOHM_UP 1
> > +#define MUX_PUS_100KOHM_DN 0
> > +
> > +#define MUX_PKE_EN 1
> > +#define MUX_PKE_DIS 0
> > +
> > +#define MUX_PUE_PULLEN 1
> > +#define MUX_PUE_KEEPEREN 0
> > +
> > +#define MUX_OBE_EN 1
> > +#define MUX_OBE_DIS 0
> > +
> > +#define MUX_IBE_EN 1
> > +#define MUX_IBE_DIS 0
> > +
> > +#define MUX_DDR_INPUT_DIFF 1
> > +#define MUX_DDR_INPUT_CMOS 0
> > +
> > +#define MUX_DDR_TRIM_150PS 3
> > +#define MUX_DDR_TRIM_100PS 2
> > +#define MUX_DDR_TRIM_50PS 1
> > +#define MUX_DDR_TRIM_MIN 0
> > +
> > +void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio);
> > +
> > +#endif /* __MACH_VYBRID_IOMUX_H__ */
> > diff --git a/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> > new file mode 100644
> > index 0000000..9575f73
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> > @@ -0,0 +1,213 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __SERIAL_VYBRID_H__
> > +#define __SERIAL_VYBRID_H__
> > +
> > +#define UBDH 0x00
> > +#define UBDL 0x01
> > +#define UC1 0x02
> > +#define UC2 0x03
> > +#define US1 0x04
> > +#define US2 0x05
> > +#define UC3 0x06
> > +#define UD 0x07
> > +#define UMA1 0x08
> > +#define UMA2 0x09
> > +#define UC4 0x0A
> > +#define UC5 0x0B
> > +#define UED 0x0C
>
> These are offset - please replace with C structures, thanks.
[Alison Wang] Agree. Thanks.
>
> > +#define UMODEM 0x0D
> > +#define UIR 0x0E
> > +#define UPFIFO 0x10
> > +#define UCFIFO 0x11
> > +#define USFIFO 0x12
> > +#define UTWFIFO 0x13
> > +#define UTCFIFO 0x14
> > +#define URWFIFO 0x15
> > +#define URCFIFO 0x16
> > +#define UC7816 0x18
> > +#define UIE7816 0x19
> > +#define UIS7816 0x1A
> > +#define UWP7816T0 0x1B
> > +#define UWP7816T1 0x1B
> > +#define UWN7816 0x1C
> > +#define UWF7816 0x1D
> > +#define UET78416 0x1E
> > +#define UTL7816 0x1F
> > +#define UC6 0x21
> > +#define UPCTH 0x22
> > +#define UPCTL 0x23
> > +#define UB1T 0x24
> > +#define USDTH 0x25
> > +#define USDTL 0x26
> > +#define UPRE 0x27
> > +#define UTPL 0x28
> > +#define UIE 0x29
> > +#define UWB 0x2A
> > +#define US3 0x2B
> > +#define US4 0x2C
> > +#define UPRL 0x2D
> > +#define URPREL 0x2E
> > +#define UCPW 0x2F
> > +#define URIDT 0x30
> > +#define UTIDT 0x31
> > +
> > +#define UBDH_LBKDIE (1 << 7)
> > +#define UBDH_RXEDGIE (1 << 6)
> > +#define UBDH_SBR(x) (x & 0x1F)
> > +
> > +#define UC1_LOOPS (1 << 7)
> > +#define UC1_SWAI (1 << 6)
> > +#define UC1_RSRC (1 << 5)
> > +#define UC1_M (1 << 4)
> > +#define UC1_WAKE (1 << 3)
> > +#define UC1_ILT (1 << 2)
> > +#define UC1_PE (1 << 1)
> > +#define UC1_PT (1 << 0)
> > +
> > +#define UC2_TIE (1 << 7)
> > +#define UC2_TCIE (1 << 6)
> > +#define UC2_RIE (1 << 5)
> > +#define UC2_ILIE (1 << 4)
> > +#define UC2_TE (1 << 3)
> > +#define UC2_RE (1 << 2)
> > +#define UC2_RWU (1 << 1)
> > +#define UC2_SBK (1 << 0)
> > +
> > +#define US1_TDRE (1 << 7)
> > +#define US1_TC (1 << 6)
> > +#define US1_RDRF (1 << 5)
> > +#define US1_IDLE (1 << 4)
> > +#define US1_OR (1 << 3)
> > +#define US1_NF (1 << 2)
> > +#define US1_FE (1 << 1)
> > +#define US1_PF (1 << 0)
> > +
> > +#define US2_LBKDIF (1 << 7)
> > +#define US2_RXEDGIF (1 << 6)
> > +#define US2_MSBF (1 << 5)
> > +#define US2_RXINV (1 << 4)
> > +#define US2_RWUID (1 << 3)
> > +#define US2_BRK13 (1 << 2)
> > +#define US2_RBKDE (1 << 1)
> > +#define US2_RAF (1 << 0)
> > +
> > +#define UC3_R8 (1 << 7)
> > +#define UC3_T8 (1 << 6)
> > +#define UC3_TXDIR (1 << 5)
> > +#define UC3_TXINV (1 << 4)
> > +#define UC3_ORIE (1 << 3)
> > +#define UC3_NEIF (1 << 2)
> > +#define UC3_FEIF (1 << 1)
> > +#define UC3_PEIE (1 << 0)
> > +
> > +#define UC4_MAEN1 (1 << 7)
> > +#define UC4_MAEN2 (1 << 6)
> > +#define UC4_M10 (1 << 5)
> > +#define UC4_BRFA(x) (x & 0x1F)
> > +
> > +#define UC5_TDMAS (1 << 7)
> > +#define UC5_RDMAS (1 << 5)
> > +
> > +#define UED_NOISY (1 << 7)
> > +#define UED_PARITYE (1 << 6)
> > +
> > +#define UMODEM_RXRTSE (1 << 3)
> > +#define UMODEM_TXRTSPOL (1 << 2)
> > +#define UMODEM_TXRTSE (1 << 1)
> > +#define UMODEM_TXCTSE (1 << 0)
> > +
> > +#define UIR_IREN (1 << 2)
> > +#define UIR_TNP(x) (x & 3)
> > +
> > +#define UPFIFO_TXFE (1 << 7)
> > +#define UPFIFO_TXFSZ(x) ((x & 7) << 4)
> > +#define UPFIFO_RXFE (1 << 3)
> > +#define UPFIFO_RXFSZ(x) ((x & 7) << 0)
> > +
> > +#define UCFIFO_TXFLUSH (1 << 7)
> > +#define UCFIFO_RXFLUSH (1 << 6)
> > +#define UCFIFO_TXOFE (1 << 1)
> > +#define UCFIFO_RXUFE (1 << 0)
> > +
> > +#define USFIFO_TXEMPT (1 << 7)
> > +#define USFIFO_RXEMPT (1 << 6)
> > +#define USFIFO_TXOF (1 << 1)
> > +#define USFIFO_RXUF (1 << 0)
> > +
> > +#define UC7816_ONACK (1 << 4)
> > +#define UC7816_ANACK (1 << 3)
> > +#define UC7816_INIT (1 << 2)
> > +#define UC7816_TTYPE (1 << 1)
> > +#define UC7816_7816E (1 << 0)
> > +
> > +#define UIE7816_WTE (1 << 7)
> > +#define UIE7816_CWTE (1 << 6)
> > +#define UIE7816_BWTE (1 << 5)
> > +#define UIE7816_INITDE (1 << 4)
> > +#define UIE7816_GTVE (1 << 2)
> > +#define UIE7816_TXTE (1 << 1)
> > +#define UIE7816_RXTE (1 << 0)
> > +
> > +#define UIS7816_WTE (1 << 7)
> > +#define UIS7816_CWTE (1 << 6)
> > +#define UIS7816_BWTE (1 << 5)
> > +#define UIS7816_INITDE (1 << 4)
> > +#define UIS7816_GTVE (1 << 2)
> > +#define UIS7816_TXTE (1 << 1)
> > +#define UIS7816_RXTE (1 << 0)
> > +
> > +#define UWP7816T1_CWI(x) ((x & 0xf) << 4)
> > +#define UWP7816T1_BWI(x) ((x & 0xf) << 0)
> > +
> > +#define UET78416_TXTHRESHOLD(x) ((x & 0xf) << 4)
> > +#define UET78416_RXTHRESHOLD(x) ((x & 0xf) << 0)
> > +
> > +#define UC6_EN709 (1 << 7)
> > +#define UC6_TX709 (1 << 6)
> > +#define UC6_CE (1 << 5)
> > +#define UC6_CP (1 << 4)
> > +
> > +#define UIE_WBEIE (1 << 6)
> > +#define UIE_ISDIE (1 << 5)
> > +#define UIE_PRXIE (1 << 4)
> > +#define UIE_PTXIE (1 << 3)
> > +#define UIE_PCTEIE (1 << 2)
> > +#define UIE_PSIE (1 << 1)
> > +#define UIE_TXFIE (1 << 0)
> > +
> > +#define US3_PEF (1 << 7)
> > +#define US3_WBEF (1 << 6)
> > +#define US3_ISD (1 << 5)
> > +#define US3_PRXF (1 << 4)
> > +#define US3_PTXF (1 << 3)
> > +#define US3_PCTEF (1 << 2)
> > +#define US3_PSF (1 << 1)
> > +#define US3_TXFF (1 << 0)
> > +
> > +#define US4_INITF (1 << 4)
> > +#define US4_CDET(x) ((x & 3) << 2)
> > +#define US4_ILCV (1 << 1)
> > +#define US4_FE (1 << 0)
> > +
> > +#endif /* __SERIAL_VYBRID_H__ */
> > diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h
> b/arch/arm/include/asm/arch-vybrid/sys_proto.h
> > new file mode 100644
> > index 0000000..7e2de97
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h
> > @@ -0,0 +1,30 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef _SYS_PROTO_H_
> > +#define _SYS_PROTO_H_
> > +
> > +u32 get_cpu_rev(void);
> > +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
> > +void sdelay(unsigned long);
>
> We get rid of sdelay() and we use udelay() when it is possible. I do not
> know if this is the case.
[Alison Wang] Agree.
>
> > diff --git a/arch/arm/include/asm/arch-vybrid/timer.h
> b/arch/arm/include/asm/arch-vybrid/timer.h
> > new file mode 100644
> > index 0000000..55497e3
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-vybrid/timer.h
> > @@ -0,0 +1,405 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __ASM_ARCH_TIMER_H
> > +#define __ASM_ARCH_TIMER_H
> > +
> > +struct ftm_regs {
> > + u32 sc; /* 0x00 */
> > + u32 cnt; /* 0x04 */
> > + u32 mod; /* 0x08 */
> > + u32 c0sc; /* 0x0C */
> > + u32 c0v; /* 0x10 */
> > + u32 c1sc; /* 0x14 */
> > + u32 c1v; /* 0x18 */
> > + u32 c2sc; /* 0x1C */
> > + u32 c2v; /* 0x20 */
> > + u32 c3sc; /* 0x24 */
> > + u32 c3v; /* 0x28 */
> > + u32 c4sc; /* 0x2C */
> > + u32 c4v; /* 0x30 */
> > + u32 c5sc; /* 0x34 */
> > + u32 c5v; /* 0x38 */
> > + u32 c6sc; /* 0x3C */
> > + u32 c6v; /* 0x40 */
> > + u32 c7sc; /* 0x44 */
> > + u32 c7v; /* 0x48 */
> > + u32 cntin; /* 0x4C */
> > + u32 status; /* 0x50 */
> > + u32 mode; /* 0x54 */
> > + u32 sync; /* 0x58 */
> > + u32 outinit; /* 0x5C */
> > + u32 outmask; /* 0x60 */
> > + u32 combine; /* 0x64 */
> > + u32 deadtime; /* 0x68 */
> > + u32 exttrig; /* 0x6C */
> > + u32 pol; /* 0x70 */
> > + u32 fms; /* 0x74 */
> > + u32 filter; /* 0x78 */
> > + u32 fltctrl; /* 0x7C */
> > + u32 qdctrl; /* 0x80 */
> > + u32 conf; /* 0x84 */
> > + u32 fltpol; /* 0x88 */
> > + u32 synconf; /* 0x8C */
> > + u32 invctrl; /* 0x90 */
> > + u32 swoctrl; /* 0x94 */
> > + u32 pwmload; /* 0x98 */
> > +};
> > +
> > +struct pit2_regs {
> > + u32 ldval; /* 0x00 */
> > + u32 cval; /* 0x04 */
> > + u32 tctrl; /* 0x08 */
> > + u32 tflg; /* 0x0C */
> > +};
> > +
> > +struct pit_regs {
> > + u32 mcr; /* 0x00 */
> > + u32 rsvd0[55];
> > + u32 ltmr64h; /* 0xE0 */
> > + u32 ltmr64l; /* 0xE4 */
> > + u32 rsvd1[6];
> > + struct pit2_regs counter[8]; /* 0x100 */
> > +};
> > +
> > +struct lptmr_regs {
> > + u32 csr; /* 0x00 */
> > + u32 psr; /* 0x04 */
> > + u32 cmr; /* 0x08 */
> > + u32 cnr; /* 0x0C */
> > +};
>
> Comments with offset are not very useful, drop them.
[Alison Wang] Agree.
>
> > diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> > new file mode 100644
> > index 0000000..225a1e1
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> > @@ -0,0 +1,88 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __ASM_ARCH_VYBRID_PINS_H__
> > +#define __ASM_ARCH_VYBRID_PINS_H__
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +/*!
> > + * Starting bit position within each entry of \b iomux_pins to
> represent the
> > + * MUX control register offset
> > + */
> > +#define MUX_I 0
>
> You use inconsistently doxygen comments. As I remember, there is no
> decision to use it in the project, so please remove the meta chars.
[Alison Wang] Agree.
>
>
> > +/*!
> > + * Starting bit position within each entry of \b iomux_pins to
> represent the
> > + * PAD control register offset
> > + */
> > +#define PAD_I 10
> > +/*!
> > + * Starting bit position within each entry of \b iomux_pins to
> represent which
> > + * mux mode is for GPIO (0-based)
> > + */
> > +#define GPIO_I 21
> > +
> > +#define MUX_IO_P 29
> > +#define MUX_IO_I 24
> > +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
> > + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
> > + ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
> > +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE +
> IOMUX_TO_GPIO(pin))
> > +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
> > +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
>
> I prefer you use the same convention we have for other Freescale's SOC,
> that is PORT starts from 1 and not from zero. Check if you can use the
> macros already set for MX% / MX6.
[Alison Wang] Agree.
>
> > +#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
> > +#define AIPS0_BASE_ADDR 0x40000000
> > +#define AIPS1_BASE_ADDR 0x40080000
> > +#define CSD0_BASE_ADDR 0x80000000 /* ddr 0 */
> > +#define CSD1_BASE_ADDR 0xa0000000 /* ddr 1 */
> > +
> > +#define IRAM_SIZE 0x00040000 /* 256 KB */
> > +
> > +/* AIPS 0 */
> > +#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
> > +#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
> > +#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
> > +#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
> > +#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
> > +#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
> > +#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
> > +#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
> > +#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
> > +#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
> > +#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
> > +#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
> > +#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
> > +#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
> > +#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
> > +#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
> > +#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
> > +#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
> > +#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
> > +#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
> > +#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
> > +#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
> > +#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
> > +#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
> > +#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
> > +#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
> > +#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
> > +#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
> > +#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
> > +#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
> > +#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
> > +#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
> > +#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
> > +#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
> > +#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
> > +#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
> > +#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
> > +#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
> > +#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
> > +#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
> > +#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
> > +#define WDOG_A5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
> > +#define WDOG_M4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
> > +#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
> > +#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
> > +#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
> > +#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
> > +#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
> > +#define ANATOP_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
> > +#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
> > +#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
> > +#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
> > +#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
> > +#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
> > +#define EWDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
> > +#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
> > +#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
> > +#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
> > +#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
> > +#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
> > +#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
> > +#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
> > +
> > +/* AIPS 1 */
> > +#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
> > +#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
> > +#define ESDHC2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
> > +#define QSPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
> > +#define MACNET0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
> > +#define MACNET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
> > +
> > +/* WEIM CSnGCR1 */
> > +#define CSEN 1
> > +#define SWR (1 << 1)
> > +#define SRD (1 << 2)
> > +#define MUM (1 << 3)
> > +#define WFL (1 << 4)
> > +#define RFL (1 << 5)
> > +#define CRE (1 << 6)
> > +#define CREP (1 << 7)
> > +#define BL(x) (((x) & 0x7) << 8)
> > +#define WC (1 << 11)
> > +#define BCD(x) (((x) & 0x3) << 12)
> > +#define BCS(x) (((x) & 0x3) << 14)
> > +#define DSZ(x) (((x) & 0x7) << 16)
> > +#define SP (1 << 19)
> > +#define CSREC(x) (((x) & 0x7) << 20)
> > +#define AUS (1 << 23)
> > +#define GBC(x) (((x) & 0x7) << 24)
> > +#define WP (1 << 27)
> > +#define PSZ(x) (((x) & 0x0f << 28)
> > +
> > +/* WEIM CSnGCR2 */
> > +#define ADH(x) (((x) & 0x3))
> > +#define DAPS(x) (((x) & 0x0f << 4)
> > +#define DAE (1 << 8)
> > +#define DAP (1 << 9)
> > +#define MUX16_BYP (1 << 12)
> > +
> > +/* WEIM CSnRCR1 */
> > +#define RCSN(x) (((x) & 0x7))
> > +#define RCSA(x) (((x) & 0x7) << 4)
> > +#define OEN(x) (((x) & 0x7) << 8)
> > +#define OEA(x) (((x) & 0x7) << 12)
> > +#define RADVN(x) (((x) & 0x7) << 16)
> > +#define RAL (1 << 19)
> > +#define RADVA(x) (((x) & 0x7) << 20)
> > +#define RWSC(x) (((x) & 0x3f) << 24)
> > +
> > +/* WEIM CSnRCR2 */
> > +#define RBEN(x) (((x) & 0x7))
> > +#define RBE (1 << 3)
> > +#define RBEA(x) (((x) & 0x7) << 4)
> > +#define RL(x) (((x) & 0x3) << 8)
> > +#define PAT(x) (((x) & 0x7) << 12)
> > +#define APR (1 << 15)
> > +
> > +/* WEIM CSnWCR1 */
> > +#define WCSN(x) (((x) & 0x7))
> > +#define WCSA(x) (((x) & 0x7) << 3)
> > +#define WEN(x) (((x) & 0x7) << 6)
> > +#define WEA(x) (((x) & 0x7) << 9)
> > +#define WBEN(x) (((x) & 0x7) << 12)
> > +#define WBEA(x) (((x) & 0x7) << 15)
> > +#define WADVN(x) (((x) & 0x7) << 18)
> > +#define WADVA(x) (((x) & 0x7) << 21)
> > +#define WWSC(x) (((x) & 0x3f) << 24)
> > +#define WBED1 (1 << 30)
> > +#define WAL (1 << 31)
> > +
> > +/* WEIM CSnWCR2 */
> > +#define WBED 1
> > +
> > +/* WEIM WCR */
> > +#define BCM 1
> > +#define GBCD(x) (((x) & 0x3) << 1)
> > +#define INTEN (1 << 4)
> > +#define INTPOL (1 << 5)
> > +#define WDOG_EN (1 << 8)
> > +#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
> > +
> > +/* Number of GPIO pins per port */
> > +#define GPIO_NUM_PIN 32
> > +
> > +#define IIM_SREV 0x24
> > +#define ROM_SI_REV 0x80
> > +
> > +#define NFC_BUF_SIZE 0x1000
> > +
> > +#define CHIP_REV_1_0 0x10
> > +#define CHIP_REV_1_1 0x11
> > +#define CHIP_REV_2_0 0x20
> > +#define CHIP_REV_2_5 0x25
> > +#define CHIP_REV_3_0 0x30
> > +
> > +#define BOARD_REV_1_0 0x0
> > +#define BOARD_REV_2_0 0x1
> > +
> > +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
> > +#include <asm/types.h>
> > +
> > +struct clkctl {
> > + u32 ccr; /* 0x00 */
> > + u32 csr; /* 0x04 */
> > + u32 ccsr; /* 0x08 */
> > + u32 cacrr; /* 0x0C */
> > + u32 cscmr1; /* 0x10 */
> > + u32 cscdr1; /* 0x14 */
> > + u32 cscdr2; /* 0x18 */
> > + u32 cscdr3; /* 0x1C */
> > + u32 cscmr2; /* 0x20 */
> > + u32 cscdr4; /* 0x24 */
> > + u32 ctor; /* 0x28 */
> > + u32 clpcr; /* 0x2C */
> > + u32 cisr; /* 0x30 */
> > + u32 cimr; /* 0x34 */
> > + u32 ccosr; /* 0x38 */
> > + u32 cgpr; /* 0x3C */
> > + u32 ccgr0; /* 0x40 */
> > + u32 ccgr1; /* 0x44 */
> > + u32 ccgr2; /* 0x48 */
> > + u32 ccgr3; /* 0x4C */
> > + u32 ccgr4; /* 0x50 */
> > + u32 ccgr5; /* 0x54 */
> > + u32 ccgr6; /* 0x58 */
> > + u32 ccgr7; /* 0x5C */
> > + u32 ccgr8; /* 0x60 */
> > + u32 ccgr9; /* 0x64 */
> > + u32 ccgr10; /* 0x68 */
> > + u32 ccgr11; /* 0x6C */
> > + u32 cmeor0; /* 0x70 */
> > + u32 cmeor1; /* 0x74 */
> > + u32 cmeor2; /* 0x78 */
> > + u32 cmeor3; /* 0x7C */
> > + u32 cmeor4; /* 0x80 */
> > + u32 cmeor5; /* 0x84 */
> > + u32 cppdsr; /* 0x88 */
> > + u32 ccowr; /* 0x8C */
> > + u32 ccpgr0; /* 0x90 */
> > + u32 ccpgr1; /* 0x94 */
> > + u32 ccpgr2; /* 0x98 */
> > + u32 ccpgr3; /* 0x9C */
> > +};
> > +
> > +/* WEIM registers */
> > +struct weim {
> > + u32 cs0gcr1;
> > + u32 cs0gcr2;
> > + u32 cs0rcr1;
> > + u32 cs0rcr2;
> > + u32 cs0wcr1;
> > + u32 cs0wcr2;
> > + u32 cs1gcr1;
> > + u32 cs1gcr2;
> > + u32 cs1rcr1;
> > + u32 cs1rcr2;
> > + u32 cs1wcr1;
> > + u32 cs1wcr2;
> > + u32 cs2gcr1;
> > + u32 cs2gcr2;
> > + u32 cs2rcr1;
> > + u32 cs2rcr2;
> > + u32 cs2wcr1;
> > + u32 cs2wcr2;
> > + u32 cs3gcr1;
> > + u32 cs3gcr2;
> > + u32 cs3rcr1;
> > + u32 cs3rcr2;
> > + u32 cs3wcr1;
> > + u32 cs3wcr2;
> > + u32 cs4gcr1;
> > + u32 cs4gcr2;
> > + u32 cs4rcr1;
> > + u32 cs4rcr2;
> > + u32 cs4wcr1;
> > + u32 cs4wcr2;
> > + u32 cs5gcr1;
> > + u32 cs5gcr2;
> > + u32 cs5rcr1;
> > + u32 cs5rcr2;
> > + u32 cs5wcr1;
> > + u32 cs5wcr2;
> > + u32 wcr;
> > + u32 wiar;
> > + u32 ear;
> > +};
> > +
>
> I think about if we cann avoid to duplicate another time this structure,
> moving it into a common place. See MX5 struct weim.
>
> > +struct anadig {
> > + u32 usb1_pll_ctrl;
> > + u32 usb2_pll_ctrl;
> > + u32 pll_528_ctrl;
> > + u32 pll_528_ss;
> > + u32 pll_528_num;
> > + u32 pll_528_denom;
> > + u32 pll_aud_ctrl;
> > + u32 pll_aud_num;
> > + u32 pll_aud_denom;
> > + u32 pll_vid_ctrl;
> > + u32 pll_vid_num;
> > + u32 pll_vid_denom;
> > + u32 pll_enet_ctrl;
> > + u32 pll_pfd_480_usb1;
> > + u32 pll_pfd_528;
> > + u32 reg_1p1;
> > + u32 reg_3p0;
> > + u32 reg_2p5;
> > + u32 ana_misc0;
> > + u32 ana_misc1;
> > + u32 tempsens0;
> > + u32 usb1_vbus_det;
> > + u32 usb1_vbus_chrg_det;
> > + u32 usb1_vbus_detsta;
> > + u32 usb1_chrg_detsta;
> > + u32 usb1_loopback;
> > + u32 usb1_misc;
> > + u32 usb2_vbus_det;
> > + u32 usb2_vbus_chrg_det;
> > + u32 usb2_vbus_detsta;
> > + u32 usb2_chrg_detsta;
> > + u32 usb2_loopback;
> > + u32 usb2_misc;
> > + u32 digprog;
> > + u32 pll_sys_ctrl;
> > + u32 pll_sys_ss;
> > + u32 pll_sys_num;
> > + u32 pll_sys_denom;
> > + u32 pfd_528_sys;
> > + u32 pll_lock;
> > +};
> > +
> > +struct iomuxc {
> > + u32 gpr0;
> > + u32 gpr1;
> > + u32 omux0;
> > + u32 omux1;
> > + u32 omux2;
> > + u32 omux3;
> > + u32 omux4;
> > +};
> > +
> > +/* System Reset Controller (SRC) */
> > +struct src {
> > + u32 scr; /* 0x00 */
> > + u32 sbmr1; /* 0x04 */
> > + u32 srsr; /* 0x08 */
> > + u32 secr; /* 0x0C */
> > + u32 gpsr; /* 0x10 */
> > + u32 sicr; /* 0x14 */
> > + u32 simr; /* 0x18 */
> > + u32 sbmr2; /* 0x1C */
> > + u32 gpr0; /* 0x20 */
> > + u32 gpr1; /* 0x24 */
> > + u32 gpr2; /* 0x28 */
> > + u32 gpr3; /* 0x2C */
> > + u32 gpr4; /* 0x30 */
> > + u32 hab0; /* 0x34 */
> > + u32 hab1; /* 0x38 */
> > + u32 hab2; /* 0x3C */
> > + u32 hab3; /* 0x40 */
> > + u32 hab4; /* 0x44 */
> > + u32 hab5; /* 0x48 */
> > + u32 misc0; /* 0x4C */
> > + u32 misc1; /* 0x50 */
> > + u32 misc2; /* 0x54 */
> > + u32 misc3; /* 0x58 */
> > +};
> > +
> > +struct fuse_bank1_regs {
> > + u32 fuse0_8[9];
> > + u32 mac_addr[6];
> > + u32 fuse15_31[0x11];
> > +};
> > +
> > +#define ANADIG_USB1_PLL_CTRL (0x10)
> > +#define ANADIG_USB2_PLL_CTRL (0x20)
> > +#define ANADIG_PLL_528_CTRL (0x30)
> > +#define ANADIG_PLL_528_SS (0x40)
> > +#define ANADIG_PLL_528_NUM (0x50)
> > +#define ANADIG_PLL_528_DENOM (0x60)
> > +#define ANADIG_PLL_AUD_CTRL (0x70)
> > +#define ANADIG_PLL_AUD_NUM (0x80)
> > +#define ANADIG_PLL_AUD_DENOM (0x90)
> > +#define ANADIG_PLL_VID_CTRL (0xA0)
> > +#define ANADIG_PLL_VID_NUM (0xB0)
> > +#define ANADIG_PLL_VID_DENOM (0xC0)
> > +#define ANADIG_PLL_ENET_CTRL (0xE0)
> > +#define ANADIG_PLL_PFD_480_USB1 (0xF0)
> > +#define ANADIG_PLL_PFD_528 (0x100)
> > +#define ANADIG_REG_1P1 (0x110)
> > +#define ANADIG_REG_3P0 (0x120)
> > +#define ANADIG_REG_2P5 (0x130)
> > +#define ANADIG_ANA_MISC0 (0x150)
> > +#define ANADIG_ANA_MISC1 (0x160)
> > +#define ANADIG_TEMPSENS0 (0x180)
> > +#define ANADIG_USB1_VBUS_DET (0x1A0)
> > +#define ANADIG_USB1_CHRG_DET (0x1B0)
> > +#define ANADIG_USB1_VBUS_DETSTA (0x1C0)
> > +#define ANADIG_UAB1_CHRG_DETSTA (0x1D0)
> > +#define ANADIG_USB1_LOOPBACK (0x1E0)
> > +#define ANADIG_USB1_MISC (0x1F0)
> > +#define ANADIG_USB2_VBUS_DET (0x200)
> > +#define ANADIG_USB2_CHRG_DET (0x210)
> > +#define ANADIG_USB2_VBUS_DETSTA (0x220)
> > +#define ANADIG_USB2_CHRG_DETSTA (0x230)
> > +#define ANADIG_USB2_LOOPBACK (0x240)
> > +#define ANADIG_USB2_MISC (0x250)
> > +#define ANADIG_DIGPROG (0x260)
> > +#define ANADIG_PLL_SYS_CTRL (0x270)
> > +#define ANADIG_PLL_SYS_SS (0x280)
> > +#define ANADIG_PLL_SYS_NUM (0x290)
> > +#define ANADIG_PLL_SYS_DENOM (0x2A0)
> > +#define ANADIG_PFD_528_SYS (0x2B0)
> > +#define ANADIG_PLL_LOCK (0x2C0)
> > +
> > +#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
> > +#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
> > +
> > +#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
> > +#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
> > +
> > +#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
> > +#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
> > +
> > +#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
> > +#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
> > +#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
> > +#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
> > +#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
> > +#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
> > +
> > +#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
> > +#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
> > +
> > +#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
> > +#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
> > +
> > +#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
> > +#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
> > +
> > +#define FASE_CLK_FREQ 24000000
> > +#define SLOW_CLK_FREQ 32000
> > +#define PLL1_PFD1_FREQ 500000000
> > +#define PLL1_PFD2_FREQ 452000000
> > +#define PLL1_PFD3_FREQ 396000000
> > +#define PLL1_PFD4_FREQ 528000000
> > +#define PLL1_MAIN_FREQ 528000000
> > +#define PLL2_PFD1_FREQ 500000000
> > +#define PLL2_PFD2_FREQ 396000000
> > +#define PLL2_PFD3_FREQ 339000000
> > +#define PLL2_PFD4_FREQ 413000000
> > +#define PLL2_MAIN_FREQ 528000000
> > +#define PLL3_MAIN_FREQ 480000000
> > +#define PLL3_PFD3_FREQ 298000000
> > +#define PLL5_MAIN_FREQ 500000000
> > +
> > +#define ENET_EXTERNAL_CLK 50000000
> > +#define AUDIO_EXTERNAL_CLK 24576000
> > +
> > +#define DDR_CR_BASE DDR_BASE_ADDR
> > +#define DDR_PHY_BASE (DDR_BASE_ADDR + 0x400)
> > +
> > +#define DDR_CR000 (DDR_CR_BASE + 0x000)
> > +#define DDR_CR001 (DDR_CR_BASE + 0x004)
> > +#define DDR_CR002 (DDR_CR_BASE + 0x008)
> > +#define DDR_CR003 (DDR_CR_BASE + 0x00C)
> > +#define DDR_CR004 (DDR_CR_BASE + 0x010)
> > +#define DDR_CR005 (DDR_CR_BASE + 0x014)
> > +#define DDR_CR006 (DDR_CR_BASE + 0x018)
> > +#define DDR_CR007 (DDR_CR_BASE + 0x01C)
> > +#define DDR_CR008 (DDR_CR_BASE + 0x020)
> > +#define DDR_CR009 (DDR_CR_BASE + 0x024)
> > +
> > +#define DDR_CR010 (DDR_CR_BASE + 0x028)
> > +#define DDR_CR011 (DDR_CR_BASE + 0x02C)
> > +#define DDR_CR012 (DDR_CR_BASE + 0x030)
> > +#define DDR_CR013 (DDR_CR_BASE + 0x034)
> > +#define DDR_CR014 (DDR_CR_BASE + 0x038)
> > +#define DDR_CR015 (DDR_CR_BASE + 0x03C)
> > +#define DDR_CR016 (DDR_CR_BASE + 0x040)
> > +#define DDR_CR017 (DDR_CR_BASE + 0x044)
> > +#define DDR_CR018 (DDR_CR_BASE + 0x048)
> > +#define DDR_CR019 (DDR_CR_BASE + 0x04C)
> > +
> > +#define DDR_CR020 (DDR_CR_BASE + 0x050)
> > +#define DDR_CR021 (DDR_CR_BASE + 0x054)
> > +#define DDR_CR022 (DDR_CR_BASE + 0x058)
> > +#define DDR_CR023 (DDR_CR_BASE + 0x05C)
> > +#define DDR_CR024 (DDR_CR_BASE + 0x060)
> > +#define DDR_CR025 (DDR_CR_BASE + 0x064)
> > +#define DDR_CR026 (DDR_CR_BASE + 0x068)
> > +#define DDR_CR027 (DDR_CR_BASE + 0x06C)
> > +#define DDR_CR028 (DDR_CR_BASE + 0x070)
> > +#define DDR_CR029 (DDR_CR_BASE + 0x074)
> > +
> > +#define DDR_CR030 (DDR_CR_BASE + 0x078)
> > +#define DDR_CR031 (DDR_CR_BASE + 0x07C)
> > +#define DDR_CR032 (DDR_CR_BASE + 0x080)
> > +#define DDR_CR033 (DDR_CR_BASE + 0x084)
> > +#define DDR_CR034 (DDR_CR_BASE + 0x088)
> > +#define DDR_CR035 (DDR_CR_BASE + 0x08C)
> > +#define DDR_CR036 (DDR_CR_BASE + 0x090)
> > +#define DDR_CR037 (DDR_CR_BASE + 0x094)
> > +#define DDR_CR038 (DDR_CR_BASE + 0x098)
> > +#define DDR_CR039 (DDR_CR_BASE + 0x09C)
> > +
> > +#define DDR_CR040 (DDR_CR_BASE + 0x0A0)
> > +#define DDR_CR041 (DDR_CR_BASE + 0x0A4)
> > +#define DDR_CR042 (DDR_CR_BASE + 0x0A8)
> > +#define DDR_CR043 (DDR_CR_BASE + 0x0AC)
> > +#define DDR_CR044 (DDR_CR_BASE + 0x0B0)
> > +#define DDR_CR045 (DDR_CR_BASE + 0x0B4)
> > +#define DDR_CR046 (DDR_CR_BASE + 0x0B8)
> > +#define DDR_CR047 (DDR_CR_BASE + 0x0BC)
> > +#define DDR_CR048 (DDR_CR_BASE + 0x0C0)
> > +#define DDR_CR049 (DDR_CR_BASE + 0x0C4)
> > +
> > +#define DDR_CR050 (DDR_CR_BASE + 0x0C8)
> > +#define DDR_CR051 (DDR_CR_BASE + 0x0CC)
> > +#define DDR_CR052 (DDR_CR_BASE + 0x0D0)
> > +#define DDR_CR053 (DDR_CR_BASE + 0x0D4)
> > +#define DDR_CR054 (DDR_CR_BASE + 0x0D8)
> > +#define DDR_CR055 (DDR_CR_BASE + 0x0DC)
> > +#define DDR_CR056 (DDR_CR_BASE + 0x0E0)
> > +#define DDR_CR057 (DDR_CR_BASE + 0x0E4)
> > +#define DDR_CR058 (DDR_CR_BASE + 0x0E8)
> > +#define DDR_CR059 (DDR_CR_BASE + 0x0EC)
> > +
> > +#define DDR_CR060 (DDR_CR_BASE + 0x0F0)
> > +#define DDR_CR061 (DDR_CR_BASE + 0x0F4)
> > +#define DDR_CR062 (DDR_CR_BASE + 0x0F8)
> > +#define DDR_CR063 (DDR_CR_BASE + 0x0FC)
> > +#define DDR_CR064 (DDR_CR_BASE + 0x100)
> > +#define DDR_CR065 (DDR_CR_BASE + 0x104)
> > +#define DDR_CR066 (DDR_CR_BASE + 0x108)
> > +#define DDR_CR067 (DDR_CR_BASE + 0x10C)
> > +#define DDR_CR068 (DDR_CR_BASE + 0x110)
> > +#define DDR_CR069 (DDR_CR_BASE + 0x114)
> > +
> > +#define DDR_CR070 (DDR_CR_BASE + 0x118)
> > +#define DDR_CR071 (DDR_CR_BASE + 0x11C)
> > +#define DDR_CR072 (DDR_CR_BASE + 0x120)
> > +#define DDR_CR073 (DDR_CR_BASE + 0x124)
> > +#define DDR_CR074 (DDR_CR_BASE + 0x128)
> > +#define DDR_CR075 (DDR_CR_BASE + 0x12C)
> > +#define DDR_CR076 (DDR_CR_BASE + 0x130)
> > +#define DDR_CR077 (DDR_CR_BASE + 0x134)
> > +#define DDR_CR078 (DDR_CR_BASE + 0x138)
> > +#define DDR_CR079 (DDR_CR_BASE + 0x13C)
> > +
> > +#define DDR_CR080 (DDR_CR_BASE + 0x140)
> > +#define DDR_CR081 (DDR_CR_BASE + 0x144)
> > +#define DDR_CR082 (DDR_CR_BASE + 0x148)
> > +#define DDR_CR083 (DDR_CR_BASE + 0x14C)
> > +#define DDR_CR084 (DDR_CR_BASE + 0x150)
> > +#define DDR_CR085 (DDR_CR_BASE + 0x154)
> > +#define DDR_CR086 (DDR_CR_BASE + 0x158)
> > +#define DDR_CR087 (DDR_CR_BASE + 0x15C)
> > +#define DDR_CR088 (DDR_CR_BASE + 0x160)
> > +#define DDR_CR089 (DDR_CR_BASE + 0x164)
> > +
> > +#define DDR_CR090 (DDR_CR_BASE + 0x168)
> > +#define DDR_CR091 (DDR_CR_BASE + 0x16C)
> > +#define DDR_CR092 (DDR_CR_BASE + 0x170)
> > +#define DDR_CR093 (DDR_CR_BASE + 0x174)
> > +#define DDR_CR094 (DDR_CR_BASE + 0x178)
> > +#define DDR_CR095 (DDR_CR_BASE + 0x17C)
> > +#define DDR_CR096 (DDR_CR_BASE + 0x180)
> > +#define DDR_CR097 (DDR_CR_BASE + 0x184)
> > +#define DDR_CR098 (DDR_CR_BASE + 0x188)
> > +#define DDR_CR099 (DDR_CR_BASE + 0x18C)
> > +
> > +#define DDR_CR100 (DDR_CR_BASE + 0x190)
> > +#define DDR_CR101 (DDR_CR_BASE + 0x194)
> > +#define DDR_CR102 (DDR_CR_BASE + 0x198)
> > +#define DDR_CR103 (DDR_CR_BASE + 0x19C)
> > +#define DDR_CR104 (DDR_CR_BASE + 0x1A0)
> > +#define DDR_CR105 (DDR_CR_BASE + 0x1A4)
> > +#define DDR_CR106 (DDR_CR_BASE + 0x1A8)
> > +#define DDR_CR107 (DDR_CR_BASE + 0x1AC)
> > +#define DDR_CR108 (DDR_CR_BASE + 0x1B0)
> > +#define DDR_CR109 (DDR_CR_BASE + 0x1B4)
> > +
> > +#define DDR_CR110 (DDR_CR_BASE + 0x1B8)
> > +#define DDR_CR111 (DDR_CR_BASE + 0x1BC)
> > +#define DDR_CR112 (DDR_CR_BASE + 0x1C0)
> > +#define DDR_CR113 (DDR_CR_BASE + 0x1C4)
> > +#define DDR_CR114 (DDR_CR_BASE + 0x1C8)
> > +#define DDR_CR115 (DDR_CR_BASE + 0x1CC)
> > +#define DDR_CR116 (DDR_CR_BASE + 0x1D0)
> > +#define DDR_CR117 (DDR_CR_BASE + 0x1D4)
> > +#define DDR_CR118 (DDR_CR_BASE + 0x1D8)
> > +#define DDR_CR119 (DDR_CR_BASE + 0x1DC)
> > +
> > +#define DDR_CR120 (DDR_CR_BASE + 0x1E0)
> > +#define DDR_CR121 (DDR_CR_BASE + 0x1E4)
> > +#define DDR_CR122 (DDR_CR_BASE + 0x1E8)
> > +#define DDR_CR123 (DDR_CR_BASE + 0x1EC)
> > +#define DDR_CR124 (DDR_CR_BASE + 0x1F0)
> > +#define DDR_CR125 (DDR_CR_BASE + 0x1F4)
> > +#define DDR_CR126 (DDR_CR_BASE + 0x1F8)
> > +#define DDR_CR127 (DDR_CR_BASE + 0x1FC)
> > +#define DDR_CR128 (DDR_CR_BASE + 0x200)
> > +#define DDR_CR129 (DDR_CR_BASE + 0x204)
> > +
> > +#define DDR_CR130 (DDR_CR_BASE + 0x208)
> > +#define DDR_CR131 (DDR_CR_BASE + 0x20C)
> > +#define DDR_CR132 (DDR_CR_BASE + 0x210)
> > +#define DDR_CR133 (DDR_CR_BASE + 0x214)
> > +#define DDR_CR134 (DDR_CR_BASE + 0x218)
> > +#define DDR_CR135 (DDR_CR_BASE + 0x21C)
> > +#define DDR_CR136 (DDR_CR_BASE + 0x220)
> > +#define DDR_CR137 (DDR_CR_BASE + 0x224)
> > +#define DDR_CR138 (DDR_CR_BASE + 0x228)
> > +#define DDR_CR139 (DDR_CR_BASE + 0x22C)
> > +
> > +#define DDR_CR140 (DDR_CR_BASE + 0x230)
> > +#define DDR_CR141 (DDR_CR_BASE + 0x234)
> > +#define DDR_CR142 (DDR_CR_BASE + 0x238)
> > +#define DDR_CR143 (DDR_CR_BASE + 0x23C)
> > +#define DDR_CR144 (DDR_CR_BASE + 0x240)
> > +#define DDR_CR145 (DDR_CR_BASE + 0x244)
> > +#define DDR_CR146 (DDR_CR_BASE + 0x248)
> > +#define DDR_CR147 (DDR_CR_BASE + 0x24C)
> > +#define DDR_CR148 (DDR_CR_BASE + 0x250)
> > +#define DDR_CR149 (DDR_CR_BASE + 0x254)
> > +
> > +#define DDR_CR150 (DDR_CR_BASE + 0x258)
> > +#define DDR_CR151 (DDR_CR_BASE + 0x25C)
> > +#define DDR_CR152 (DDR_CR_BASE + 0x260)
> > +#define DDR_CR153 (DDR_CR_BASE + 0x264)
> > +#define DDR_CR154 (DDR_CR_BASE + 0x268)
> > +#define DDR_CR155 (DDR_CR_BASE + 0x26C)
> > +#define DDR_CR156 (DDR_CR_BASE + 0x270)
> > +#define DDR_CR157 (DDR_CR_BASE + 0x274)
> > +#define DDR_CR158 (DDR_CR_BASE + 0x278)
> > +#define DDR_CR159 (DDR_CR_BASE + 0x27C)
> > +
> > +#define DDR_CR160 (DDR_CR_BASE + 0x280)
> > +#define DDR_CR161 (DDR_CR_BASE + 0x284)
> > +#define DDR_CR162 (DDR_CR_BASE + 0x288)
> > +#define DDR_CR163 (DDR_CR_BASE + 0x28C)
> > +#define DDR_CR164 (DDR_CR_BASE + 0x290)
> > +#define DDR_CR165 (DDR_CR_BASE + 0x294)
> > +#define DDR_CR166 (DDR_CR_BASE + 0x298)
> > +#define DDR_CR167 (DDR_CR_BASE + 0x29C)
> > +#define DDR_CR168 (DDR_CR_BASE + 0x2A0)
> > +#define DDR_CR169 (DDR_CR_BASE + 0x2A4)
> > +
> > +#define DDR_CR170 (DDR_CR_BASE + 0x2A8)
> > +#define DDR_CR171 (DDR_CR_BASE + 0x2AC)
> > +#define DDR_CR172 (DDR_CR_BASE + 0x2B0)
> > +#define DDR_CR173 (DDR_CR_BASE + 0x2B4)
> > +#define DDR_CR174 (DDR_CR_BASE + 0x2B8)
> > +#define DDR_CR175 (DDR_CR_BASE + 0x2BC)
> > +#define DDR_CR176 (DDR_CR_BASE + 0x2C0)
> > +#define DDR_CR177 (DDR_CR_BASE + 0x2C4)
> > +#define DDR_CR178 (DDR_CR_BASE + 0x2C8)
> > +#define DDR_CR179 (DDR_CR_BASE + 0x2CC)
> > +
> > +/*
> > + * PHY
> > + */
> > +#define DDR_PHY000 (DDR_PHY_BASE + 0x000)
> > +#define DDR_PHY001 (DDR_PHY_BASE + 0x004)
> > +#define DDR_PHY002 (DDR_PHY_BASE + 0x008)
> > +#define DDR_PHY003 (DDR_PHY_BASE + 0x00C)
> > +#define DDR_PHY004 (DDR_PHY_BASE + 0x010)
> > +#define DDR_PHY005 (DDR_PHY_BASE + 0x014)
> > +#define DDR_PHY006 (DDR_PHY_BASE + 0x018)
> > +#define DDR_PHY007 (DDR_PHY_BASE + 0x01C)
> > +#define DDR_PHY008 (DDR_PHY_BASE + 0x020)
> > +#define DDR_PHY009 (DDR_PHY_BASE + 0x024)
> > +
> > +#define DDR_PHY010 (DDR_PHY_BASE + 0x028)
> > +#define DDR_PHY011 (DDR_PHY_BASE + 0x02C)
> > +#define DDR_PHY012 (DDR_PHY_BASE + 0x030)
> > +#define DDR_PHY013 (DDR_PHY_BASE + 0x034)
> > +#define DDR_PHY014 (DDR_PHY_BASE + 0x038)
> > +#define DDR_PHY015 (DDR_PHY_BASE + 0x03C)
> > +#define DDR_PHY016 (DDR_PHY_BASE + 0x040)
> > +#define DDR_PHY017 (DDR_PHY_BASE + 0x044)
> > +#define DDR_PHY018 (DDR_PHY_BASE + 0x048)
> > +#define DDR_PHY019 (DDR_PHY_BASE + 0x04C)
> > +
> > +#define DDR_PHY020 (DDR_PHY_BASE + 0x050)
> > +#define DDR_PHY021 (DDR_PHY_BASE + 0x054)
> > +#define DDR_PHY022 (DDR_PHY_BASE + 0x058)
> > +#define DDR_PHY023 (DDR_PHY_BASE + 0x05C)
> > +#define DDR_PHY024 (DDR_PHY_BASE + 0x060)
> > +#define DDR_PHY025 (DDR_PHY_BASE + 0x064)
> > +#define DDR_PHY026 (DDR_PHY_BASE + 0x068)
> > +#define DDR_PHY027 (DDR_PHY_BASE + 0x06C)
> > +#define DDR_PHY028 (DDR_PHY_BASE + 0x070)
> > +#define DDR_PHY029 (DDR_PHY_BASE + 0x074)
> > +
> > +#define DDR_PHY030 (DDR_PHY_BASE + 0x078)
> > +#define DDR_PHY031 (DDR_PHY_BASE + 0x07C)
> > +#define DDR_PHY032 (DDR_PHY_BASE + 0x080)
> > +#define DDR_PHY033 (DDR_PHY_BASE + 0x084)
> > +#define DDR_PHY034 (DDR_PHY_BASE + 0x088)
> > +#define DDR_PHY035 (DDR_PHY_BASE + 0x08C)
> > +#define DDR_PHY036 (DDR_PHY_BASE + 0x090)
> > +#define DDR_PHY037 (DDR_PHY_BASE + 0x094)
> > +#define DDR_PHY038 (DDR_PHY_BASE + 0x098)
> > +#define DDR_PHY039 (DDR_PHY_BASE + 0x09C)
> > +
> > +#define DDR_PHY040 (DDR_PHY_BASE + 0x0A0)
> > +#define DDR_PHY041 (DDR_PHY_BASE + 0x0A4)
> > +#define DDR_PHY042 (DDR_PHY_BASE + 0x0A8)
> > +#define DDR_PHY043 (DDR_PHY_BASE + 0x0AC)
> > +#define DDR_PHY044 (DDR_PHY_BASE + 0x0B0)
> > +#define DDR_PHY045 (DDR_PHY_BASE + 0x0B4)
> > +#define DDR_PHY046 (DDR_PHY_BASE + 0x0B8)
> > +#define DDR_PHY047 (DDR_PHY_BASE + 0x0BC)
> > +#define DDR_PHY048 (DDR_PHY_BASE + 0x0C0)
> > +#define DDR_PHY049 (DDR_PHY_BASE + 0x0C4)
> > +
> > +#define DDR_PHY050 (DDR_PHY_BASE + 0x0C8)
> > +#define DDR_PHY051 (DDR_PHY_BASE + 0x0CC)
> > +#define DDR_PHY052 (DDR_PHY_BASE + 0x0D0)
> > +#define DDR_PHY053 (DDR_PHY_BASE + 0x0D4)
> > +#define DDR_PHY054 (DDR_PHY_BASE + 0x0D8)
> > +#define DDR_PHY055 (DDR_PHY_BASE + 0x0DC)
> > +#define DDR_PHY056 (DDR_PHY_BASE + 0x0E0)
> > +#define DDR_PHY057 (DDR_PHY_BASE + 0x0E4)
> > +#define DDR_PHY058 (DDR_PHY_BASE + 0x0E8)
> > +#define DDR_PHY059 (DDR_PHY_BASE + 0x0EC)
> > +
> > +#define DDR_PHY060 (DDR_PHY_BASE + 0x0F0)
> > +#define DDR_PHY061 (DDR_PHY_BASE + 0x0F4)
> > +#define DDR_PHY062 (DDR_PHY_BASE + 0x0F8)
> > +#define DDR_PHY063 (DDR_PHY_BASE + 0x0FC)
> > +#define DDR_PHY064 (DDR_PHY_BASE + 0x100)
> > +#define DDR_PHY065 (DDR_PHY_BASE + 0x104)
> > +#define DDR_PHY066 (DDR_PHY_BASE + 0x108)
> > +#define DDR_PHY067 (DDR_PHY_BASE + 0x10C)
> > +#define DDR_PHY068 (DDR_PHY_BASE + 0x110)
> > +
> > +#endif /* __ASSEMBLER__*/
> > +
> > +#endif /* __ASM_ARCH_VYBRID_REGS_H__ */
> > diff --git a/arch/arm/include/asm/global_data.h
> b/arch/arm/include/asm/global_data.h
> > index 37ac0da..bb7ebc2 100644
> > --- a/arch/arm/include/asm/global_data.h
> > +++ b/arch/arm/include/asm/global_data.h
> > @@ -29,6 +29,9 @@ struct arch_global_data {
> > #if defined(CONFIG_FSL_ESDHC)
> > u32 sdhc_clk;
> > #endif
> > +#ifdef CONFIG_SYS_IPG
> > + unsigned long ipg_clk;
> > +#endif
> > #ifdef CONFIG_AT91FAMILY
> > /* "static data" needed by at91's clock.c */
> > unsigned long cpu_clk_rate_hz;
> > diff --git a/arch/arm/include/asm/mach-types.h
> b/arch/arm/include/asm/mach-types.h
> > index a676b6d..31d67bf 100644
> > --- a/arch/arm/include/asm/mach-types.h
> > +++ b/arch/arm/include/asm/mach-types.h
> > @@ -1107,6 +1107,10 @@ extern unsigned int __machine_arch_type;
> > #define MACH_TYPE_OMAP5_SEVM 3777
> > #define MACH_TYPE_ARMADILLO_800EVA 3863
> > #define MACH_TYPE_KZM9G 4140
> > +#define MACH_TYPE_VYBRID_VF7XX 4145
> > +#define MACH_TYPE_VYBRID_VF6XX 4146
> > +#define MACH_TYPE_VYBRID_VF5XX 4147
> > +#define MACH_TYPE_VYBRID_VF4XX 4148
> >
>
> No, we drop this. Set instead CONFIG_MACH_TYPE in your board
> configuration file.
[Alison Wang] Agree. I will set in board configuration file in the next version patches.
Thanks a lot!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-28 10:36 ` Wang Huan-B18965
@ 2013-04-28 10:59 ` Stefano Babic
0 siblings, 0 replies; 27+ messages in thread
From: Stefano Babic @ 2013-04-28 10:59 UTC (permalink / raw)
To: u-boot
On 28/04/2013 12:36, Wang Huan-B18965 wrote:
>>
>> I would like to understand there common code should be put. As you
>> can see, for i.MX there is a imx_common directory that is valid
>> across ARM-Core.
> [Alison Wang] I'm trying to align the soc with i.mx platform and will
> use i.MX's imx_common directory in the next version. But there are
> still some issues for sharing the I.MX platform,
>
> 1. i.mx family uses GPT in timer.c. VF600 doesn't have GPT but a
> Periodic Interrupt Timer(PIT) which I think is totally different with
> GPT. Too much ifdef in the timer.c seems unacceptable. So I plan to
> modify the Makefile and add a pit.c file in imx_common directory for
> the timer on this Vybrid platform, How do you think about this idea?
> Thanks.
We do not need to put everything in imx-common if there is nothing in
common. Of course, a new driver is fully acceptable if it support a
device that it is not yet mainlined.
> 2. The SRC_SRSR register definition on VF600 is different with i.MX.
> To reuse the get_reset_cause() function in cpu.c, some platform
> related ifdef will be introduced. For example: #ifdef CONFIG_MVF600
> case 0x00080: return "EXTERNAL RESET"; #endif
>
> Does this kind of ifdef acceptable? Thanks.
Only if there are some differences, but most code is shared. We have a
get_reset_cause() in imx-common/cpu.c, but also a specific
get_reset_cause() for mx25/mx31/mx35. The question can be better
answered after you post the code.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support
2013-04-12 6:53 ` [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support Alison Wang
2013-04-12 11:15 ` Fabio Estevam
2013-04-13 20:32 ` Stefano Babic
@ 2013-04-15 3:24 ` Liu Hui-R64343
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D82FB99D@039-SN1MPN1-002.039d.mgd.msft.net>
2 siblings, 1 reply; 27+ messages in thread
From: Liu Hui-R64343 @ 2013-04-15 3:24 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Wang Huan-B18965
>Sent: Friday, April 12, 2013 2:54 PM
>To: u-boot at lists.denx.de
>Cc: sbabic at denx.de; Liu Hui-R64343; Estevam Fabio-R49496; TsiChung Liew;
>Jin Zhengxiong-R64188
>Subject: [PATCH 1/5] vybrid: add vybrid CPU support
>
>The Vybrid devices are a family of Freescale's latest Dual Single
>Core offering with ARM Cortex A5 and CM4 based processors for
>Advanced Connected Radio, Entry Infotainment, and Cluster as well
>as high end industrial and general purpose applications.
>
>This patch adds vybrid CPU support.
>
>Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
>Signed-off-by: Jason Jin <Jason.jin@freescale.com>
>Signed-off-by: Alison Wang <b18965@freescale.com>
>---
> Makefile | 8 +
> arch/arm/cpu/armv7/vybrid-common/Makefile | 46 ++
> arch/arm/cpu/armv7/vybrid-common/cpu.c | 127 ++++
> arch/arm/cpu/armv7/vybrid-common/speed.c | 37 ++
> arch/arm/cpu/armv7/vybrid-common/timer.c | 140 +++++
> arch/arm/cpu/armv7/vybrid/Makefile | 45 ++
> arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 +++
> arch/arm/cpu/armv7/vybrid/clock.c | 278 +++++++++
> arch/arm/cpu/armv7/vybrid/iomux.c | 42 ++
> arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 128 ++++
> arch/arm/cpu/armv7/vybrid/soc.c | 42 ++
> arch/arm/include/asm/arch-vybrid/clock.h | 41 ++
> arch/arm/include/asm/arch-vybrid/iomux.h | 323 ++++++++++
> arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213 +++++++
> arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 +
> arch/arm/include/asm/arch-vybrid/timer.h | 405 +++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 +++
> arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735
>+++++++++++++++++++++++
> arch/arm/include/asm/global_data.h | 3 +
> arch/arm/include/asm/mach-types.h | 56 ++
> 20 files changed, 2857 insertions(+)
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/iomux.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c
> create mode 100644 arch/arm/include/asm/arch-vybrid/clock.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>
>diff --git a/Makefile b/Makefile
>index 12763ce..8a86951 100644
>--- a/Makefile
>+++ b/Makefile
>@@ -334,6 +334,9 @@ LIBS-y += test/libtest.o
> ifneq
>($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
> LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
> endif
>+ifeq ($(SOC),vybrid)
>+LIBS-y += $(CPUDIR)/vybrid-common/libvybrid-common.o
>+endif
>
> ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
> LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
>@@ -467,6 +470,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin
> $(obj)u-boot.imx: $(obj)u-boot.bin depend
> $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-
>boot.imx
>
>+$(obj)u-boot.vybrid: $(obj)u-boot.bin
>+ $(obj)tools/mkimage -n $(CONFIG_VYBRID_CONFIG) -T imximage \
>+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
>+
> $(obj)u-boot.kwb: $(obj)u-boot.bin
> $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage
>\
> -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $<
>$@
>@@ -855,6 +862,7 @@ clobber: tidy
> @rm -f $(obj)u-boot.kwb
> @rm -f $(obj)u-boot.pbl
> @rm -f $(obj)u-boot.imx
>+ @rm -f $(obj)u-boot.vybrid
> @rm -f $(obj)u-boot.ubl
> @rm -f $(obj)u-boot.ais
> @rm -f $(obj)u-boot.dtb
>diff --git a/arch/arm/cpu/armv7/vybrid-common/Makefile
>b/arch/arm/cpu/armv7/vybrid-common/Makefile
>new file mode 100644
>index 0000000..bee8850
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
>@@ -0,0 +1,46 @@
>+#
>+# Copyright 2012-2013 Freescale Semiconductor, Inc.
>+#
>+# See file CREDITS for list of people who contributed to this
>+# project.
>+#
>+# This program is free software; you can redistribute it and/or
>+# modify it under the terms of the GNU General Public License as
>+# published by the Free Software Foundation; either version 2 of
>+# the License, or (at your option) any later version.
>+#
>+# This program is distributed in the hope that it will be useful,
>+# but WITHOUT ANY WARRANTY; without even the implied warranty of
>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+# GNU General Public License for more details.
>+#
>+# You should have received a copy of the GNU General Public License
>+# along with this program; if not, write to the Free Software
>+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+# MA 02111-1307 USA
>+#
>+
>+include $(TOPDIR)/config.mk
>+
>+LIB = $(obj)libvybrid-common.o
>+
>+COBJS := timer.o
>+COBJS += cpu.o
>+COBJS += speed.o
>+
>+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
>+
>+all: $(obj).depend $(LIB)
>+
>+$(LIB): $(OBJS)
>+ $(call cmd_link_o_target, $(OBJS))
>+
>+#######################################################################
>##
>+
>+# defines $(obj).depend target
>+include $(SRCTREE)/rules.mk
>+
>+sinclude $(obj).depend
>+
>+#######################################################################
>##
>diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c
>b/arch/arm/cpu/armv7/vybrid-common/cpu.c
>new file mode 100644
>index 0000000..f99083e
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
>@@ -0,0 +1,127 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <netdev.h>
>+#include <asm/errno.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/sys_proto.h>
>+
>+#ifdef CONFIG_FSL_ESDHC
>+#include <fsl_esdhc.h>
>+#endif
>+
>+static char *get_reset_cause(void)
>+{
>+ char *resetcause[32] = {"POR",
>+ "Cortex A5 WDOG Timer Reset",
>+ 0,
>+ "CA5 WDOG reset",
>+ "CM4 WDOG reset",
>+ "JTAG HIGH-Z",
>+ 0,
>+ "External Reset",
>+ "1.2V supply below 0.7V",
>+ "HP regulator's LVD",
>+ "ULP regulator's LVD",
>+ "3.3V main supply is unstable",
>+ "LP regulator's LVD",
>+ 0,
>+ 0,
>+ 0,
>+ "MDM-AP system reset request is set",
>+ "Hard Fail State of System Security Monitor",
>+ "SRC_SCR SW Reset is set",
>+ "Platform's CSU alarm event",
>+ 0,
>+ 0,
>+ 0,
>+ 0,
>+ "Anadig regulator 1.1V unstable",
>+ "Anadig regulator 2.5V unstable",
>+ "Anadig regulator 3.0V unstable",
>+ "CMU even when FOSC freq less than 40MHz",
>+ "CMU event when BUS freq is out of range",
>+ "No clock is detected on FOSC",
>+ "No clock is detected on SOSC",
>+ "CM4 is in lockup"};
>+ u32 cause;
>+ int i, bit;
>+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
>+
>+ cause = readl(&src_regs->srsr);
>+ writel(cause, &src_regs->srsr);
>+
>+ for (i = 0; i < 32; i++) {
>+ bit = 1 << i;
>+ if ((cause & bit) == bit) {
>+ if (resetcause[i] != NULL)
>+ return resetcause[i];
>+ }
>+ }
>+
>+ return 0;
>+}
>+
>+#if defined(CONFIG_DISPLAY_CPUINFO)
>+int print_cpuinfo(void)
>+{
>+ u32 cpurev;
>+
>+ cpurev = get_cpu_rev();
>+ printf("CPU: Freescale VyBrid %x family rev%d.%d at %d MHz\n",
>+ (cpurev & 0xFFF000) >> 12,
>+ (cpurev & 0x000F0) >> 4,
>+ (cpurev & 0x0000F) >> 0,
>+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
>+ printf("Reset cause: %s\n", get_reset_cause());
>+ return 0;
>+}
>+#endif
>+
>+int cpu_eth_init(bd_t *bis)
>+{
>+ int rc = -ENODEV;
>+
>+ rc = mcffec_initialize(bis);
>+
>+ return rc;
>+}
>+
>+/* Initializes on-chip MMC controllers.
>+ * to override, implement board_mmc_init()
>+ */
>+int cpu_mmc_init(bd_t *bis)
>+{
>+#ifdef CONFIG_FSL_ESDHC
>+ return fsl_esdhc_mmc_init(bis);
>+#else
>+ return 0;
>+#endif
>+}
>+
>+void reset_cpu(ulong addr)
>+{
>+ __raw_writew(4, WDOG_A5_BASE_ADDR);
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c
>b/arch/arm/cpu/armv7/vybrid-common/speed.c
>new file mode 100644
>index 0000000..3be85ea
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/speed.c
>@@ -0,0 +1,37 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/clock.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+int get_clocks(void)
>+{
>+ gd->bus_clk = vybrid_get_clock(VYBRID_BUS_CLK);
>+ gd->arch.ipg_clk = vybrid_get_clock(VYBRID_IPG_CLK);
>+
>+#ifdef CONFIG_FSL_ESDHC
>+ gd->arch.sdhc_clk = vybrid_get_clock(VYBRID_SDHC_CLK);
>+#endif
>+ return 0;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c
>b/arch/arm/cpu/armv7/vybrid-common/timer.c
>new file mode 100644
>index 0000000..be990e6
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
>@@ -0,0 +1,140 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <div64.h>
>+#include <asm/arch/timer.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/vybrid-regs.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+#define timestamp (gd->arch.tbl)
>+#define timerticks (gd->arch.tbu)
>+#define lastinc (gd->arch.lastinc)
>+static unsigned long ltmstamp;
>+
>+#define CONFIG_TMR_USEPIT
>+#ifdef CONFIG_TMR_USEPIT
>+
The only timer here you are using in the code is the PIT and you did not
Provide the code to support the flex timer, so I suggest remove the above
Code.
>+int timer_init(void)
>+{
>+ ulong usecs;
>+ ulong ticks;
>+
>+ timestamp = 0;
>+
>+ /*
>+ * nsecs conversion = (1/ipg_clk) * 10^9
>+ * equivalent to 1000 / (ipg_clk / 10^6)
>+ */
>+ usecs = (vybrid_get_clock(VYBRID_IPG_CLK) / 1000000);
^ ^
Do you need the parentheses as above?
>+ ticks = 1000 / usecs;
>+
>+ clrbits_le32(PIT_MCR, 2); /* enable PIT */
>+
>+ /* ticks per 10 us = 10000 us / usecs = cycles time */
>+ timerticks = (10 * 1000) / ticks;
>+
>+ __raw_writel(0xFFFFFFFF, PIT_LDVAL1);
>+ __raw_writel(0, PIT_TCTRL1);
>+ __raw_writel(4, PIT_TCTRL1);
>+ __raw_writel(5, PIT_TCTRL1);
>+ __raw_writel(timerticks, PIT_LDVAL0);
>+ __raw_writel(1, PIT_TCTRL0);
>+
>+ lastinc = __raw_readl(PIT_LTMR64H);
>+
>+ return 0;
>+}
>+
>+ulong get_timer(ulong base)
>+{
>+ unsigned long now, diff;
>+
>+ now = __raw_readl(PIT_LTMR64H);
>+ diff = -(now - lastinc);
>+ ltmstamp += diff;
>+ while (ltmstamp > 100) {
>+ timestamp++;
>+ ltmstamp -= 100;
>+ }
>+ lastinc = now;
>+
>+ return timestamp - base;
>+}
>+
>+/* delay x useconds AND preserve advance timstamp value */
>+void __udelay(unsigned long usec)
>+{
>+ ulong nsecs, tmp;
>+
>+ /*
>+ * nsecs conversion = (1/ipg_clk) * 10^9
>+ * equivalent to 1000 / (ipg_clk / 10^6)
>+ */
>+ if (usec < 5)
>+ usec = 10;
>+
>+ nsecs = gd->arch.ipg_clk / 1000000;
>+ nsecs = 1000 / nsecs;
>+
>+ /* 1 us per ticks = 1000 ns / nsecs = cycles time */
>+ while (usec > 0) {
>+ if (usec > 65000)
>+ tmp = 65000;
>+ else
>+ tmp = usec;
>+ usec = usec - tmp;
>+
>+ tmp = (tmp * 1000) / nsecs;
>+
>+ __raw_writel(tmp, PIT_LDVAL2);
>+ __raw_writel(1, PIT_TCTRL2);
>+
>+ while ((__raw_readl(PIT_TFLG2) & 1) != 1)
>+ ;
>+ __raw_writel(0, PIT_TCTRL2);
>+ __raw_writel(1, PIT_TFLG2);
>+ }
u-boot upstream recommend that we use the structure access not the base + offset,
please consider to change to the u-boot upstream style.
For example, we have the following code in the imx:
i = __raw_readl(&cur_gpt->control);
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
>+}
>+#endif /* CONFIG_TMR_USEPIT */
>+
>+/*
>+ * This function is derived from PowerPC code (timebase clock
>frequency).
>+ * On ARM it returns the number of timer ticks per second.
>+ */
>+unsigned long long _usec2ticks(unsigned long long usec)
>+{
>+ return usec;
>+}
>+
>+unsigned long long get_ticks(void)
>+{
>+ return get_timer(0);
>+}
>+
>+ulong get_tbclk(void)
>+{
>+ return CONFIG_SYS_HZ;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/Makefile
>b/arch/arm/cpu/armv7/vybrid/Makefile
>new file mode 100644
>index 0000000..f71e3fb
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/Makefile
>@@ -0,0 +1,45 @@
>+#
>+# Copyright 2012-2013 Freescale Semiconductor, Inc.
>+#
>+# See file CREDITS for list of people who contributed to this
>+# project.
>+#
>+# This program is free software; you can redistribute it and/or
>+# modify it under the terms of the GNU General Public License as
>+# published by the Free Software Foundation; either version 2 of
>+# the License, or (at your option) any later version.
>+#
>+# This program is distributed in the hope that it will be useful,
>+# but WITHOUT ANY WARRANTY; without even the implied warranty of
>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+# GNU General Public License for more details.
>+#
>+# You should have received a copy of the GNU General Public License
>+# along with this program; if not, write to the Free Software
>+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+# MA 02111-1307 USA
>+#
>+
>+include $(TOPDIR)/config.mk
>+
>+LIB = $(obj)lib$(SOC).o
>+
>+COBJS = soc.o clock.o iomux.o
>+SOBJS = lowlevel_init.o
>+
>+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
>+
>+all: $(obj).depend $(LIB)
>+
>+$(LIB): $(OBJS)
>+ $(call cmd_link_o_target, $(OBJS))
>+
>+#######################################################################
>##
>+
>+# defines $(obj).depend target
>+include $(SRCTREE)/rules.mk
>+
>+sinclude $(obj).depend
>+
>+#######################################################################
>##
>diff --git a/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>new file mode 100644
>index 0000000..2951f78
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/asm-offsets.c
>@@ -0,0 +1,70 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
>+ *
>+ * This program is used to generate definitions needed by
>+ * assembly language modules.
>+ *
>+ * We use the technique used in the OSF Mach kernel code:
>+ * generate asm statements containing #defines,
>+ * compile this file to assembler, and then extract the
>+ * #defines from the assembly-language output.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License
>+ * as published by the Free Software Foundation; either version
>+ * 2 of the License, or (at your option) any later version.
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/vybrid-regs.h>
>+
>+#include <linux/kbuild.h>
>+
>+int main(void)
>+{
>+ /* Round up to make sure size gives nice stack alignment */
>+ DEFINE(CLKCTL_CCR, offsetof(struct clkctl, ccr));
>+ DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
>+ DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
>+ DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
>+ DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
>+ DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
>+ DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
>+ DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
>+ DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
>+ DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
>+ DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
>+ DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
>+ DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
>+ DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
>+ DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
>+
>+ DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
>+ DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
>+ DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
>+ DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
>+ DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
>+ DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
>+ DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
>+ DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
>+ DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
>+ DEFINE(CLKCTL_CCGR8, offsetof(struct clkctl, ccgr8));
>+ DEFINE(CLKCTL_CCGR9, offsetof(struct clkctl, ccgr9));
>+ DEFINE(CLKCTL_CCGR10, offsetof(struct clkctl, ccgr10));
>+ DEFINE(CLKCTL_CCGR11, offsetof(struct clkctl, ccgr11));
>+ DEFINE(CLKCTL_CMEOR0, offsetof(struct clkctl, cmeor0));
>+ DEFINE(CLKCTL_CMEOR1, offsetof(struct clkctl, cmeor1));
>+ DEFINE(CLKCTL_CMEOR2, offsetof(struct clkctl, cmeor2));
>+ DEFINE(CLKCTL_CMEOR3, offsetof(struct clkctl, cmeor3));
>+ DEFINE(CLKCTL_CMEOR4, offsetof(struct clkctl, cmeor4));
>+ DEFINE(CLKCTL_CMEOR5, offsetof(struct clkctl, cmeor5));
>+ DEFINE(CLKCTL_CPPDSR, offsetof(struct clkctl, cppdsr));
>+ DEFINE(CLKCTL_CCOWR, offsetof(struct clkctl, ccowr));
>+ DEFINE(CLKCTL_CCPGR0, offsetof(struct clkctl, ccpgr0));
>+ DEFINE(CLKCTL_CCPGR1, offsetof(struct clkctl, ccpgr1));
>+ DEFINE(CLKCTL_CCPGR2, offsetof(struct clkctl, ccpgr2));
>+ DEFINE(CLKCTL_CCPGR3, offsetof(struct clkctl, ccpgr3));
>+
>+ return 0;
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/clock.c
>b/arch/arm/cpu/armv7/vybrid/clock.c
>new file mode 100644
>index 0000000..073b949
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/clock.c
>@@ -0,0 +1,278 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/errno.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <div64.h>
>+
>+DECLARE_GLOBAL_DATA_PTR;
>+
>+enum pll_clocks {
>+ PLL1_CLOCK = 0,
>+ PLL2_CLOCK,
>+ PLL3_CLOCK,
>+ PLL4_CLOCK,
>+ PLL_CLOCKS,
>+};
>+
>+struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+
>+/* Get mcu main rate */
>+static u32 get_mcu_main_clk(void)
>+{
>+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+ u32 ccm_ccsr, ccm_cacrr, armclk_div;
>+ u32 sysclk_sel, pll_pfd_sel = 0;
>+ u32 freq = 0;
>+
>+ ccm_ccsr = readl(&ccm->ccsr);
>+ sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK;
>+ sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET;
>+
>+ ccm_cacrr = readl(&ccm->cacrr);
>+ armclk_div = ccm_cacrr & CCM_CACRR_ARM_CLK_DIV_MASK;
>+ armclk_div >>= CCM_CACRR_ARM_CLK_DIV_OFFSET;
>+ armclk_div += 1;
>+
>+ switch (sysclk_sel) {
>+ case 0:
>+ freq = FASE_CLK_FREQ;
>+ break;
>+ case 1:
>+ freq = SLOW_CLK_FREQ;
>+ break;
>+ case 3:
>+ freq = PLL2_MAIN_FREQ;
>+ break;
>+ case 5:
>+ freq = PLL3_MAIN_FREQ;
>+ break;
>+ case 2:
>+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL2_PFD_CLK_SEL_MASK;
>+ pll_pfd_sel >>= CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET;
>+ break;
>+ case 4:
>+ pll_pfd_sel = ccm_ccsr & CCM_CCSR_PLL1_PFD_CLK_SEL_MASK;
>+ pll_pfd_sel >>= CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET;
>+ break;
>+ default:
>+ printf("unsupported system clock select\n");
>+ }
>+
>+ if (sysclk_sel == 2) {
>+ switch (pll_pfd_sel) {
>+ case 0:
>+ freq = PLL2_MAIN_FREQ;
>+ break;
>+ case 1:
>+ freq = PLL2_PFD1_FREQ;
>+ break;
>+ case 2:
>+ freq = PLL2_PFD2_FREQ;
>+ break;
>+ case 3:
>+ freq = PLL2_PFD3_FREQ;
>+ break;
>+ case 4:
>+ freq = PLL2_PFD4_FREQ;
>+ break;
>+ default:
>+ break;
>+ }
>+ } else if (sysclk_sel == 4) {
>+ switch (pll_pfd_sel) {
>+ case 0:
>+ freq = PLL1_MAIN_FREQ;
>+ break;
>+ case 1:
>+ freq = PLL1_PFD1_FREQ;
>+ break;
>+ case 2:
>+ freq = PLL1_PFD2_FREQ;
>+ break;
>+ case 3:
>+ freq = PLL1_PFD3_FREQ;
>+ break;
>+ case 4:
>+ freq = PLL1_PFD4_FREQ;
>+ break;
>+ default:
>+ break;
>+ }
>+ }
>+
>+ return freq / armclk_div;
>+}
>+
>+/* Get the rate of bus clock */
>+static u32 get_bus_clk(void)
>+{
>+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+ u32 ccm_cacrr, busclk_div;
>+
>+ ccm_cacrr = readl(&ccm->cacrr);
>+
>+ busclk_div = ccm_cacrr & CCM_CACRR_BUS_CLK_DIV_MASK;
>+ busclk_div >>= CCM_CACRR_BUS_CLK_DIV_OFFSET;
>+ busclk_div += 1;
>+
>+ return get_mcu_main_clk() / busclk_div;
>+}
>+
>+/* Get the rate of ipg clock */
>+static u32 get_ipg_clk(void)
>+{
>+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+ u32 ccm_cacrr, ipgclk_div;
>+
>+ ccm_cacrr = readl(&ccm->cacrr);
>+
>+ ipgclk_div = ccm_cacrr & CCM_CACRR_IPG_CLK_DIV_MASK;
>+ ipgclk_div >>= CCM_CACRR_IPG_CLK_DIV_OFFSET;
>+ ipgclk_div += 1;
>+
>+ return get_bus_clk() / ipgclk_div;
>+}
>+
>+/* get dspi clock rate */
>+static u32 vybrid_get_dspiclk(void)
>+{
>+ return get_ipg_clk();
>+}
>+
>+/* The API of get vybrid clocks */
>+unsigned int vybrid_get_clock(enum vybrid_clock clk)
>+{
>+ switch (clk) {
>+ case VYBRID_ARM_CLK:
>+ return get_mcu_main_clk();
>+ case VYBRID_BUS_CLK:
>+ return get_bus_clk();
>+ case VYBRID_IPG_CLK:
>+ return get_ipg_clk();
>+ case VYBRID_UART_CLK:
>+ return vybrid_get_uartclk();
>+ case VYBRID_DSPI_CLK:
>+ return vybrid_get_dspiclk();
>+ case VYBRID_SDHC_CLK:
>+ return vybrid_get_sdhcclk();
>+ case VYBRID_FEC_CLK:
>+ return vybrid_get_fecclk();
>+ default:
>+ break;
>+ }
>+ return -1;
>+}
>+
>+/* Get the rate of uart clk */
>+u32 vybrid_get_uartclk(void)
>+{
>+ return get_ipg_clk();
>+}
>+
>+/* Get the rate of uart clk */
>+u32 vybrid_get_sdhcclk(void)
>+{
>+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+ u32 ccm_cscmr1, ccm_cscdr2, sdhc_clk_sel, sdhc_clk_div;
>+ u32 freq = 0;
>+
>+ ccm_cscmr1 = readl(&ccm->cscmr1);
>+ sdhc_clk_sel = ccm_cscmr1 & CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
>+ sdhc_clk_sel >>= CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
>+
>+ ccm_cscdr2 = readl(&ccm->cscdr2);
>+ sdhc_clk_div = ccm_cscdr2 & CCM_CSCDR2_ESDHC1_CLK_DIV_MASK;
>+ sdhc_clk_div >>= CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET;
>+ sdhc_clk_div += 1;
>+
>+ switch (sdhc_clk_sel) {
>+ case 0:
>+ freq = PLL3_MAIN_FREQ;
>+ break;
>+ case 1:
>+ freq = PLL3_PFD3_FREQ;
>+ break;
>+ case 2:
>+ freq = PLL1_PFD3_FREQ;
>+ break;
>+ case 3:
>+ freq = get_bus_clk();
>+ break;
>+ }
>+
>+ return freq / sdhc_clk_div;
>+}
>+
>+u32 vybrid_get_fecclk(void)
>+{
>+ struct clkctl *ccm = (struct clkctl *)CCM_BASE_ADDR;
>+ u32 ccm_cscmr2, rmii_clk_sel;
>+ u32 freq = 0;
>+
>+ ccm_cscmr2 = readl(&ccm->cscmr2);
>+ rmii_clk_sel = ccm_cscmr2 & CCM_CSCMR2_RMII_CLK_SEL_MASK;
>+ rmii_clk_sel >>= CCM_CSCMR2_RMII_CLK_SEL_OFFSET;
>+
>+ switch (rmii_clk_sel) {
>+ case 0:
>+ freq = ENET_EXTERNAL_CLK;
>+ break;
>+ case 1:
>+ freq = AUDIO_EXTERNAL_CLK;
>+ break;
>+ case 2:
>+ freq = PLL5_MAIN_FREQ;
>+ break;
>+ case 3:
>+ freq = PLL5_MAIN_FREQ / 2;
>+ break;
>+ }
>+
>+ return freq;
>+}
>+
>+/* Dump some core clocks */
>+int do_vybrid_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
>+ char * const argv[])
>+{
>+ printf("\n");
>+ printf("ARM %8d kHz\n",
>+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000);
>+ printf("BUS %8d kHz\n",
>+ vybrid_get_clock(VYBRID_BUS_CLK) / 1000);
>+ printf("IPG %8d kHz\n",
>+ vybrid_get_clock(VYBRID_IPG_CLK) / 1000);
>+
>+ return 0;
>+}
>+
>+/***************************************************/
>+
>+U_BOOT_CMD(
>+ clocks, CONFIG_SYS_MAXARGS, 1, do_vybrid_showclocks,
>+ "display clocks",
>+ ""
>+);
>diff --git a/arch/arm/cpu/armv7/vybrid/iomux.c
>b/arch/arm/cpu/armv7/vybrid/iomux.c
>new file mode 100644
>index 0000000..fb672e3
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/iomux.c
>@@ -0,0 +1,42 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/vybrid-pins.h>
>+#include <asm/arch/iomux.h>
>+#include <asm/arch/sys_proto.h>
>+
>+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio)
>+{
>+ u32 value;
>+
>+ value = (((padio->mod & 7) << 20) | ((padio->spd & 3) << 12) |
> \
>+ ((padio->sre & 1) << 11) | ((padio->ode & 1) << 10) |
> \
>+ ((padio->hys & 1) << 9) | ((padio->dse & 7) << 6) | \
>+ ((padio->pus & 3) << 4) | ((padio->pke & 1) << 3) | \
>+ ((padio->pue & 1) << 2) | ((padio->obe & 1) << 1) | \
>+ ((padio->ibe & 1) << 0));
>+
>+ __raw_writel(pad_addr, value);
Is this correct? __raw_writel should be (v, a), but you are opposite?
>+}
>diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>new file mode 100644
>index 0000000..c2bda4f
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
>@@ -0,0 +1,128 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <config.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <generated/asm-offsets.h>
>+
>+/* DDR */
>+.macro init_drive_strength
>+.endm /* init_drive_strength */
>+
>+.macro setup_pll pll, freq
>+.endm
>+
>+.macro init_clock
>+ ldr r0, =CCM_BASE_ADDR
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CLPCR
>+ str r1, [r0, #CLKCTL_CLPCR]
>+
>+ /* Gate of clocks to the peripherals first */
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR0
>+ str r1, [r0, #CLKCTL_CCGR0]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR1
>+ str r1, [r0, #CLKCTL_CCGR1]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR2
>+ str r1, [r0, #CLKCTL_CCGR2]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR3
>+ str r1, [r0, #CLKCTL_CCGR3]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR4
>+ str r1, [r0, #CLKCTL_CCGR4]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR5
>+ str r1, [r0, #CLKCTL_CCGR5]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR6
>+ str r1, [r0, #CLKCTL_CCGR6]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR7
>+ str r1, [r0, #CLKCTL_CCGR7]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR8
>+ str r1, [r0, #CLKCTL_CCGR8]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR9
>+ str r1, [r0, #CLKCTL_CCGR9]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR10
>+ str r1, [r0, #CLKCTL_CCGR10]
>+ ldr r1, =CONFIG_SYS_CLKCTL_CCGR11
>+ str r1, [r0, #CLKCTL_CCGR11]
>+
>+ ldr r2, =ANATOP_BASE_ADDR
>+ ldr r1, =CONFIG_SYS_ANADIG_528_CTRL
>+ str r1, [r2, #0x30]
>+ ldr r1, =CONFIG_SYS_ANADIG_ENET_CTRL
>+ str r1, [r2, #0xE0]
>+ ldr r1, =CONFIG_SYS_ANADIG_SYS_CTRL
>+ str r1, [r2, #0x270]
>+ /* check for lock */
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CCR
>+ str r1, [r0, #CLKCTL_CCR]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CCSR
>+ str r1, [r0, #CLKCTL_CCSR]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CACRR
>+ str r1, [r0, #CLKCTL_CACRR]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR1
>+ str r1, [r0, #CLKCTL_CSCMR1]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR1
>+ str r1, [r0, #CLKCTL_CSCDR1]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR2
>+ str r1, [r0, #CLKCTL_CSCDR2]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR3
>+ str r1, [r0, #CLKCTL_CSCDR3]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCMR2
>+ str r1, [r0, #CLKCTL_CSCMR2]
>+
>+ ldr r1, =CONFIG_SYS_CLKCTRL_CSCDR4
>+ str r1, [r0, #CLKCTL_CSCDR4]
>+.endm
>+
>+.macro setup_wdog
>+ ldr r0, =WDOG_A5_BASE_ADDR
>+ mov r1, #0x30
>+ strh r1, [r0]
>+.endm
What the code does here, disable-wdog, right?
IMHO,
- We can't disable the WDG if it already enabled.
- The macro name, setup_wdog will confuse others, since the reader may guess
Will setup(enable) the WDG.
But I guess this code is useless, you can remove it.
>+
>+.section ".text.init", "x"
>+
>+.globl lowlevel_init
>+lowlevel_init:
>+ /* ARM errata ID #468414 */
>+ mrc 15, 0, r1, c1, c0, 1
>+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
>+ mcr 15, 0, r1, c1, c0, 1
>+
Does this errata applied to A5 too?
>+#ifndef CONFIG_SYS_BOOTHDR
>+ init_clock
>+#endif
>+
>+ /* r12 saved upper lr*/
>+ mov pc,lr
>+
>+/* Board level setting value */
>+DDR_PERCHARGE_CMD: .word 0x04008008
>+DDR_REFRESH_CMD: .word 0x00008010
>+DDR_LMR1_W: .word 0x00338018
>+DDR_LMR_CMD: .word 0xB2220000
>+DDR_TIMING_W: .word 0xB02567A9
>+DDR_MISC_W: .word 0x000A0104
>diff --git a/arch/arm/cpu/armv7/vybrid/soc.c
>b/arch/arm/cpu/armv7/vybrid/soc.c
>new file mode 100644
>index 0000000..e73d6c4
>--- /dev/null
>+++ b/arch/arm/cpu/armv7/vybrid/soc.c
>@@ -0,0 +1,42 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <common.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/clock.h>
>+#include <asm/arch/sys_proto.h>
>+
>+#include <asm/errno.h>
>+#include <asm/io.h>
>+
>+#if !(defined(CONFIG_VYBRID))
>+#error "CPU_TYPE not defined"
>+#endif
>+
>+u32 get_cpu_rev(void)
>+{
>+ int system_rev = 0x600000;
What's the hard code 0x600000 means?
>+ int reg = __raw_readl(ROM_SI_REV);
>+
>+ system_rev |= reg;
>+ return system_rev;
>+}
>diff --git a/arch/arm/include/asm/arch-vybrid/clock.h
>b/arch/arm/include/asm/arch-vybrid/clock.h
>new file mode 100644
>index 0000000..bf95b13
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/clock.h
>@@ -0,0 +1,41 @@
>+/*
>+ * Copyright 2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_CLOCK_H
>+#define __ASM_ARCH_CLOCK_H
>+
>+enum vybrid_clock {
>+ VYBRID_ARM_CLK = 0,
>+ VYBRID_BUS_CLK,
>+ VYBRID_IPG_CLK,
>+ VYBRID_UART_CLK,
>+ VYBRID_DSPI_CLK,
>+ VYBRID_SDHC_CLK,
>+ VYBRID_FEC_CLK,
>+};
>+
>+u32 vybrid_get_uartclk(void);
>+u32 vybrid_get_sdhcclk(void);
>+u32 vybrid_get_fecclk(void);
>+unsigned int vybrid_get_clock(enum vybrid_clock clk);
>+
>+#endif /* __ASM_ARCH_CLOCK_H */
>diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h
>b/arch/arm/include/asm/arch-vybrid/iomux.h
>new file mode 100644
>index 0000000..94f8b0b
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/iomux.h
>@@ -0,0 +1,323 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __MACH_VYBRID_IOMUX_H__
>+#define __MACH_VYBRID_IOMUX_H__
>+
>+#include <common.h>
>+#include <asm/io.h>
>+#include <asm/arch/vybrid-regs.h>
>+#include <asm/arch/vybrid-pins.h>
>+
>+#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000)
>+#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004)
>+#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008)
>+#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C)
>+#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010)
>+#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014)
>+#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018)
>+#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C)
>+#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020)
>+#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024)
>+#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028)
>+#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C)
>+#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030)
>+#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034)
>+#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038)
>+#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C)
>+#define IOMUXC_PAD_016 (IOMUXC_BASE_ADDR + 0x0040)
>+#define IOMUXC_PAD_017 (IOMUXC_BASE_ADDR + 0x0044)
>+#define IOMUXC_PAD_018 (IOMUXC_BASE_ADDR + 0x0048)
>+#define IOMUXC_PAD_019 (IOMUXC_BASE_ADDR + 0x004C)
>+#define IOMUXC_PAD_020 (IOMUXC_BASE_ADDR + 0x0050)
>+#define IOMUXC_PAD_021 (IOMUXC_BASE_ADDR + 0x0054)
>+#define IOMUXC_PAD_022 (IOMUXC_BASE_ADDR + 0x0058)
>+#define IOMUXC_PAD_023 (IOMUXC_BASE_ADDR + 0x005C)
>+#define IOMUXC_PAD_024 (IOMUXC_BASE_ADDR + 0x0060)
>+#define IOMUXC_PAD_025 (IOMUXC_BASE_ADDR + 0x0064)
>+#define IOMUXC_PAD_026 (IOMUXC_BASE_ADDR + 0x0068)
>+#define IOMUXC_PAD_027 (IOMUXC_BASE_ADDR + 0x006C)
>+#define IOMUXC_PAD_028 (IOMUXC_BASE_ADDR + 0x0070)
>+#define IOMUXC_PAD_029 (IOMUXC_BASE_ADDR + 0x0074)
>+#define IOMUXC_PAD_030 (IOMUXC_BASE_ADDR + 0x0078)
>+#define IOMUXC_PAD_031 (IOMUXC_BASE_ADDR + 0x007C)
>+#define IOMUXC_PAD_032 (IOMUXC_BASE_ADDR + 0x0080)
>+#define IOMUXC_PAD_033 (IOMUXC_BASE_ADDR + 0x0084)
>+#define IOMUXC_PAD_034 (IOMUXC_BASE_ADDR + 0x0088)
>+#define IOMUXC_PAD_035 (IOMUXC_BASE_ADDR + 0x008C)
>+#define IOMUXC_PAD_036 (IOMUXC_BASE_ADDR + 0x0090)
>+#define IOMUXC_PAD_037 (IOMUXC_BASE_ADDR + 0x0094)
>+#define IOMUXC_PAD_038 (IOMUXC_BASE_ADDR + 0x0098)
>+#define IOMUXC_PAD_039 (IOMUXC_BASE_ADDR + 0x009C)
>+#define IOMUXC_PAD_040 (IOMUXC_BASE_ADDR + 0x00A0)
>+#define IOMUXC_PAD_041 (IOMUXC_BASE_ADDR + 0x00A4)
>+#define IOMUXC_PAD_042 (IOMUXC_BASE_ADDR + 0x00A8)
>+#define IOMUXC_PAD_043 (IOMUXC_BASE_ADDR + 0x00AC)
>+#define IOMUXC_PAD_044 (IOMUXC_BASE_ADDR + 0x00B0)
>+#define IOMUXC_PAD_045 (IOMUXC_BASE_ADDR + 0x00B4)
>+#define IOMUXC_PAD_046 (IOMUXC_BASE_ADDR + 0x00B8)
>+#define IOMUXC_PAD_047 (IOMUXC_BASE_ADDR + 0x00BC)
>+#define IOMUXC_PAD_048 (IOMUXC_BASE_ADDR + 0x00C0)
>+#define IOMUXC_PAD_049 (IOMUXC_BASE_ADDR + 0x00C4)
>+#define IOMUXC_PAD_050 (IOMUXC_BASE_ADDR + 0x00C8)
>+#define IOMUXC_PAD_051 (IOMUXC_BASE_ADDR + 0x00CC)
>+#define IOMUXC_PAD_052 (IOMUXC_BASE_ADDR + 0x00D0)
>+#define IOMUXC_PAD_053 (IOMUXC_BASE_ADDR + 0x00D4)
>+#define IOMUXC_PAD_054 (IOMUXC_BASE_ADDR + 0x00D8)
>+#define IOMUXC_PAD_055 (IOMUXC_BASE_ADDR + 0x00DC)
>+#define IOMUXC_PAD_056 (IOMUXC_BASE_ADDR + 0x00E0)
>+#define IOMUXC_PAD_057 (IOMUXC_BASE_ADDR + 0x00E4)
>+#define IOMUXC_PAD_058 (IOMUXC_BASE_ADDR + 0x00E8)
>+#define IOMUXC_PAD_059 (IOMUXC_BASE_ADDR + 0x00EC)
>+#define IOMUXC_PAD_060 (IOMUXC_BASE_ADDR + 0x00F0)
>+#define IOMUXC_PAD_061 (IOMUXC_BASE_ADDR + 0x00F4)
>+#define IOMUXC_PAD_062 (IOMUXC_BASE_ADDR + 0x00F8)
>+#define IOMUXC_PAD_063 (IOMUXC_BASE_ADDR + 0x00FC)
>+#define IOMUXC_PAD_064 (IOMUXC_BASE_ADDR + 0x0100)
>+#define IOMUXC_PAD_065 (IOMUXC_BASE_ADDR + 0x0104)
>+#define IOMUXC_PAD_066 (IOMUXC_BASE_ADDR + 0x0108)
>+#define IOMUXC_PAD_067 (IOMUXC_BASE_ADDR + 0x010C)
>+#define IOMUXC_PAD_068 (IOMUXC_BASE_ADDR + 0x0110)
>+#define IOMUXC_PAD_069 (IOMUXC_BASE_ADDR + 0x0114)
>+#define IOMUXC_PAD_070 (IOMUXC_BASE_ADDR + 0x0118)
>+#define IOMUXC_PAD_071 (IOMUXC_BASE_ADDR + 0x011C)
>+#define IOMUXC_PAD_072 (IOMUXC_BASE_ADDR + 0x0120)
>+#define IOMUXC_PAD_073 (IOMUXC_BASE_ADDR + 0x0124)
>+#define IOMUXC_PAD_074 (IOMUXC_BASE_ADDR + 0x0128)
>+#define IOMUXC_PAD_075 (IOMUXC_BASE_ADDR + 0x012C)
>+#define IOMUXC_PAD_076 (IOMUXC_BASE_ADDR + 0x0130)
>+#define IOMUXC_PAD_077 (IOMUXC_BASE_ADDR + 0x0134)
>+#define IOMUXC_PAD_078 (IOMUXC_BASE_ADDR + 0x0138)
>+#define IOMUXC_PAD_079 (IOMUXC_BASE_ADDR + 0x013C)
>+#define IOMUXC_PAD_080 (IOMUXC_BASE_ADDR + 0x0140)
>+#define IOMUXC_PAD_081 (IOMUXC_BASE_ADDR + 0x0144)
>+#define IOMUXC_PAD_082 (IOMUXC_BASE_ADDR + 0x0148)
>+#define IOMUXC_PAD_083 (IOMUXC_BASE_ADDR + 0x014C)
>+#define IOMUXC_PAD_084 (IOMUXC_BASE_ADDR + 0x0150)
>+#define IOMUXC_PAD_085 (IOMUXC_BASE_ADDR + 0x0154)
>+#define IOMUXC_PAD_086 (IOMUXC_BASE_ADDR + 0x0158)
>+#define IOMUXC_PAD_087 (IOMUXC_BASE_ADDR + 0x015C)
>+#define IOMUXC_PAD_088 (IOMUXC_BASE_ADDR + 0x0160)
>+#define IOMUXC_PAD_089 (IOMUXC_BASE_ADDR + 0x0164)
>+#define IOMUXC_PAD_090 (IOMUXC_BASE_ADDR + 0x0168)
>+#define IOMUXC_PAD_091 (IOMUXC_BASE_ADDR + 0x016C)
>+#define IOMUXC_PAD_092 (IOMUXC_BASE_ADDR + 0x0170)
>+#define IOMUXC_PAD_093 (IOMUXC_BASE_ADDR + 0x0174)
>+#define IOMUXC_PAD_094 (IOMUXC_BASE_ADDR + 0x0178)
>+#define IOMUXC_PAD_095 (IOMUXC_BASE_ADDR + 0x017C)
>+#define IOMUXC_PAD_096 (IOMUXC_BASE_ADDR + 0x0180)
>+#define IOMUXC_PAD_097 (IOMUXC_BASE_ADDR + 0x0184)
>+#define IOMUXC_PAD_098 (IOMUXC_BASE_ADDR + 0x0188)
>+#define IOMUXC_PAD_099 (IOMUXC_BASE_ADDR + 0x018C)
>+#define IOMUXC_PAD_100 (IOMUXC_BASE_ADDR + 0x0190)
>+#define IOMUXC_PAD_101 (IOMUXC_BASE_ADDR + 0x0194)
>+#define IOMUXC_PAD_102 (IOMUXC_BASE_ADDR + 0x0198)
>+#define IOMUXC_PAD_103 (IOMUXC_BASE_ADDR + 0x019C)
>+#define IOMUXC_PAD_104 (IOMUXC_BASE_ADDR + 0x01A0)
>+#define IOMUXC_PAD_105 (IOMUXC_BASE_ADDR + 0x01A4)
>+#define IOMUXC_PAD_106 (IOMUXC_BASE_ADDR + 0x01A8)
>+#define IOMUXC_PAD_107 (IOMUXC_BASE_ADDR + 0x01AC)
>+#define IOMUXC_PAD_108 (IOMUXC_BASE_ADDR + 0x01B0)
>+#define IOMUXC_PAD_109 (IOMUXC_BASE_ADDR + 0x01B4)
>+#define IOMUXC_PAD_110 (IOMUXC_BASE_ADDR + 0x01B8)
>+#define IOMUXC_PAD_111 (IOMUXC_BASE_ADDR + 0x01BC)
>+#define IOMUXC_PAD_112 (IOMUXC_BASE_ADDR + 0x01C0)
>+#define IOMUXC_PAD_113 (IOMUXC_BASE_ADDR + 0x01C4)
>+#define IOMUXC_PAD_114 (IOMUXC_BASE_ADDR + 0x01C8)
>+#define IOMUXC_PAD_115 (IOMUXC_BASE_ADDR + 0x01CC)
>+#define IOMUXC_PAD_116 (IOMUXC_BASE_ADDR + 0x01D0)
>+#define IOMUXC_PAD_117 (IOMUXC_BASE_ADDR + 0x01D4)
>+#define IOMUXC_PAD_118 (IOMUXC_BASE_ADDR + 0x01D8)
>+#define IOMUXC_PAD_119 (IOMUXC_BASE_ADDR + 0x01DC)
>+#define IOMUXC_PAD_120 (IOMUXC_BASE_ADDR + 0x01E0)
>+#define IOMUXC_PAD_121 (IOMUXC_BASE_ADDR + 0x01E4)
>+#define IOMUXC_PAD_122 (IOMUXC_BASE_ADDR + 0x01E8)
>+#define IOMUXC_PAD_123 (IOMUXC_BASE_ADDR + 0x01EC)
>+#define IOMUXC_PAD_124 (IOMUXC_BASE_ADDR + 0x01F0)
>+#define IOMUXC_PAD_125 (IOMUXC_BASE_ADDR + 0x01F4)
>+#define IOMUXC_PAD_126 (IOMUXC_BASE_ADDR + 0x01F8)
>+#define IOMUXC_PAD_127 (IOMUXC_BASE_ADDR + 0x01FC)
>+#define IOMUXC_PAD_128 (IOMUXC_BASE_ADDR + 0x0200)
>+#define IOMUXC_PAD_129 (IOMUXC_BASE_ADDR + 0x0204)
>+#define IOMUXC_PAD_130 (IOMUXC_BASE_ADDR + 0x0208)
>+#define IOMUXC_PAD_131 (IOMUXC_BASE_ADDR + 0x020C)
>+#define IOMUXC_PAD_132 (IOMUXC_BASE_ADDR + 0x0210)
>+#define IOMUXC_PAD_133 (IOMUXC_BASE_ADDR + 0x0214)
>+#define IOMUXC_PAD_134 (IOMUXC_BASE_ADDR + 0x0218)
>+
>+#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C)
>+#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220)
>+#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224)
>+#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228)
>+#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C)
>+#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230)
>+#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234)
>+#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238)
>+#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C)
>+#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240)
>+#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244)
>+#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248)
>+#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C)
>+#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250)
>+#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254)
>+#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258)
>+#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C)
>+
>+#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260)
>+#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264)
>+#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268)
>+
>+#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C)
>+
>+#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270)
>+
>+#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274)
>+
>+#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278)
>+
>+#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C)
>+#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280)
>+#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284)
>+#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288)
>+#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C)
>+#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290)
>+#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294)
>+#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298)
>+#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C)
>+#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0)
>+#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4)
>+#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8)
>+#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC)
>+#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0)
>+#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4)
>+#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8)
>+
>+#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC)
>+#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0)
>+
>+#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4)
>+#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8)
>+
>+#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC)
>+#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0)
>+
>+#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4)
>+#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8)
>+
>+#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC)
>+#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0)
>+
>+#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4)
>+#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8)
>+
>+#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC)
>+#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0)
>+#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4)
>+
>+struct pad_iomux {
>+ u8 mod;
>+ u8 spd;
>+ u8 sre;
>+ u8 ode;
>+ u8 hys;
>+ u8 dse;
>+ u8 pus;
>+ u8 pke;
>+ u8 pue;
>+ u8 obe;
>+ u8 ibe;
>+};
>+
>+#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, \
>+ dse, pus, pke, pue, obe, ibe) \
>+ (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \
>+ ((sre & 1) << 11) | ((ode & 1) << 10) | \
>+ ((hys & 1) << 9) | ((dse & 7) << 6) | \
>+ ((pus & 3) << 4) | ((pke & 1) << 3) | \
>+ ((pue & 1) << 2) | ((obe & 1) << 1) | \
>+ (ibe & 1)))
>+
>+#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \
>+ (((inp & 1) << 16) | ((trim & 3) << 14) | \
>+ ((hys & 1) << 9) | ((dse & 7) << 6) | \
>+ ((pus & 3) << 4) | ((pke & 1) << 3) | \
>+ ((pue & 1) << 2))
>+
>+#define MUX_MODE_ALT0 0x00
>+#define MUX_MODE_ALT1 0x01
>+#define MUX_MODE_ALT2 0x02
>+#define MUX_MODE_ALT3 0x03
>+#define MUX_MODE_ALT4 0x04
>+#define MUX_MODE_ALT5 0x05
>+#define MUX_MODE_ALT6 0x06
>+#define MUX_MODE_ALT7 0x07
>+
>+#define MUX_SPD_50MHZ 0x00
>+#define MUX_SPD_100MHZ 0x02
>+#define MUX_SPD_200MHZ 0x03
>+
>+#define MUX_SRE_SLOW 0
>+#define MUX_SRE_FAST 1
>+
>+#define MUX_ODE_CMOS 0
>+#define MUX_ODE_OPEN 1
>+
>+#define MUX_HYS_CMOS 0
>+#define MUX_HYS_SCHMITT 1
>+
>+#define MUX_DSE_20_OHM 7
>+#define MUX_DSE_25_OHM 6
>+#define MUX_DSE_30_OHM 5
>+#define MUX_DSE_37_OHM 4
>+#define MUX_DSE_50_OHM 3
>+#define MUX_DSE_75_OHM 2
>+#define MUX_DSE_150_OHM 1
>+#define MUX_DSE_DIS 0
>+
>+#define MUX_PUS_22KOHM_UP 3
>+#define MUX_PUS_100KOHM_UP 2
>+#define MUX_PUS_47KOHM_UP 1
>+#define MUX_PUS_100KOHM_DN 0
>+
>+#define MUX_PKE_EN 1
>+#define MUX_PKE_DIS 0
>+
>+#define MUX_PUE_PULLEN 1
>+#define MUX_PUE_KEEPEREN 0
>+
>+#define MUX_OBE_EN 1
>+#define MUX_OBE_DIS 0
>+
>+#define MUX_IBE_EN 1
>+#define MUX_IBE_DIS 0
>+
>+#define MUX_DDR_INPUT_DIFF 1
>+#define MUX_DDR_INPUT_CMOS 0
>+
>+#define MUX_DDR_TRIM_150PS 3
>+#define MUX_DDR_TRIM_100PS 2
>+#define MUX_DDR_TRIM_50PS 1
>+#define MUX_DDR_TRIM_MIN 0
>+
>+void pad_iomux_set(u32 pad_addr, struct pad_iomux *padio);
>+
>+#endif /* __MACH_VYBRID_IOMUX_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>new file mode 100644
>index 0000000..9575f73
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/serial-vybrid.h
>@@ -0,0 +1,213 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __SERIAL_VYBRID_H__
>+#define __SERIAL_VYBRID_H__
>+
>+#define UBDH 0x00
>+#define UBDL 0x01
>+#define UC1 0x02
>+#define UC2 0x03
>+#define US1 0x04
>+#define US2 0x05
>+#define UC3 0x06
>+#define UD 0x07
>+#define UMA1 0x08
>+#define UMA2 0x09
>+#define UC4 0x0A
>+#define UC5 0x0B
>+#define UED 0x0C
>+#define UMODEM 0x0D
>+#define UIR 0x0E
>+#define UPFIFO 0x10
>+#define UCFIFO 0x11
>+#define USFIFO 0x12
>+#define UTWFIFO 0x13
>+#define UTCFIFO 0x14
>+#define URWFIFO 0x15
>+#define URCFIFO 0x16
>+#define UC7816 0x18
>+#define UIE7816 0x19
>+#define UIS7816 0x1A
>+#define UWP7816T0 0x1B
>+#define UWP7816T1 0x1B
>+#define UWN7816 0x1C
>+#define UWF7816 0x1D
>+#define UET78416 0x1E
>+#define UTL7816 0x1F
>+#define UC6 0x21
>+#define UPCTH 0x22
>+#define UPCTL 0x23
>+#define UB1T 0x24
>+#define USDTH 0x25
>+#define USDTL 0x26
>+#define UPRE 0x27
>+#define UTPL 0x28
>+#define UIE 0x29
>+#define UWB 0x2A
>+#define US3 0x2B
>+#define US4 0x2C
>+#define UPRL 0x2D
>+#define URPREL 0x2E
>+#define UCPW 0x2F
>+#define URIDT 0x30
>+#define UTIDT 0x31
>+
>+#define UBDH_LBKDIE (1 << 7)
>+#define UBDH_RXEDGIE (1 << 6)
>+#define UBDH_SBR(x) (x & 0x1F)
>+
>+#define UC1_LOOPS (1 << 7)
>+#define UC1_SWAI (1 << 6)
>+#define UC1_RSRC (1 << 5)
>+#define UC1_M (1 << 4)
>+#define UC1_WAKE (1 << 3)
>+#define UC1_ILT (1 << 2)
>+#define UC1_PE (1 << 1)
>+#define UC1_PT (1 << 0)
>+
>+#define UC2_TIE (1 << 7)
>+#define UC2_TCIE (1 << 6)
>+#define UC2_RIE (1 << 5)
>+#define UC2_ILIE (1 << 4)
>+#define UC2_TE (1 << 3)
>+#define UC2_RE (1 << 2)
>+#define UC2_RWU (1 << 1)
>+#define UC2_SBK (1 << 0)
>+
>+#define US1_TDRE (1 << 7)
>+#define US1_TC (1 << 6)
>+#define US1_RDRF (1 << 5)
>+#define US1_IDLE (1 << 4)
>+#define US1_OR (1 << 3)
>+#define US1_NF (1 << 2)
>+#define US1_FE (1 << 1)
>+#define US1_PF (1 << 0)
>+
>+#define US2_LBKDIF (1 << 7)
>+#define US2_RXEDGIF (1 << 6)
>+#define US2_MSBF (1 << 5)
>+#define US2_RXINV (1 << 4)
>+#define US2_RWUID (1 << 3)
>+#define US2_BRK13 (1 << 2)
>+#define US2_RBKDE (1 << 1)
>+#define US2_RAF (1 << 0)
>+
>+#define UC3_R8 (1 << 7)
>+#define UC3_T8 (1 << 6)
>+#define UC3_TXDIR (1 << 5)
>+#define UC3_TXINV (1 << 4)
>+#define UC3_ORIE (1 << 3)
>+#define UC3_NEIF (1 << 2)
>+#define UC3_FEIF (1 << 1)
>+#define UC3_PEIE (1 << 0)
>+
>+#define UC4_MAEN1 (1 << 7)
>+#define UC4_MAEN2 (1 << 6)
>+#define UC4_M10 (1 << 5)
>+#define UC4_BRFA(x) (x & 0x1F)
>+
>+#define UC5_TDMAS (1 << 7)
>+#define UC5_RDMAS (1 << 5)
>+
>+#define UED_NOISY (1 << 7)
>+#define UED_PARITYE (1 << 6)
>+
>+#define UMODEM_RXRTSE (1 << 3)
>+#define UMODEM_TXRTSPOL (1 << 2)
>+#define UMODEM_TXRTSE (1 << 1)
>+#define UMODEM_TXCTSE (1 << 0)
>+
>+#define UIR_IREN (1 << 2)
>+#define UIR_TNP(x) (x & 3)
>+
>+#define UPFIFO_TXFE (1 << 7)
>+#define UPFIFO_TXFSZ(x) ((x & 7) << 4)
>+#define UPFIFO_RXFE (1 << 3)
>+#define UPFIFO_RXFSZ(x) ((x & 7) << 0)
>+
>+#define UCFIFO_TXFLUSH (1 << 7)
>+#define UCFIFO_RXFLUSH (1 << 6)
>+#define UCFIFO_TXOFE (1 << 1)
>+#define UCFIFO_RXUFE (1 << 0)
>+
>+#define USFIFO_TXEMPT (1 << 7)
>+#define USFIFO_RXEMPT (1 << 6)
>+#define USFIFO_TXOF (1 << 1)
>+#define USFIFO_RXUF (1 << 0)
>+
>+#define UC7816_ONACK (1 << 4)
>+#define UC7816_ANACK (1 << 3)
>+#define UC7816_INIT (1 << 2)
>+#define UC7816_TTYPE (1 << 1)
>+#define UC7816_7816E (1 << 0)
>+
>+#define UIE7816_WTE (1 << 7)
>+#define UIE7816_CWTE (1 << 6)
>+#define UIE7816_BWTE (1 << 5)
>+#define UIE7816_INITDE (1 << 4)
>+#define UIE7816_GTVE (1 << 2)
>+#define UIE7816_TXTE (1 << 1)
>+#define UIE7816_RXTE (1 << 0)
>+
>+#define UIS7816_WTE (1 << 7)
>+#define UIS7816_CWTE (1 << 6)
>+#define UIS7816_BWTE (1 << 5)
>+#define UIS7816_INITDE (1 << 4)
>+#define UIS7816_GTVE (1 << 2)
>+#define UIS7816_TXTE (1 << 1)
>+#define UIS7816_RXTE (1 << 0)
>+
>+#define UWP7816T1_CWI(x) ((x & 0xf) << 4)
>+#define UWP7816T1_BWI(x) ((x & 0xf) << 0)
>+
>+#define UET78416_TXTHRESHOLD(x) ((x & 0xf) << 4)
>+#define UET78416_RXTHRESHOLD(x) ((x & 0xf) << 0)
>+
>+#define UC6_EN709 (1 << 7)
>+#define UC6_TX709 (1 << 6)
>+#define UC6_CE (1 << 5)
>+#define UC6_CP (1 << 4)
>+
>+#define UIE_WBEIE (1 << 6)
>+#define UIE_ISDIE (1 << 5)
>+#define UIE_PRXIE (1 << 4)
>+#define UIE_PTXIE (1 << 3)
>+#define UIE_PCTEIE (1 << 2)
>+#define UIE_PSIE (1 << 1)
>+#define UIE_TXFIE (1 << 0)
>+
>+#define US3_PEF (1 << 7)
>+#define US3_WBEF (1 << 6)
>+#define US3_ISD (1 << 5)
>+#define US3_PRXF (1 << 4)
>+#define US3_PTXF (1 << 3)
>+#define US3_PCTEF (1 << 2)
>+#define US3_PSF (1 << 1)
>+#define US3_TXFF (1 << 0)
>+
>+#define US4_INITF (1 << 4)
>+#define US4_CDET(x) ((x & 3) << 2)
>+#define US4_ILCV (1 << 1)
>+#define US4_FE (1 << 0)
>+
>+#endif /* __SERIAL_VYBRID_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/sys_proto.h
>b/arch/arm/include/asm/arch-vybrid/sys_proto.h
>new file mode 100644
>index 0000000..7e2de97
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/sys_proto.h
>@@ -0,0 +1,30 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef _SYS_PROTO_H_
>+#define _SYS_PROTO_H_
>+
>+u32 get_cpu_rev(void);
>+#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
>+void sdelay(unsigned long);
>+
>+#endif
>diff --git a/arch/arm/include/asm/arch-vybrid/timer.h
>b/arch/arm/include/asm/arch-vybrid/timer.h
>new file mode 100644
>index 0000000..55497e3
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/timer.h
>@@ -0,0 +1,405 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_TIMER_H
>+#define __ASM_ARCH_TIMER_H
>+
>+struct ftm_regs {
>+ u32 sc; /* 0x00 */
>+ u32 cnt; /* 0x04 */
>+ u32 mod; /* 0x08 */
>+ u32 c0sc; /* 0x0C */
>+ u32 c0v; /* 0x10 */
>+ u32 c1sc; /* 0x14 */
>+ u32 c1v; /* 0x18 */
>+ u32 c2sc; /* 0x1C */
>+ u32 c2v; /* 0x20 */
>+ u32 c3sc; /* 0x24 */
>+ u32 c3v; /* 0x28 */
>+ u32 c4sc; /* 0x2C */
>+ u32 c4v; /* 0x30 */
>+ u32 c5sc; /* 0x34 */
>+ u32 c5v; /* 0x38 */
>+ u32 c6sc; /* 0x3C */
>+ u32 c6v; /* 0x40 */
>+ u32 c7sc; /* 0x44 */
>+ u32 c7v; /* 0x48 */
>+ u32 cntin; /* 0x4C */
>+ u32 status; /* 0x50 */
>+ u32 mode; /* 0x54 */
>+ u32 sync; /* 0x58 */
>+ u32 outinit; /* 0x5C */
>+ u32 outmask; /* 0x60 */
>+ u32 combine; /* 0x64 */
>+ u32 deadtime; /* 0x68 */
>+ u32 exttrig; /* 0x6C */
>+ u32 pol; /* 0x70 */
>+ u32 fms; /* 0x74 */
>+ u32 filter; /* 0x78 */
>+ u32 fltctrl; /* 0x7C */
>+ u32 qdctrl; /* 0x80 */
>+ u32 conf; /* 0x84 */
>+ u32 fltpol; /* 0x88 */
>+ u32 synconf; /* 0x8C */
>+ u32 invctrl; /* 0x90 */
>+ u32 swoctrl; /* 0x94 */
>+ u32 pwmload; /* 0x98 */
>+};
>+
>+struct pit2_regs {
>+ u32 ldval; /* 0x00 */
>+ u32 cval; /* 0x04 */
>+ u32 tctrl; /* 0x08 */
>+ u32 tflg; /* 0x0C */
>+};
>+
>+struct pit_regs {
>+ u32 mcr; /* 0x00 */
>+ u32 rsvd0[55];
>+ u32 ltmr64h; /* 0xE0 */
>+ u32 ltmr64l; /* 0xE4 */
>+ u32 rsvd1[6];
>+ struct pit2_regs counter[8]; /* 0x100 */
>+};
>+
>+struct lptmr_regs {
>+ u32 csr; /* 0x00 */
>+ u32 psr; /* 0x04 */
>+ u32 cmr; /* 0x08 */
>+ u32 cnr; /* 0x0C */
>+};
>+
>+/* Flex Timer */
>+#define FTM_SC (FTM_BASE_ADDR + 0x00)
>+#define FTM_CNT (FTM_BASE_ADDR + 0x04)
>+#define FTM_MOD (FTM_BASE_ADDR + 0x08)
>+#define FTM_C0SC (FTM_BASE_ADDR + 0x0C)
>+#define FTM_C0V (FTM_BASE_ADDR + 0x10)
>+#define FTM_C1SC (FTM_BASE_ADDR + 0x14)
>+#define FTM_C1V (FTM_BASE_ADDR + 0x18)
>+#define FTM_C2SC (FTM_BASE_ADDR + 0x1C)
>+#define FTM_C2V (FTM_BASE_ADDR + 0x20)
>+#define FTM_C3SC (FTM_BASE_ADDR + 0x24)
>+#define FTM_C3V (FTM_BASE_ADDR + 0x28)
>+#define FTM_C4SC (FTM_BASE_ADDR + 0x2C)
>+#define FTM_C4V (FTM_BASE_ADDR + 0x30)
>+#define FTM_C5SC (FTM_BASE_ADDR + 0x34)
>+#define FTM_C5V (FTM_BASE_ADDR + 0x38)
>+#define FTM_C6SC (FTM_BASE_ADDR + 0x3C)
>+#define FTM_C6V (FTM_BASE_ADDR + 0x40)
>+#define FTM_C7SC (FTM_BASE_ADDR + 0x44)
>+#define FTM_C7V (FTM_BASE_ADDR + 0x48)
>+#define FTM_CNTIN (FTM_BASE_ADDR + 0x4C)
>+#define FTM_STATUS (FTM_BASE_ADDR + 0x50)
>+#define FTM_MODE (FTM_BASE_ADDR + 0x54)
>+#define FTM_SYNC (FTM_BASE_ADDR + 0x58)
>+#define FTM_OUTINIT (FTM_BASE_ADDR + 0x5C)
>+#define FTM_OUTMASK (FTM_BASE_ADDR + 0x60)
>+#define FTM_COMBINE (FTM_BASE_ADDR + 0x64)
>+#define FTM_DEADTIME (FTM_BASE_ADDR + 0x68)
>+#define FTM_EXTTRIG (FTM_BASE_ADDR + 0x6C)
>+#define FTM_POL (FTM_BASE_ADDR + 0x70)
>+#define FTM_FMS (FTM_BASE_ADDR + 0x74)
>+#define FTM_FILTER (FTM_BASE_ADDR + 0x78)
>+#define FTM_FLTCTRL (FTM_BASE_ADDR + 0x7C)
>+#define FTM_QDCTRL (FTM_BASE_ADDR + 0x80)
>+#define FTM_CONF (FTM_BASE_ADDR + 0x84)
>+#define FTM_FLTPOL (FTM_BASE_ADDR + 0x88)
>+#define FTM_SYNCONF (FTM_BASE_ADDR + 0x8C)
>+#define FTM_INVCTRL (FTM_BASE_ADDR + 0x90)
>+#define FTM_SWOCTRL (FTM_BASE_ADDR + 0x94)
>+#define FTM_PWMLOAD (FTM_BASE_ADDR + 0x98)
You are already provide the c structure for the FTM, do you still need the
Base + offset define here?
>+
>+#define FTM_SC_TOF (1 << 7)
>+#define FTM_SC_TOIE (1 << 6)
>+#define FTM_SC_CPWMS (1 << 5)
>+#define FTM_SC_CLKS(x) ((x & 3) << 3)
>+#define FTM_SC_PS(x) ((x & 7) << 0)
>+
>+#define FTM_CNT_COUNT(x) (x & 0xFFFF)
>+
>+#define FTM_MOD_MOD(x) (x & 0xFFFF)
>+
>+#define FTM_CnSC_CHF (1 << 7)
>+#define FTM_CnSC_CHIE (1 << 6)
>+#define FTM_CnSC_MSB (1 << 5)
>+#define FTM_CnSC_MSA (1 << 4)
>+#define FTM_CnSC_ELSB (1 << 3)
>+#define FTM_CnSC_ELSA (1 << 2)
>+#define FTM_CnSC_DMA (1 << 0)
>+
>+#define FTM_CnV_VAL(x) (x & 0xFFFF)
>+
>+#define FTM_CNTIN_INIT(x) (x & 0xFFFF)
>+
>+#define FTM_STATUS_CH7F (1 << 7)
>+#define FTM_STATUS_CH6F (1 << 6)
>+#define FTM_STATUS_CH5F (1 << 5)
>+#define FTM_STATUS_CH4F (1 << 4)
>+#define FTM_STATUS_CH3F (1 << 3)
>+#define FTM_STATUS_CH2F (1 << 2)
>+#define FTM_STATUS_CH1F (1 << 1)
>+#define FTM_STATUS_CH0F (1 << 0)
>+
>+#define FTM_MODE_FAULTIE (1 << 7)
>+#define FTM_MODE_FAULTM(x) ((x & 3) << 5)
>+#define FTM_MODE_CAPTEST (1 << 4)
>+#define FTM_MODE_PWMSYNC (1 << 3)
>+#define FTM_MODE_WPDIS (1 << 2)
>+#define FTM_MODE_INIT (1 << 1)
>+#define FTM_MODE_FTMEN (1 << 0)
>+
>+#define FTM_SYNC_SWSYNC (1 << 7)
>+#define FTM_SYNC_TRIG2 (1 << 6)
>+#define FTM_SYNC_TRIG1 (1 << 5)
>+#define FTM_SYNC_TRIG0 (1 << 4)
>+#define FTM_SYNC_SYNCHOM (1 << 3)
>+#define FTM_SYNC_REINIT (1 << 2)
>+#define FTM_SYNC_CNTMAX (1 << 1)
>+#define FTM_SYNC_CNTMIN (1 << 0)
>+
>+#define FTM_OUTINIT_CH7OI (1 << 7)
>+#define FTM_OUTINIT_CH6OI (1 << 6)
>+#define FTM_OUTINIT_CH5OI (1 << 5)
>+#define FTM_OUTINIT_CH4OI (1 << 4)
>+#define FTM_OUTINIT_CH3OI (1 << 3)
>+#define FTM_OUTINIT_CH2OI (1 << 2)
>+#define FTM_OUTINIT_CH1OI (1 << 1)
>+#define FTM_OUTINIT_CH0OI (1 << 0)
>+
>+#define FTM_OUTMASK_CH7OM (1 << 7)
>+#define FTM_OUTMASK_CH6OM (1 << 6)
>+#define FTM_OUTMASK_CH5OM (1 << 5)
>+#define FTM_OUTMASK_CH4OM (1 << 4)
>+#define FTM_OUTMASK_CH3OM (1 << 3)
>+#define FTM_OUTMASK_CH2OM (1 << 2)
>+#define FTM_OUTMASK_CH1OM (1 << 1)
>+#define FTM_OUTMASK_CH0OM (1 << 0)
>+
>+#define FTM_COMBINE_FAULTEN3 (1 << 30)
>+#define FTM_COMBINE_SYNCEN3 (1 << 29)
>+#define FTM_COMBINE_DTEN3 (1 << 28)
>+#define FTM_COMBINE_DECAP3 (1 << 27)
>+#define FTM_COMBINE_DECAPEN3 (1 << 26)
>+#define FTM_COMBINE_COMP3 (1 << 25)
>+#define FTM_COMBINE_COMBINE3 (1 << 24)
>+#define FTM_COMBINE_FAULTEN2 (1 << 22)
>+#define FTM_COMBINE_SYNCEN2 (1 << 21)
>+#define FTM_COMBINE_DTEN2 (1 << 20)
>+#define FTM_COMBINE_DECAP2 (1 << 19)
>+#define FTM_COMBINE_DECAPEN2 (1 << 18)
>+#define FTM_COMBINE_COMP2 (1 << 17)
>+#define FTM_COMBINE_COMBINE2 (1 << 16)
>+#define FTM_COMBINE_FAULTEN1 (1 << 14)
>+#define FTM_COMBINE_SYNCEN1 (1 << 13)
>+#define FTM_COMBINE_DTEN1 (1 << 12)
>+#define FTM_COMBINE_DECAP1 (1 << 11)
>+#define FTM_COMBINE_DECAPEN1 (1 << 10)
>+#define FTM_COMBINE_COMP1 (1 << 9)
>+#define FTM_COMBINE_COMBINE1 (1 << 8)
>+#define FTM_COMBINE_FAULTEN0 (1 << 6)
>+#define FTM_COMBINE_SYNCEN0 (1 << 5)
>+#define FTM_COMBINE_DTEN0 (1 << 4)
>+#define FTM_COMBINE_DECAP0 (1 << 3)
>+#define FTM_COMBINE_DECAPEN0 (1 << 2)
>+#define FTM_COMBINE_COMP0 (1 << 1)
>+#define FTM_COMBINE_COMBINE0 (1 << 0)
>+
>+#define FTM_DEADTIME_DTPS(x) ((x & 3) << 6)
>+#define FTM_DEADTIME_DTVAL(x) ((x & 0x3F) << 0)
>+
>+#define FTM_EXTTRIG_TRIGF (1 << 7)
>+#define FTM_EXTTRIG_INITTRIGEN (1 << 6)
>+#define FTM_EXTTRIG_CH1TRIG (1 << 5)
>+#define FTM_EXTTRIG_CH0TRIG (1 << 4)
>+#define FTM_EXTTRIG_CH5TRIG (1 << 3)
>+#define FTM_EXTTRIG_CH4TRIG (1 << 2)
>+#define FTM_EXTTRIG_CH3TRIG (1 << 1)
>+#define FTM_EXTTRIG_CH2TRIG (1 << 0)
>+
>+#define FTM_POL_POL7 (1 << 7)
>+#define FTM_POL_POL6 (1 << 6)
>+#define FTM_POL_POL5 (1 << 5)
>+#define FTM_POL_POL4 (1 << 4)
>+#define FTM_POL_POL3 (1 << 3)
>+#define FTM_POL_POL2 (1 << 2)
>+#define FTM_POL_POL1 (1 << 1)
>+#define FTM_POL_POL0 (1 << 0)
>+
>+#define FTM_FMS_FAULTF (1 << 7)
>+#define FTM_FMS_WPEN (1 << 6)
>+#define FTM_FMS_FAULTIN (1 << 5)
>+#define FTM_FMS_FAULTF3 (1 << 3)
>+#define FTM_FMS_FAULTF2 (1 << 2)
>+#define FTM_FMS_FAULTF1 (1 << 1)
>+#define FTM_FMS_FAULTF0 (1 << 0)
>+
>+#define FTM_FILTER_CH3FVAL(x) ((x & 0xF) << 12)
>+#define FTM_FILTER_CH2FVAL(x) ((x & 0xF) << 8)
>+#define FTM_FILTER_CH1FVAL(x) ((x & 0xF) << 4)
>+#define FTM_FILTER_CH0FVAL(x) ((x & 0xF) << 0)
>+
>+#define FTM_FLTCTRL_FFVAL(x) ((x & 0xF) << 8)
>+#define FTM_FLTCTRL_FFLTR3EN (1 << 7)
>+#define FTM_FLTCTRL_FFLTR2EN (1 << 6)
>+#define FTM_FLTCTRL_FFLTR1EN (1 << 5)
>+#define FTM_FLTCTRL_FFLTR0EN (1 << 4)
>+#define FTM_FLTCTRL_FAULT3EN (1 << 3)
>+#define FTM_FLTCTRL_FAULT2EN (1 << 2)
>+#define FTM_FLTCTRL_FAULT1EN (1 << 1)
>+#define FTM_FLTCTRL_FAULT0EN (1 << 0)
>+
>+#define FTM_QDCTRL_PHAFLTREN (1 << 7)
>+#define FTM_QDCTRL_PHBFLTREN (1 << 6)
>+#define FTM_QDCTRL_PHAPOL (1 << 5)
>+#define FTM_QDCTRL_PHBPOL (1 << 4)
>+#define FTM_QDCTRL_QUADMODE (1 << 3)
>+#define FTM_QDCTRL_QUADIR (1 << 2)
>+#define FTM_QDCTRL_TOFDIR (1 << 1)
>+#define FTM_QDCTRL_QUADEN (1 << 0)
>+
>+#define FTM_CONF_GTBEOUT (1 << 10)
>+#define FTM_CONF_GTBEEN (1 << 9)
>+#define FTM_CONF_BDMMODE(x) ((x & 3) << 6)
>+#define FTM_CONF_NUMTOF(x) ((x & 0x1F) << 0)
>+
>+#define FTM_FLTPOL_FLT3POL (1 << 3)
>+#define FTM_FLTPOL_FLT2POL (1 << 2)
>+#define FTM_FLTPOL_FLT1POL (1 << 1)
>+#define FTM_FLTPOL_FLT0POL (1 << 0)
>+
>+#define FTM_SYNCONF_HWSOC (1 << 20)
>+#define FTM_SYNCONF_HWINVC (1 << 19)
>+#define FTM_SYNCONF_HWOM (1 << 18)
>+#define FTM_SYNCONF_HWWRBUF (1 << 17)
>+#define FTM_SYNCONF_HWRSTCNT (1 << 16)
>+#define FTM_SYNCONF_SWSOC (1 << 12)
>+#define FTM_SYNCONF_SWINVC (1 << 11)
>+#define FTM_SYNCONF_SWOM (1 << 10)
>+#define FTM_SYNCONF_SWWRBUF (1 << 9)
>+#define FTM_SYNCONF_SWRSTCNT (1 << 8)
>+#define FTM_SYNCONF_SYNCMODE (1 << 7)
>+#define FTM_SYNCONF_SWOC (1 << 5)
>+#define FTM_SYNCONF_INVC (1 << 4)
>+#define FTM_SYNCONF_CNTINC (1 << 2)
>+#define FTM_SYNCONF_HWTRIGMODE (1 << 0)
>+
>+#define FTM_INVCTRL_INV3EN (1 << 3)
>+#define FTM_INVCTRL_INV2EN (1 << 2)
>+#define FTM_INVCTRL_INV1EN (1 << 1)
>+#define FTM_INVCTRL_INV0EN (1 << 0)
>+
>+#define FTM_SWOCTRL_CH7OCV (1 << 15)
>+#define FTM_SWOCTRL_CH6OCV (1 << 14)
>+#define FTM_SWOCTRL_CH5OCV (1 << 13)
>+#define FTM_SWOCTRL_CH4OCV (1 << 12)
>+#define FTM_SWOCTRL_CH3OCV (1 << 11)
>+#define FTM_SWOCTRL_CH2OCV (1 << 10)
>+#define FTM_SWOCTRL_CH1OCV (1 << 9)
>+#define FTM_SWOCTRL_CH0OCV (1 << 8)
>+#define FTM_SWOCTRL_CH7OC (1 << 7)
>+#define FTM_SWOCTRL_CH6OC (1 << 6)
>+#define FTM_SWOCTRL_CH5OC (1 << 5)
>+#define FTM_SWOCTRL_CH4OC (1 << 4)
>+#define FTM_SWOCTRL_CH3OC (1 << 3)
>+#define FTM_SWOCTRL_CH2OC (1 << 2)
>+#define FTM_SWOCTRL_CH1OC (1 << 1)
>+#define FTM_SWOCTRL_CH0OC (1 << 0)
>+
>+#define FTM_PWMLOAD_LDOK (1 << 9)
>+#define FTM_PWMLOAD_CH7SEL (1 << 7)
>+#define FTM_PWMLOAD_CH6SEL (1 << 6)
>+#define FTM_PWMLOAD_CH5SEL (1 << 5)
>+#define FTM_PWMLOAD_CH4SEL (1 << 4)
>+#define FTM_PWMLOAD_CH3SEL (1 << 3)
>+#define FTM_PWMLOAD_CH2SEL (1 << 2)
>+#define FTM_PWMLOAD_CH1SEL (1 << 1)
>+#define FTM_PWMLOAD_CH0SEL (1 << 0)
>+
>+/* Periodic Interrupt Timer */
>+#define PIT_MCR (PIT_BASE_ADDR + 0x00)
>+#define PIT_LTMR64H (PIT_BASE_ADDR + 0xE0)
>+#define PIT_LTMR64L (PIT_BASE_ADDR + 0xE4)
>+#define PIT_LDVAL0 (PIT_BASE_ADDR + 0x100)
>+#define PIT_CVAL0 (PIT_BASE_ADDR + 0x104)
>+#define PIT_TCTRL0 (PIT_BASE_ADDR + 0x108)
>+#define PIT_TFLG0 (PIT_BASE_ADDR + 0x10C)
>+#define PIT_LDVAL1 (PIT_BASE_ADDR + 0x110)
>+#define PIT_CVAL1 (PIT_BASE_ADDR + 0x114)
>+#define PIT_TCTRL1 (PIT_BASE_ADDR + 0x118)
>+#define PIT_TFLG1 (PIT_BASE_ADDR + 0x11C)
>+#define PIT_LDVAL2 (PIT_BASE_ADDR + 0x120)
>+#define PIT_CVAL2 (PIT_BASE_ADDR + 0x124)
>+#define PIT_TCTRL2 (PIT_BASE_ADDR + 0x128)
>+#define PIT_TFLG2 (PIT_BASE_ADDR + 0x12C)
>+#define PIT_LDVAL3 (PIT_BASE_ADDR + 0x130)
>+#define PIT_CVAL3 (PIT_BASE_ADDR + 0x134)
>+#define PIT_TCTRL3 (PIT_BASE_ADDR + 0x138)
>+#define PIT_TFLG3 (PIT_BASE_ADDR + 0x13C)
>+#define PIT_LDVAL4 (PIT_BASE_ADDR + 0x140)
>+#define PIT_CVAL4 (PIT_BASE_ADDR + 0x144)
>+#define PIT_TCTRL4 (PIT_BASE_ADDR + 0x148)
>+#define PIT_TFLG4 (PIT_BASE_ADDR + 0x14C)
>+#define PIT_LDVAL5 (PIT_BASE_ADDR + 0x150)
>+#define PIT_CVAL5 (PIT_BASE_ADDR + 0x154)
>+#define PIT_TCTRL5 (PIT_BASE_ADDR + 0x158)
>+#define PIT_TFLG5 (PIT_BASE_ADDR + 0x15C)
>+#define PIT_LDVAL6 (PIT_BASE_ADDR + 0x160)
>+#define PIT_CVAL6 (PIT_BASE_ADDR + 0x164)
>+#define PIT_TCTRL6 (PIT_BASE_ADDR + 0x168)
>+#define PIT_TFLG6 (PIT_BASE_ADDR + 0x16C)
>+#define PIT_LDVAL7 (PIT_BASE_ADDR + 0x170)
>+#define PIT_CVAL7 (PIT_BASE_ADDR + 0x174)
>+#define PIT_TCTRL7 (PIT_BASE_ADDR + 0x178)
>+#define PIT_TFLG7 (PIT_BASE_ADDR + 0x17C)
Ditto,
>+
>+#define PIT_MCR_MDIS (1 << 1)
>+#define PIT_MCR_FRZ (1 << 0)
>+
>+#define PIT_TCTRL_CHN (1 << 2)
>+#define PIT_TCTRL_TIE (1 << 1)
>+#define PIT_TCTRL_TEN (1 << 0)
>+
>+#define PIT_TFLG_TIF (1 << 0)
>+
>+/* Low Power Timer */
>+#define LPTMR_CSR (LPTMR_BASE_ADDR + 0x00)
>+#define LPTMR_PSR (LPTMR_BASE_ADDR + 0x04)
>+#define LPTMR_CMR (LPTMR_BASE_ADDR + 0x08)
>+#define LPTMR_CNR (LPTMR_BASE_ADDR + 0x0C)
>+
>+#define LPTMR_CSR_TCF (1 << 7)
>+#define LPTMR_CSR_TIE (1 << 6)
>+#define LPTMR_CSR_TPS(x) ((x & 3) << 4)
>+#define LPTMR_CSR_TPP (1 << 3)
>+#define LPTMR_CSR_TFC (1 << 2)
>+#define LPTMR_CSR_TMS (1 << 1)
>+#define LPTMR_CSR_TEN (1 << 0)
>+
>+#define LPTMR_PSR_PRESCALE(x) ((x & 0x0F) << 3)
>+#define LPTMR_PSR_PBYP (1 << 2)
>+#define LPTMR_PSR_PCS(x) ((x & 0x03) << 0)
>+
>+#define LPTMR_CMR_COMPARE(x) (x & 0xFFFF)
>+#define LPTMR_CNR_COUNTER(x) (x & 0xFFFF)
>+
>+#endif /* __ASM_ARCH_TIMER_H */
>diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>new file mode 100644
>index 0000000..225a1e1
>--- /dev/null
>+++ b/arch/arm/include/asm/arch-vybrid/vybrid-pins.h
>@@ -0,0 +1,88 @@
>+/*
>+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
>+ *
>+ * See file CREDITS for list of people who contributed to this
>+ * project.
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#ifndef __ASM_ARCH_VYBRID_PINS_H__
>+#define __ASM_ARCH_VYBRID_PINS_H__
>+
>+#ifndef __ASSEMBLY__
>+
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent the
>+ * MUX control register offset
>+ */
>+#define MUX_I 0
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent the
>+ * PAD control register offset
>+ */
>+#define PAD_I 10
>+/*!
>+ * Starting bit position within each entry of \b iomux_pins to
>represent which
>+ * mux mode is for GPIO (0-based)
>+ */
>+#define GPIO_I 21
>+
>+#define MUX_IO_P 29
>+#define MUX_IO_I 24
>+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
>+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
>+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
>+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
>+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
>+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
>+
>+#define NON_GPIO_PORT 0x7
>+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
>+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
>+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
>+
>+#define NON_MUX_I PIN_TO_MUX_MASK
>+#define NON_PAD_I PIN_TO_PAD_MASK
>+
>+#define MUX_I_START 0x001C
>+#define PAD_I_START 0x3F0
>+#define INPUT_CTL_START 0x8C4
>+#define MUX_I_END (PAD_I_START - 4)
>+
>+#define _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi) \
>+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
>+ ((mi) << MUX_I) | \
>+ ((pi - PAD_I_START) << PAD_I) | \
>+ ((ga) << GPIO_I))
>+
>+#define _VYBRID_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
>+ _VYBRID_BUILD_PIN(gp, gi, ga, mi, pi)
>+
>+#define _VYBRID_BUILD_NON_GPIO_PIN(mi, pi) \
>+ _VYBRID_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
>+
>+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
>+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
>+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
>+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
>+
>+enum iomux_input_select {
>+ AUDMUX_P4_INPUT = 0,
>+};
Could you please consider the common iomux-v3 code?
Jason Liu
>+
>+#endif /* __ASSEMBLY__ */
>+#endif /* __ASM_ARCH_VYBRID_PINS_H__ */
>diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
>new file mode 100644
>index 0000000..51cfba5
[..]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
2013-04-12 6:53 ` [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support Alison Wang
@ 2013-04-12 6:53 ` Alison Wang
2013-04-12 11:41 ` Fabio Estevam
2013-04-13 20:50 ` Stefano Babic
2013-04-12 6:53 ` [U-Boot] [PATCH 3/5] vybrid: add uart driver support Alison Wang
` (4 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Alison Wang @ 2013-04-12 6:53 UTC (permalink / raw)
To: u-boot
This patch adds Freescale vybrid vf600 tower board support.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
board/freescale/vybrid/Makefile | 40 +++
board/freescale/vybrid/vybrid.c | 488 +++++++++++++++++++++++++++++++++
board/freescale/vybrid/vybridimage.cfg | 44 +++
boards.cfg | 2 +
include/configs/vybrid.h | 284 +++++++++++++++++++
include/configs/vybrid_iram.h | 284 +++++++++++++++++++
6 files changed, 1142 insertions(+)
create mode 100644 board/freescale/vybrid/Makefile
create mode 100644 board/freescale/vybrid/vybrid.c
create mode 100644 board/freescale/vybrid/vybridimage.cfg
create mode 100644 include/configs/vybrid.h
create mode 100644 include/configs/vybrid_iram.h
diff --git a/board/freescale/vybrid/Makefile b/board/freescale/vybrid/Makefile
new file mode 100644
index 0000000..0749b21
--- /dev/null
+++ b/board/freescale/vybrid/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright 2012-2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c
new file mode 100644
index 0000000..c2da1ff
--- /dev/null
+++ b/board/freescale/vybrid/vybrid.c
@@ -0,0 +1,488 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fec.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/vybrid-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_IOMUX 0x00000180
+#define DDR_IOMUX1 0x00010180
+
+#define PHY_DQ_TIMING 0x00002613
+#define PHY_DQS_TIMING 0x00002615
+#define PHY_CTRL 0x01210080
+#define PHY_MASTER_CTRL 0x0001012a
+#define PHY_SLAVE_CTRL 0x00012020
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {CONFIG_SYS_ESDHC1_BASE, 1},
+ {ESDHC2_BASE_ADDR, 1},
+};
+#endif
+
+void setup_iomux_ddr(void)
+{
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE);
+ __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0);
+ __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1);
+ __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0);
+}
+
+void ddr_phy_init(void)
+{
+ /* phy_dq_timing_reg freq set 0 */
+ __raw_writel(PHY_DQ_TIMING, DDR_PHY000);
+ __raw_writel(PHY_DQ_TIMING, DDR_PHY016);
+ __raw_writel(PHY_DQ_TIMING, DDR_PHY032);
+ __raw_writel(PHY_DQ_TIMING, DDR_PHY048);
+
+ /* phy_dqs_timing_reg freq set 0 */
+ __raw_writel(PHY_DQS_TIMING, DDR_PHY001);
+ __raw_writel(PHY_DQS_TIMING, DDR_PHY017);
+ __raw_writel(PHY_DQS_TIMING, DDR_PHY033);
+ __raw_writel(PHY_DQS_TIMING, DDR_PHY049);
+
+ /* phy_gate_lpbk_ctrl_reg freq set 0 */
+ __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */
+ __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */
+ __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */
+ __raw_writel(PHY_CTRL, DDR_PHY050);
+
+ /* phy_dll_master_ctrl_reg freq set 0 */
+ __raw_writel(PHY_MASTER_CTRL, DDR_PHY003);
+ __raw_writel(PHY_MASTER_CTRL, DDR_PHY019);
+ __raw_writel(PHY_MASTER_CTRL, DDR_PHY035);
+ __raw_writel(PHY_MASTER_CTRL, DDR_PHY051);
+
+ /* phy_dll_slave_ctrl_reg freq set 0 */
+ __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004);
+ __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020);
+ __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036);
+ __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052);
+
+ __raw_writel(0x00001105, DDR_PHY050);
+}
+
+unsigned long ddr_ctrl_init(void)
+{
+ int dram_size, rows, cols, banks, port;
+
+ __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */
+ __raw_writel(0x00000020, DDR_CR002); /* TINIT */
+ __raw_writel(0x0000007c, DDR_CR010); /* reset during power on */
+ /* warm boot - 200ns */
+ __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */
+ __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */
+ __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd
+ tbst_int_interval */
+ __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr, tras_min */
+ __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */
+ __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */
+ __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */
+
+ __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */
+ __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout
+ ccAP */
+ __raw_writel(0x000B0000, DDR_CR022); /* tdal */
+ __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */
+ __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm
+ trp_ab */
+ __raw_writel(0x00010000, DDR_CR025); /* tref_enable, auto_refresh
+ arefresh */
+ __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */
+ __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at 5 */
+ __raw_writel(0x00000003, DDR_CR029); /* tpdex */
+
+ __raw_writel(0x0000000A, DDR_CR030); /* txpdll */
+ __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */
+ __raw_writel(0x00010000, DDR_CR033); /* cke_dly, en_quick_srefresh
+ * srefresh_exit_no_refresh,
+ * pwr, srefresh_exit
+ */
+ __raw_writel(0x00050500, DDR_CR034); /* cksrx, */
+ /* cksre, lowpwr_ref_en */
+
+ /* Frequency change */
+ __raw_writel(0x00000100, DDR_CR038); /* freq change... */
+ __raw_writel(0x04001002, DDR_CR039);
+
+ __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */
+ __raw_writel(0x00000000, DDR_CR045); /* wrmd */
+ __raw_writel(0x00000000, DDR_CR046); /* rdmd */
+ __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK:
+ * LPDDR2 set to 2, else 0
+ */
+
+ /* DRAM device Mode registers */
+ __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8 only
+ * mr1, if freq < 125
+ * dll_dis = 1, rtt = 0
+ * if freq > 125, dll_dis = 0
+ * rtt = 3
+ */
+ __raw_writel(0x00000000, DDR_CR049); /* mr2 */
+ __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0 */
+
+ __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */
+
+ /* ZQ stuff */
+ __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */
+ __raw_writel(0x02000040, DDR_CR067); /* zqcs */
+ __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit, qz_req */
+
+ __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */
+ __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0 */
+ __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate, no_zq_init */
+
+ /* DRAM controller misc */
+ __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff, row_diff
+ bank_diff */
+ __raw_writel(0x0101ffff, DDR_CR074); /* bank_split, addr_cmp_en
+ cmd/age cnt */
+ __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en
+ pri en, plen */
+ __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis
+ * (#cmdqueues
+ * dis_rw_grp_w_bnk_conflict
+ * w2r_split_en, cs_same_en */
+ __raw_writel(0x01000101, DDR_CR077); /* cs_map, inhibit_dram_cmd
+ * dis_interleave, swen */
+ __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4, reduc
+ burst_on_fly */
+ __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref en
+ * ctrlupd_req
+ * ctrller busy
+ * in_ord_accept */
+ /* disable interrupts */
+ __raw_writel(0x1FFFFFFF, DDR_CR082);
+
+ /* ODT */
+ __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0
+ * rd_map_cs0
+ * port_data_err_id */
+ __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */
+ __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */
+
+ __raw_writel(0x00020000, DDR_CR091);
+ __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */
+
+ __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */
+
+ /* AXI ports */
+ __raw_writel(0x00202000, DDR_CR105);
+ __raw_writel(0x20200000, DDR_CR106);
+ __raw_writel(0x00002020, DDR_CR110);
+ __raw_writel(0x00202000, DDR_CR114);
+ __raw_writel(0x20200000, DDR_CR115);
+
+ __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1-2:1
+ * 2-1:2, 3- sync, w_pri
+ * r_pri
+ */
+ __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */
+ __raw_writel(0x00000000, DDR_CR119); /* fifo_type */
+
+ __raw_writel(0x02020000, DDR_CR120);
+ __raw_writel(0x00000202, DDR_CR121);
+ __raw_writel(0x01010064, DDR_CR122);
+ __raw_writel(0x00000101, DDR_CR123);
+ __raw_writel(0x00000064, DDR_CR124);
+
+ /* TDFI */
+ __raw_writel(0x00000000, DDR_CR125);
+ __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */
+ __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */
+
+ __raw_writel(0x00000000, DDR_CR131);
+ __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */
+ __raw_writel(0x02000000, DDR_CR137);
+ __raw_writel(0x04070303, DDR_CR139);
+
+ __raw_writel(0x00000000, DDR_CR136);
+
+ __raw_writel(0x68200000, DDR_CR154);
+ __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */
+ __raw_writel(0x00000006, DDR_CR158); /* twr */
+ __raw_writel(0x00000006, DDR_CR159); /* todth */
+
+ ddr_phy_init();
+
+ __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start */
+
+ udelay(200);
+
+ rows = (__raw_readl(DDR_CR001) & 0x1F) -
+ ((__raw_readl(DDR_CR073) >> 8) & 3);
+ cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) -
+ ((__raw_readl(DDR_CR073) >> 16) & 7);
+ banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3));
+ port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2;
+
+ dram_size = (1 << (rows + cols)) * banks * port;
+
+ return dram_size;
+}
+
+int dram_init(void)
+{
+ setup_iomux_ddr();
+#ifdef CONFIG_SYS_UBOOT_IN_GPURAM
+ gd->ram_size = 0x80000;
+ ddr_ctrl_init();
+#else
+ gd->ram_size = ddr_ctrl_init();
+#endif
+ return 0;
+}
+
+void setup_iomux_uart(void)
+{
+ __raw_writel(0x002011a2, IOMUXC_PAD_026);
+ __raw_writel(0x002011a1, IOMUXC_PAD_027);
+ __raw_writel(0x002011a2, IOMUXC_PAD_028);
+ __raw_writel(0x002011a1, IOMUXC_PAD_029);
+ __raw_writel(0x001011a2, IOMUXC_PAD_032);
+ __raw_writel(0x001011a1, IOMUXC_PAD_033);
+}
+
+#ifdef CONFIG_CMD_NET
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+ __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */
+
+ if (setclear) {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/
+ __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/
+ __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/
+ __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/
+ __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/
+ __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/
+ __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/
+ __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/
+ __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/
+ }
+ if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
+ __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/
+ __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/
+ __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/
+ __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/
+ __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/
+ __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/
+ __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/
+ __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/
+ __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/
+ __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/
+ __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/
+ __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/
+ __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/
+ __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/
+ __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/
+ __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/
+ __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/
+ }
+ if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
+ __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/
+ __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/
+ __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/
+ __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/
+ __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/
+ __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/
+ __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/
+ __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/
+ __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_QUAD_SPI
+void setup_iomux_quadspi(void)
+{
+ __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */
+ __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */
+
+ __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */
+ __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */
+ __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ int ret;
+
+ __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */
+ __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */
+ __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */
+ __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */
+ __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */
+ __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */
+
+ ret = 1;
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ u32 index = 0;
+ s32 status = 0;
+
+ esdhc_cfg[0].sdhc_clk = 132000000;
+ esdhc_cfg[1].sdhc_clk = 132000000;
+ status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ return status;
+}
+#endif
+
+#ifdef CONFIG_NAND_FSL_NFC
+void setup_iomux_nfc(void)
+{
+ __raw_writel(0x002038df, IOMUXC_PAD_063);
+ __raw_writel(0x002038df, IOMUXC_PAD_064);
+ __raw_writel(0x002038df, IOMUXC_PAD_065);
+ __raw_writel(0x002038df, IOMUXC_PAD_066);
+ __raw_writel(0x002038df, IOMUXC_PAD_067);
+ __raw_writel(0x002038df, IOMUXC_PAD_068);
+ __raw_writel(0x002038df, IOMUXC_PAD_069);
+ __raw_writel(0x002038df, IOMUXC_PAD_070);
+ __raw_writel(0x002038df, IOMUXC_PAD_071);
+ __raw_writel(0x002038df, IOMUXC_PAD_072);
+ __raw_writel(0x002038df, IOMUXC_PAD_073);
+ __raw_writel(0x002038df, IOMUXC_PAD_074);
+ __raw_writel(0x002038df, IOMUXC_PAD_075);
+ __raw_writel(0x002038df, IOMUXC_PAD_076);
+ __raw_writel(0x002038df, IOMUXC_PAD_077);
+ __raw_writel(0x002038df, IOMUXC_PAD_078);
+
+ __raw_writel(0x005038d2, IOMUXC_PAD_094);
+ __raw_writel(0x005038d2, IOMUXC_PAD_095);
+ __raw_writel(0x006038d2, IOMUXC_PAD_097);
+ __raw_writel(0x005038dd, IOMUXC_PAD_099);
+ __raw_writel(0x006038d2, IOMUXC_PAD_100);
+ __raw_writel(0x006038d2, IOMUXC_PAD_101);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+#ifdef CONFIG_NAND_FSL_NFC
+ setup_iomux_nfc();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+ setup_iomux_spi();
+#endif
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: Vybrid\n");
+
+ return 0;
+}
diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg
new file mode 100644
index 0000000..5da5659
--- /dev/null
+++ b/board/freescale/vybrid/vybridimage.cfg
@@ -0,0 +1,44 @@
+#
+# Copyright 2012-2013 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+
+# Setting IOMUXC
diff --git a/boards.cfg b/boards.cfg
index 7725a15..2700a76 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti
am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
pcm051 arm armv7 pcm051 phytec am33xx pcm051
highbank arm armv7 highbank - highbank
+vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
+vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h
new file mode 100644
index 0000000..d915bd0
--- /dev/null
+++ b/include/configs/vybrid.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the vybrid Board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+
+#define CONFIG_VYBRID
+
+#define CONFIG_SYS_VYBRID_HCLK 24000000
+#define CONFIG_SYS_VYBRID_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_IPG
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#include <asm/arch/vybrid-regs.h>
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#undef CONFIG_SETUP_MEMORY_TAGS
+#undef CONFIG_INITRD_TAG
+
+#undef CONFIG_OF_LIBFDT
+
+#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Hardware drivers */
+#define CONFIG_VYBRID_UART
+#define CONFIG_VYBRID_UART_BASE UART0_BASE
+#define CONFIG_VYBRID_GPIO
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_PING
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB /* loadb */
+#undef CONFIG_CMD_LOADS /* loads */
+
+#define CONFIG_SYS_TEXT_BASE 0x3f000800
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
+#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE 0x400E0000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+#define CONFIG_QUAD_SPI
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC1_PINMUX 0
+# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
+# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
+# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
+# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
+# define MCFFEC_TOUT_LOOP 50000
+# undef CONFIG_HAS_ETH1
+
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_ETHPRIME "FEC0"
+# define CONFIG_IPADDR 10.81.67.175
+# define CONFIG_NETMASK 255.255.252.0
+# define CONFIG_SERVERIP 10.81.64.153
+# define CONFIG_GATEWAYIP 10.81.67.254
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CONFIG_SYS_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x80010000
+#define CONFIG_SYS_MEMTEST_END 0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+#undef CONFIG_CMDLINE_EDITING
+
+#define CONFIG_PRAM 2048
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE (0x80000000)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* timer */
+#define FTM_BASE_ADDR FTM0_BASE_ADDR
+#define CONFIG_TMR_USEPIT
+
+/* clock/PLL configuration */
+/* uart0-2 */
+#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
+/* crc, pit, ftm0/1, a5/m4 wdog */
+#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
+/* lptmr, qspi0, iomuxc, gpio */
+#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
+/* anadig, scscm*/
+#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
+/* acrc, i2c0/1, wkup, ccm, gpc, src */
+#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
+#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
+/* ocotp, snvs, wdog_snvs, ddrmc */
+#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
+/* usb1, sdhc0/1 */
+#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
+/* qspi1 */
+#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
+/* enet0/1 */
+#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
+/* nfc */
+#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
+/* caam */
+#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
+
+#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
+#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
+#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
+#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
+#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
+#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
+#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
+#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
+#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
+#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
+
+#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
+#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
+#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
+#define CONFIG_SYS_ANADIG_528_SS 0x00000000
+#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
+#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
+#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
+#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
+#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
+#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
+#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
+#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
+#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
+#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h
new file mode 100644
index 0000000..f88050e
--- /dev/null
+++ b/include/configs/vybrid_iram.h
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the vybrid Board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+
+#define CONFIG_VYBRID
+
+#define CONFIG_SYS_VYBRID_HCLK 24000000
+#define CONFIG_SYS_VYBRID_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_IPG
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_SYS_UBOOT_IN_GPURAM
+
+#include <asm/arch/vybrid-regs.h>
+
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#undef CONFIG_SETUP_MEMORY_TAGS
+#undef CONFIG_INITRD_TAG
+
+#undef CONFIG_OF_LIBFDT
+
+#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (16 << 10)
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Hardware drivers */
+#define CONFIG_VYBRID_UART
+#define CONFIG_VYBRID_UART_BASE UART0_BASE
+#define CONFIG_VYBRID_GPIO
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT (1)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_PING
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB /* loadb */
+#undef CONFIG_CMD_LOADS /* loads */
+
+#define CONFIG_SYS_TEXT_BASE 0x3f000800
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
+#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE 0x400E0000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+#define CONFIG_QUAD_SPI
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC1_PINMUX 0
+# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
+# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
+# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
+# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
+# define MCFFEC_TOUT_LOOP 50000
+# undef CONFIG_HAS_ETH1
+
+# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+# define CONFIG_ETHPRIME "FEC0"
+# define CONFIG_IPADDR 10.81.67.175
+# define CONFIG_NETMASK 255.255.252.0
+# define CONFIG_SERVERIP 10.81.64.153
+# define CONFIG_GATEWAYIP 10.81.67.254
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+# ifndef CONFIG_SYS_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_LOADADDR 0x3f400000 /* loadaddr env var */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x3f400000
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+#undef CONFIG_CMDLINE_EDITING
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE (0x3f400000)
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* timer */
+#define FTM_BASE_ADDR FTM0_BASE_ADDR
+#define CONFIG_TMR_USEPIT
+
+/* clock/PLL configuration */
+/* uart0-2 */
+#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
+/* crc, pit, ftm0/1, a5/m4 wdog */
+#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
+/* lptmr, qspi0, iomuxc, gpio */
+#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
+/* anadig, scscm*/
+#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
+/* acrc, i2c0/1, wkup, ccm, gpc, src */
+#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
+#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
+/* ocotp, snvs, wdog_snvs, ddrmc */
+#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
+/* usb1, sdhc0/1 */
+#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
+/* qspi1 */
+#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
+/* enet0/1 */
+#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
+/* nfc */
+#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
+/* caam */
+#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
+
+#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
+#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
+#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
+#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
+#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
+#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
+#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
+#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
+#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
+#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
+
+#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
+#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
+#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
+#define CONFIG_SYS_ANADIG_528_SS 0x00000000
+#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
+#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
+#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
+#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
+#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
+#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
+#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
+#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
+#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
+#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
+#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
+#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE (8 * 1024)
+#undef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support
2013-04-12 6:53 ` [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support Alison Wang
@ 2013-04-12 11:41 ` Fabio Estevam
[not found] ` <81BA6E5E0BC2344391CABCEE22D1B6D82F26CF@039-SN1MPN1-002.039d.mgd.msft.net>
2013-04-13 20:50 ` Stefano Babic
1 sibling, 1 reply; 27+ messages in thread
From: Fabio Estevam @ 2013-04-12 11:41 UTC (permalink / raw)
To: u-boot
Hi Alison,
On Fri, Apr 12, 2013 at 3:53 AM, Alison Wang <b18965@freescale.com> wrote:
> This patch adds Freescale vybrid vf600 tower board support.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> board/freescale/vybrid/Makefile | 40 +++
> board/freescale/vybrid/vybrid.c | 488 +++++++++++++++++++++++++++++++++
Vybrid is the SoC name and the board name is vf600, right?
Then you should add:
board/freescale/vf600
Also, please copy Stefano Babic in your future patches, as he is the
U-boot imx maintainer.
> board/freescale/vybrid/vybridimage.cfg | 44 +++
> boards.cfg | 2 +
> include/configs/vybrid.h | 284 +++++++++++++++++++
> include/configs/vybrid_iram.h | 284 +++++++++++++++++++
> 6 files changed, 1142 insertions(+)
> create mode 100644 board/freescale/vybrid/Makefile
> create mode 100644 board/freescale/vybrid/vybrid.c
> create mode 100644 board/freescale/vybrid/vybridimage.cfg
> create mode 100644 include/configs/vybrid.h
> create mode 100644 include/configs/vybrid_iram.h
This patch should be the last of the series.
You add the board support here, but ethernet, serial, esdhc support
comes later in the patch series.
Please add an entry to MAINTAINERS file.
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg[2] = {
> + {CONFIG_SYS_ESDHC1_BASE, 1},
> + {ESDHC2_BASE_ADDR, 1},
CONFIG_ESDHC2_BASE_ADDR ?
> +int dram_init(void)
> +{
> + setup_iomux_ddr();
> +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM
You introduced CONFIG_SYS_UBOOT_IN_GPURAM here and it would be nice to
add an entry into README explaining what it means.
> + gd->ram_size = 0x80000;
> + ddr_ctrl_init();
> +#else
> + gd->ram_size = ddr_ctrl_init();
> +#endif
> + return 0;
Can't you use the standard method?
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> +#ifdef CONFIG_QUAD_SPI
CONFIG_QUAD_SPI does not exist in U-boot. Can't you re-use an existing
SPI config option?
> +#ifdef CONFIG_FSL_ESDHC
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + int ret;
> +
> + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */
> + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */
> + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */
This function should basically return the card detect status, please
setup the IOMUX in another place.
> + ret = 1;
> + return ret;
In this board you assume that the SD card is always present, right?
You could remove the 'ret' variable.
> diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg
> new file mode 100644
> index 0000000..5da5659
> --- /dev/null
> +++ b/board/freescale/vybrid/vybridimage.cfg
> @@ -0,0 +1,44 @@
> +#
> +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not write to the Free Software
> +# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> +# MA 02110-1301 USA
> +#
> +# Refer docs/README.imxmage for more details about how-to configure
> +# and create imximage boot image
> +#
> +# The syntax is taken as close as possible with the kwbimage
> +
> +IMAGE_VERSION 2
> +
> +# Boot Device : one of
> +# spi, sd (the board has no nand neither onenand)
> +
> +BOOT_FROM sd
> +
> +# Device Configuration Data (DCD)
> +#
> +# Each entry must have the format:
> +# Addr-type Address Value
> +#
> +# where:
> +# Addr-type register length (1,2 or 4 bytes)
> +# Address absolute address of the register
> +# value value to be stored in the register
> +
> +# Setting IOMUXC
This file is suited for imx. If you don't need this for Vybrid, please
remove it.
> diff --git a/boards.cfg b/boards.cfg
> index 7725a15..2700a76 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti
> am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
> pcm051 arm armv7 pcm051 phytec am33xx pcm051
> highbank arm armv7 highbank - highbank
> +vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
> +vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
Looks like you don't need vybridimage.cfg.
> mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
> mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
> mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
> diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h
> new file mode 100644
> index 0000000..d915bd0
> --- /dev/null
> +++ b/include/configs/vybrid.h
> @@ -0,0 +1,284 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the vybrid Board
Since Vybrid is the SoC name, I would expect the
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> + /* High Level Configuration Options */
> +
> +#define CONFIG_VYBRID
> +
> +#define CONFIG_SYS_VYBRID_HCLK 24000000
> +#define CONFIG_SYS_VYBRID_CLK32 32768
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_SYS_IPG
> +
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +
> +#include <asm/arch/vybrid-regs.h>
Move the include to the start of the file.
> +
> +/*
> + * Disabled for now due to build problems under Debian and a significant
> + * increase in the final file size: 144260 vs. 109536 Bytes.
> + */
Please remove this comment. It does not apply here.
> +
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#undef CONFIG_SETUP_MEMORY_TAGS
> +#undef CONFIG_INITRD_TAG
> +
> +#undef CONFIG_OF_LIBFDT
> +
> +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_LATE_INIT
> +
> +/* Hardware drivers */
> +#define CONFIG_VYBRID_UART
> +#define CONFIG_VYBRID_UART_BASE UART0_BASE
> +#define CONFIG_VYBRID_GPIO
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_UART_PORT (1)
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BDI /* bdinfo */
> +#define CONFIG_CMD_BOOTD
> +#define CONFIG_CMD_CONSOLE /* coninfo */
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
> +#define CONFIG_CMD_MISC
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS /* NFS support */
Do you need to undef it? Just do not include it, right?
> +#define CONFIG_CMD_PING
> +#undef CONFIG_CMD_NAND
Same here.
> +#undef CONFIG_CMD_DATE
Same here.
> +#undef CONFIG_CMD_IMI /* iminfo */
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_LOADB /* loadb */
> +#undef CONFIG_CMD_LOADS /* loads */
> +
> +#define CONFIG_SYS_TEXT_BASE 0x3f000800
> +
> +#define CONFIG_MMC
> +#ifdef CONFIG_MMC
> +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +#endif
> +
> +/*
> + * NAND FLASH
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1
> +#define CONFIG_JFFS2_NAND
> +#define CONFIG_NAND_FSL_NFC
> +#define CONFIG_SYS_NAND_BASE 0x400E0000
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
> +#define CONFIG_SYS_NAND_SELECT_DEVICE
> +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> +#endif
> +
> +#define CONFIG_QUAD_SPI
> +
> +/* Network configuration */
> +#define CONFIG_MCFFEC
> +#ifdef CONFIG_MCFFEC
> +# define CONFIG_MII 1
> +# define CONFIG_MII_INIT 1
> +# define CONFIG_SYS_DISCOVER_PHY
> +# define CONFIG_SYS_RX_ETH_BUFFER 8
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +
> +# define CONFIG_SYS_FEC0_PINMUX 0
> +# define CONFIG_SYS_FEC1_PINMUX 0
> +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
> +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
> +# define MCFFEC_TOUT_LOOP 50000
> +# undef CONFIG_HAS_ETH1
> +
> +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
> +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
> +# define CONFIG_ETHPRIME "FEC0"
> +# define CONFIG_IPADDR 10.81.67.175
> +# define CONFIG_NETMASK 255.255.252.0
> +# define CONFIG_SERVERIP 10.81.64.153
> +# define CONFIG_GATEWAYIP 10.81.67.254
> +# define CONFIG_OVERWRITE_ETHADDR_ONCE
No hardcoded IP addresses/MAC addresses, please.
> +
> +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
> +# ifndef CONFIG_SYS_DISCOVER_PHY
> +# define FECDUPLEX FULL
> +# define FECSPEED _100BASET
> +# else
> +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +# endif
> +# endif /* CONFIG_SYS_DISCOVER_PHY */
> +#endif
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_ETHPRIME "FEC0"
> +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */
> +#define CONFIG_ARP_TIMEOUT 200UL
Is this really needed?
> diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h
> new file mode 100644
> index 0000000..f88050e
> --- /dev/null
> +++ b/include/configs/vybrid_iram.h
Do we really need two configs? Can't we have just one?
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support
2013-04-12 6:53 ` [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support Alison Wang
2013-04-12 11:41 ` Fabio Estevam
@ 2013-04-13 20:50 ` Stefano Babic
2013-04-28 10:49 ` Wang Huan-B18965
1 sibling, 1 reply; 27+ messages in thread
From: Stefano Babic @ 2013-04-13 20:50 UTC (permalink / raw)
To: u-boot
On 12/04/2013 08:53, Alison Wang wrote:
> This patch adds Freescale vybrid vf600 tower board support.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Hi Alison.
> board/freescale/vybrid/Makefile | 40 +++
> board/freescale/vybrid/vybrid.c | 488 +++++++++++++++++++++++++++++++++
> board/freescale/vybrid/vybridimage.cfg | 44 +++
> boards.cfg | 2 +
> include/configs/vybrid.h | 284 +++++++++++++++++++
> include/configs/vybrid_iram.h | 284 +++++++++++++++++++
> 6 files changed, 1142 insertions(+)
> create mode 100644 board/freescale/vybrid/Makefile
> create mode 100644 board/freescale/vybrid/vybrid.c
> create mode 100644 board/freescale/vybrid/vybridimage.cfg
> create mode 100644 include/configs/vybrid.h
> create mode 100644 include/configs/vybrid_iram.h
>
> diff --git a/board/freescale/vybrid/Makefile b/board/freescale/vybrid/Makefile
> new file mode 100644
> index 0000000..0749b21
> --- /dev/null
> +++ b/board/freescale/vybrid/Makefile
> @@ -0,0 +1,40 @@
> +#
> +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +COBJS := $(BOARD).o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c
> new file mode 100644
> index 0000000..c2da1ff
> --- /dev/null
> +++ b/board/freescale/vybrid/vybrid.c
> @@ -0,0 +1,488 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/fec.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/vybrid-pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/errno.h>
> +#include <asm/arch/sys_proto.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <usb/ehci-fsl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DDR_IOMUX 0x00000180
> +#define DDR_IOMUX1 0x00010180
> +
> +#define PHY_DQ_TIMING 0x00002613
> +#define PHY_DQS_TIMING 0x00002615
> +#define PHY_CTRL 0x01210080
> +#define PHY_MASTER_CTRL 0x0001012a
> +#define PHY_SLAVE_CTRL 0x00012020
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg[2] = {
> + {CONFIG_SYS_ESDHC1_BASE, 1},
> + {ESDHC2_BASE_ADDR, 1},
> +};
> +#endif
> +
> +void setup_iomux_ddr(void)
> +{
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE);
> + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0);
> + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1);
> + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1);
> + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0);
> +}
> +
> +void ddr_phy_init(void)
> +{
> + /* phy_dq_timing_reg freq set 0 */
> + __raw_writel(PHY_DQ_TIMING, DDR_PHY000);
> + __raw_writel(PHY_DQ_TIMING, DDR_PHY016);
> + __raw_writel(PHY_DQ_TIMING, DDR_PHY032);
> + __raw_writel(PHY_DQ_TIMING, DDR_PHY048);
> +
> + /* phy_dqs_timing_reg freq set 0 */
> + __raw_writel(PHY_DQS_TIMING, DDR_PHY001);
> + __raw_writel(PHY_DQS_TIMING, DDR_PHY017);
> + __raw_writel(PHY_DQS_TIMING, DDR_PHY033);
> + __raw_writel(PHY_DQS_TIMING, DDR_PHY049);
> +
> + /* phy_gate_lpbk_ctrl_reg freq set 0 */
> + __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */
> + __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */
> + __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */
> + __raw_writel(PHY_CTRL, DDR_PHY050);
> +
> + /* phy_dll_master_ctrl_reg freq set 0 */
> + __raw_writel(PHY_MASTER_CTRL, DDR_PHY003);
> + __raw_writel(PHY_MASTER_CTRL, DDR_PHY019);
> + __raw_writel(PHY_MASTER_CTRL, DDR_PHY035);
> + __raw_writel(PHY_MASTER_CTRL, DDR_PHY051);
> +
> + /* phy_dll_slave_ctrl_reg freq set 0 */
> + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004);
> + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020);
> + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036);
> + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052);
> +
> + __raw_writel(0x00001105, DDR_PHY050);
> +}
> +
> +unsigned long ddr_ctrl_init(void)
> +{
> + int dram_size, rows, cols, banks, port;
> +
> + __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */
> + __raw_writel(0x00000020, DDR_CR002); /* TINIT */
> + __raw_writel(0x0000007c, DDR_CR010); /* reset during power on */
> + /* warm boot - 200ns */
> + __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */
> + __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */
> + __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd
> + tbst_int_interval */
> + __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr, tras_min */
> + __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */
> + __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */
> + __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */
> +
> + __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */
> + __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout
> + ccAP */
> + __raw_writel(0x000B0000, DDR_CR022); /* tdal */
> + __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */
> + __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm
> + trp_ab */
> + __raw_writel(0x00010000, DDR_CR025); /* tref_enable, auto_refresh
> + arefresh */
> + __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */
> + __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at 5 */
> + __raw_writel(0x00000003, DDR_CR029); /* tpdex */
> +
> + __raw_writel(0x0000000A, DDR_CR030); /* txpdll */
> + __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */
> + __raw_writel(0x00010000, DDR_CR033); /* cke_dly, en_quick_srefresh
> + * srefresh_exit_no_refresh,
> + * pwr, srefresh_exit
> + */
> + __raw_writel(0x00050500, DDR_CR034); /* cksrx, */
> + /* cksre, lowpwr_ref_en */
> +
> + /* Frequency change */
> + __raw_writel(0x00000100, DDR_CR038); /* freq change... */
> + __raw_writel(0x04001002, DDR_CR039);
> +
> + __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */
> + __raw_writel(0x00000000, DDR_CR045); /* wrmd */
> + __raw_writel(0x00000000, DDR_CR046); /* rdmd */
> + __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK:
> + * LPDDR2 set to 2, else 0
> + */
> +
> + /* DRAM device Mode registers */
> + __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8 only
> + * mr1, if freq < 125
> + * dll_dis = 1, rtt = 0
> + * if freq > 125, dll_dis = 0
> + * rtt = 3
> + */
> + __raw_writel(0x00000000, DDR_CR049); /* mr2 */
> + __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0 */
> +
> + __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */
> +
> + /* ZQ stuff */
> + __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */
> + __raw_writel(0x02000040, DDR_CR067); /* zqcs */
> + __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit, qz_req */
> +
> + __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */
> + __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0 */
> + __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate, no_zq_init */
> +
> + /* DRAM controller misc */
> + __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff, row_diff
> + bank_diff */
> + __raw_writel(0x0101ffff, DDR_CR074); /* bank_split, addr_cmp_en
> + cmd/age cnt */
> + __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en
> + pri en, plen */
> + __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis
> + * (#cmdqueues
> + * dis_rw_grp_w_bnk_conflict
> + * w2r_split_en, cs_same_en */
> + __raw_writel(0x01000101, DDR_CR077); /* cs_map, inhibit_dram_cmd
> + * dis_interleave, swen */
> + __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4, reduc
> + burst_on_fly */
> + __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref en
> + * ctrlupd_req
> + * ctrller busy
> + * in_ord_accept */
> + /* disable interrupts */
> + __raw_writel(0x1FFFFFFF, DDR_CR082);
> +
> + /* ODT */
> + __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0
> + * rd_map_cs0
> + * port_data_err_id */
> + __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */
> + __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */
> +
> + __raw_writel(0x00020000, DDR_CR091);
> + __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */
> +
> + __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */
> +
> + /* AXI ports */
> + __raw_writel(0x00202000, DDR_CR105);
> + __raw_writel(0x20200000, DDR_CR106);
> + __raw_writel(0x00002020, DDR_CR110);
> + __raw_writel(0x00202000, DDR_CR114);
> + __raw_writel(0x20200000, DDR_CR115);
> +
> + __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1-2:1
> + * 2-1:2, 3- sync, w_pri
> + * r_pri
> + */
> + __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */
> + __raw_writel(0x00000000, DDR_CR119); /* fifo_type */
> +
> + __raw_writel(0x02020000, DDR_CR120);
> + __raw_writel(0x00000202, DDR_CR121);
> + __raw_writel(0x01010064, DDR_CR122);
> + __raw_writel(0x00000101, DDR_CR123);
> + __raw_writel(0x00000064, DDR_CR124);
> +
> + /* TDFI */
> + __raw_writel(0x00000000, DDR_CR125);
> + __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */
> + __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */
> +
> + __raw_writel(0x00000000, DDR_CR131);
> + __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */
> + __raw_writel(0x02000000, DDR_CR137);
> + __raw_writel(0x04070303, DDR_CR139);
> +
> + __raw_writel(0x00000000, DDR_CR136);
> +
> + __raw_writel(0x68200000, DDR_CR154);
> + __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */
> + __raw_writel(0x00000006, DDR_CR158); /* twr */
> + __raw_writel(0x00000006, DDR_CR159); /* todth */
> +
> + ddr_phy_init();
> +
> + __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start */
> +
> + udelay(200);
> +
> + rows = (__raw_readl(DDR_CR001) & 0x1F) -
> + ((__raw_readl(DDR_CR073) >> 8) & 3);
> + cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) -
> + ((__raw_readl(DDR_CR073) >> 16) & 7);
> + banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3));
> + port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2;
> +
> + dram_size = (1 << (rows + cols)) * banks * port;
> +
> + return dram_size;
> +}
> +
> +int dram_init(void)
> +{
> + setup_iomux_ddr();
> +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM
> + gd->ram_size = 0x80000;
> + ddr_ctrl_init();
> +#else
> + gd->ram_size = ddr_ctrl_init();
> +#endif
> + return 0;
> +}
> +
> +void setup_iomux_uart(void)
> +{
> + __raw_writel(0x002011a2, IOMUXC_PAD_026);
> + __raw_writel(0x002011a1, IOMUXC_PAD_027);
> + __raw_writel(0x002011a2, IOMUXC_PAD_028);
> + __raw_writel(0x002011a1, IOMUXC_PAD_029);
> + __raw_writel(0x001011a2, IOMUXC_PAD_032);
> + __raw_writel(0x001011a1, IOMUXC_PAD_033);
> +}
> +
> +#ifdef CONFIG_CMD_NET
> +int fecpin_setclear(struct eth_device *dev, int setclear)
> +{
> + struct fec_info_s *info = (struct fec_info_s *)dev->priv;
> +
> + __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */
> +
> + if (setclear) {
> + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
> + __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/
> + __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/
> + __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/
> + __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/
> + __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/
> + __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/
> + __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/
> + __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/
> + __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/
> + }
> + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
> + __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/
> + __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/
> + __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/
> + __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/
> + __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/
> + __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/
> + __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/
> + __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/
> + __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/
> + }
> + } else {
> + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
> + __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/
> + __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/
> + __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/
> + __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/
> + __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/
> + __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/
> + __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/
> + __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/
> + __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/
> + }
> + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
> + __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/
> + __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/
> + __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/
> + __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/
> + __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/
> + __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/
> + __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/
> + __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/
> + __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/
> + }
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_QUAD_SPI
> +void setup_iomux_quadspi(void)
> +{
> + __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */
> + __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */
> +
> + __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */
> + __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */
> + __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */
> +}
> +#endif
> +
> +#ifdef CONFIG_FSL_ESDHC
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + int ret;
> +
> + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */
> + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */
> + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */
> + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */
> +
> + ret = 1;
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + u32 index = 0;
> + s32 status = 0;
> +
> + esdhc_cfg[0].sdhc_clk = 132000000;
> + esdhc_cfg[1].sdhc_clk = 132000000;
> + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
> + return status;
> +}
> +#endif
> +
> +#ifdef CONFIG_NAND_FSL_NFC
> +void setup_iomux_nfc(void)
> +{
> + __raw_writel(0x002038df, IOMUXC_PAD_063);
> + __raw_writel(0x002038df, IOMUXC_PAD_064);
> + __raw_writel(0x002038df, IOMUXC_PAD_065);
> + __raw_writel(0x002038df, IOMUXC_PAD_066);
> + __raw_writel(0x002038df, IOMUXC_PAD_067);
> + __raw_writel(0x002038df, IOMUXC_PAD_068);
> + __raw_writel(0x002038df, IOMUXC_PAD_069);
> + __raw_writel(0x002038df, IOMUXC_PAD_070);
> + __raw_writel(0x002038df, IOMUXC_PAD_071);
> + __raw_writel(0x002038df, IOMUXC_PAD_072);
> + __raw_writel(0x002038df, IOMUXC_PAD_073);
> + __raw_writel(0x002038df, IOMUXC_PAD_074);
> + __raw_writel(0x002038df, IOMUXC_PAD_075);
> + __raw_writel(0x002038df, IOMUXC_PAD_076);
> + __raw_writel(0x002038df, IOMUXC_PAD_077);
> + __raw_writel(0x002038df, IOMUXC_PAD_078);
> +
> + __raw_writel(0x005038d2, IOMUXC_PAD_094);
> + __raw_writel(0x005038d2, IOMUXC_PAD_095);
> + __raw_writel(0x006038d2, IOMUXC_PAD_097);
> + __raw_writel(0x005038dd, IOMUXC_PAD_099);
> + __raw_writel(0x006038d2, IOMUXC_PAD_100);
> + __raw_writel(0x006038d2, IOMUXC_PAD_101);
> +}
> +#endif
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> +#ifdef CONFIG_NAND_FSL_NFC
> + setup_iomux_nfc();
> +#endif
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_MXC_SPI
> + setup_iomux_spi();
> +#endif
> + return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> + puts("Board: Vybrid\n");
> +
> + return 0;
> +}
> diff --git a/board/freescale/vybrid/vybridimage.cfg b/board/freescale/vybrid/vybridimage.cfg
> new file mode 100644
> index 0000000..5da5659
> --- /dev/null
> +++ b/board/freescale/vybrid/vybridimage.cfg
> @@ -0,0 +1,44 @@
> +#
> +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not write to the Free Software
> +# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
> +# MA 02110-1301 USA
> +#
> +# Refer docs/README.imxmage for more details about how-to configure
> +# and create imximage boot image
> +#
> +# The syntax is taken as close as possible with the kwbimage
> +
> +IMAGE_VERSION 2
> +
> +# Boot Device : one of
> +# spi, sd (the board has no nand neither onenand)
> +
> +BOOT_FROM sd
> +
> +# Device Configuration Data (DCD)
> +#
> +# Each entry must have the format:
> +# Addr-type Address Value
> +#
> +# where:
> +# Addr-type register length (1,2 or 4 bytes)
> +# Address absolute address of the register
> +# value value to be stored in the register
> +
> +# Setting IOMUXC
> diff --git a/boards.cfg b/boards.cfg
> index 7725a15..2700a76 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7 am335x ti
> am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
> pcm051 arm armv7 pcm051 phytec am33xx pcm051
> highbank arm armv7 highbank - highbank
> +vybrid arm armv7 vybrid freescale vybrid vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
> +vybrid_iram arm armv7 vybrid freescale vybrid vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
> mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
> mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
> mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
> diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h
> new file mode 100644
> index 0000000..d915bd0
> --- /dev/null
> +++ b/include/configs/vybrid.h
> @@ -0,0 +1,284 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the vybrid Board
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> + /* High Level Configuration Options */
> +
> +#define CONFIG_VYBRID
> +
> +#define CONFIG_SYS_VYBRID_HCLK 24000000
> +#define CONFIG_SYS_VYBRID_CLK32 32768
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +#define CONFIG_SYS_IPG
> +
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +
> +#include <asm/arch/vybrid-regs.h>
> +
> +/*
> + * Disabled for now due to build problems under Debian and a significant
> + * increase in the final file size: 144260 vs. 109536 Bytes.
> + */
> +
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#undef CONFIG_SETUP_MEMORY_TAGS
> +#undef CONFIG_INITRD_TAG
> +
> +#undef CONFIG_OF_LIBFDT
> +
> +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
> +/* Size of malloc() pool */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +
> +#define CONFIG_BOARD_LATE_INIT
> +
> +/* Hardware drivers */
> +#define CONFIG_VYBRID_UART
> +#define CONFIG_VYBRID_UART_BASE UART0_BASE
> +#define CONFIG_VYBRID_GPIO
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_SYS_UART_PORT (1)
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BDI /* bdinfo */
> +#define CONFIG_CMD_BOOTD
> +#define CONFIG_CMD_CONSOLE /* coninfo */
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
> +#define CONFIG_CMD_MISC
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS /* NFS support */
> +#define CONFIG_CMD_PING
> +#undef CONFIG_CMD_NAND
> +#undef CONFIG_CMD_DATE
> +#undef CONFIG_CMD_IMI /* iminfo */
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_LOADB /* loadb */
> +#undef CONFIG_CMD_LOADS /* loads */
> +
> +#define CONFIG_SYS_TEXT_BASE 0x3f000800
> +
> +#define CONFIG_MMC
> +#ifdef CONFIG_MMC
> +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_FAT
> +#define CONFIG_DOS_PARTITION
> +#endif
> +
> +/*
> + * NAND FLASH
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1
> +#define CONFIG_JFFS2_NAND
> +#define CONFIG_NAND_FSL_NFC
> +#define CONFIG_SYS_NAND_BASE 0x400E0000
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
> +#define CONFIG_SYS_NAND_SELECT_DEVICE
> +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> +#endif
> +
> +#define CONFIG_QUAD_SPI
> +
> +/* Network configuration */
> +#define CONFIG_MCFFEC
> +#ifdef CONFIG_MCFFEC
> +# define CONFIG_MII 1
> +# define CONFIG_MII_INIT 1
> +# define CONFIG_SYS_DISCOVER_PHY
> +# define CONFIG_SYS_RX_ETH_BUFFER 8
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +
> +# define CONFIG_SYS_FEC0_PINMUX 0
> +# define CONFIG_SYS_FEC1_PINMUX 0
> +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
> +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
> +# define MCFFEC_TOUT_LOOP 50000
> +# undef CONFIG_HAS_ETH1
> +
> +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
> +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
> +# define CONFIG_ETHPRIME "FEC0"
> +# define CONFIG_IPADDR 10.81.67.175
> +# define CONFIG_NETMASK 255.255.252.0
> +# define CONFIG_SERVERIP 10.81.64.153
> +# define CONFIG_GATEWAYIP 10.81.67.254
> +# define CONFIG_OVERWRITE_ETHADDR_ONCE
> +
> +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
> +# ifndef CONFIG_SYS_DISCOVER_PHY
> +# define FECDUPLEX FULL
> +# define FECSPEED _100BASET
> +# else
> +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +# endif
> +# endif /* CONFIG_SYS_DISCOVER_PHY */
> +#endif
> +
> +#define CONFIG_BOOTDELAY 3
> +#define CONFIG_ETHPRIME "FEC0"
> +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var */
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
> +#undef CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START 0x80010000
> +#define CONFIG_SYS_MEMTEST_END 0x87C00000
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ 1000
> +#undef CONFIG_CMDLINE_EDITING
> +
> +#define CONFIG_PRAM 2048
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE (0x80000000)
> +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* timer */
> +#define FTM_BASE_ADDR FTM0_BASE_ADDR
> +#define CONFIG_TMR_USEPIT
> +
> +/* clock/PLL configuration */
> +/* uart0-2 */
> +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
> +/* crc, pit, ftm0/1, a5/m4 wdog */
> +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
> +/* lptmr, qspi0, iomuxc, gpio */
> +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
> +/* anadig, scscm*/
> +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
> +/* acrc, i2c0/1, wkup, ccm, gpc, src */
> +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
> +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
> +/* ocotp, snvs, wdog_snvs, ddrmc */
> +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
> +/* usb1, sdhc0/1 */
> +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
> +/* qspi1 */
> +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
> +/* enet0/1 */
> +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
> +/* nfc */
> +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
> +/* caam */
> +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
> +
> +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
> +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
> +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
> +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
> +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
> +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
> +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
> +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
> +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
> +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
> +
> +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
> +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
> +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
> +#define CONFIG_SYS_ANADIG_528_SS 0x00000000
> +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
> +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
> +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
> +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
> +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
> +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
> +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
> +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
> +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
> +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#endif
> diff --git a/include/configs/vybrid_iram.h b/include/configs/vybrid_iram.h
> new file mode 100644
> index 0000000..f88050e
> --- /dev/null
> +++ b/include/configs/vybrid_iram.h
> @@ -0,0 +1,284 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the vybrid Board
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
As the name suggest, I am expecting that <soc>_iram.h contains the
layout of the internal RAM, IRAM on Freescale's SOC. So the name is
inconsistent with a board name.
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/* High Level Configuration Options */
> +
> +#define CONFIG_VYBRID
> +
> +#define CONFIG_SYS_VYBRID_HCLK 24000000
> +#define CONFIG_SYS_VYBRID_CLK32 32768
As I have already said, each CONFIG_SYS must be documented. Anyway, we
get rid of these two defines in MX2x / MX3 /.. Do we really need them ?
> +#define CONFIG_SYS_UBOOT_IN_GPURAM
???
> +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> +#undef CONFIG_SETUP_MEMORY_TAGS
> +#undef CONFIG_INITRD_TAG
> +
> +#undef CONFIG_OF_LIBFDT
> +
> +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
Set MACH_TYPE_VYBRID_VF6XX in this file
> +/* Command definition */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_BDI /* bdinfo */
> +#define CONFIG_CMD_BOOTD
> +#define CONFIG_CMD_CONSOLE /* coninfo */
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ELF
> +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
> +#define CONFIG_CMD_MISC
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS /* NFS support */
> +#define CONFIG_CMD_PING
> +#undef CONFIG_CMD_DATE
> +#undef CONFIG_CMD_IMI /* iminfo */
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_LOADB /* loadb */
> +#undef CONFIG_CMD_LOADS /* loads */
> +
> +#define CONFIG_SYS_TEXT_BASE 0x3f000800
> +
> +#define CONFIG_MMC
> +#ifdef CONFIG_MMC
> +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
> +#define CONFIG_FSL_ESDHC
> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> +
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Maybe correct, but they are up now defined only in PowerPC boards. Do
you confirm that they are needed ?
> +/*
> + * NAND FLASH
> + */
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_JFFS2_NAND
> +#define CONFIG_NAND_FSL_NFC
> +#define CONFIG_SYS_NAND_BASE 0x400E0000
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
> +#define CONFIG_SYS_NAND_SELECT_DEVICE
> +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> +#endif
Does the board have NAND ? I do not see the nand driver.
> +
> +/* Network configuration */
> +#define CONFIG_MCFFEC
> +#ifdef CONFIG_MCFFEC
> +# define CONFIG_MII 1
> +# define CONFIG_MII_INIT 1
> +# define CONFIG_SYS_DISCOVER_PHY
> +# define CONFIG_SYS_RX_ETH_BUFFER 8
> +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> +
> +# define CONFIG_SYS_FEC0_PINMUX 0
> +# define CONFIG_SYS_FEC1_PINMUX 0
> +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
> +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
> +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
> +# define MCFFEC_TOUT_LOOP 50000
> +# undef CONFIG_HAS_ETH1
> +
> +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
> +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
Do not hardcode network addresses in u-boot
> +/* timer */
> +#define FTM_BASE_ADDR FTM0_BASE_ADDR
> +#define CONFIG_TMR_USEPIT
> +
> +/* clock/PLL configuration */
> +/* uart0-2 */
> +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
> +/* crc, pit, ftm0/1, a5/m4 wdog */
> +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
> +/* lptmr, qspi0, iomuxc, gpio */
> +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
> +/* anadig, scscm*/
> +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
> +/* acrc, i2c0/1, wkup, ccm, gpc, src */
> +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
> +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
> +/* ocotp, snvs, wdog_snvs, ddrmc */
> +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
> +/* usb1, sdhc0/1 */
> +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
> +/* qspi1 */
> +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
> +/* enet0/1 */
> +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
> +/* nfc */
> +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
> +/* caam */
> +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
> +
> +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
> +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
> +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
> +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
> +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
> +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
> +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
> +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
> +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
> +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
> +
> +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
> +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
> +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
> +#define CONFIG_SYS_ANADIG_528_SS 0x00000000
> +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
> +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
> +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
> +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
> +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
> +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
> +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
> +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
> +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
> +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
> +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
> +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
> +
See my previous comments about this stuff.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support
2013-04-13 20:50 ` Stefano Babic
@ 2013-04-28 10:49 ` Wang Huan-B18965
0 siblings, 0 replies; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 10:49 UTC (permalink / raw)
To: u-boot
> On 12/04/2013 08:53, Alison Wang wrote:
> > This patch adds Freescale vybrid vf600 tower board support.
> >
> > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
>
> Hi Alison.
>
> > board/freescale/vybrid/Makefile | 40 +++
> > board/freescale/vybrid/vybrid.c | 488
> +++++++++++++++++++++++++++++++++
> > board/freescale/vybrid/vybridimage.cfg | 44 +++
> > boards.cfg | 2 +
> > include/configs/vybrid.h | 284 +++++++++++++++++++
> > include/configs/vybrid_iram.h | 284 +++++++++++++++++++
> > 6 files changed, 1142 insertions(+)
> > create mode 100644 board/freescale/vybrid/Makefile create mode
> > 100644 board/freescale/vybrid/vybrid.c create mode 100644
> > board/freescale/vybrid/vybridimage.cfg
> > create mode 100644 include/configs/vybrid.h create mode 100644
> > include/configs/vybrid_iram.h
> >
> > diff --git a/board/freescale/vybrid/Makefile
> > b/board/freescale/vybrid/Makefile new file mode 100644 index
> > 0000000..0749b21
> > --- /dev/null
> > +++ b/board/freescale/vybrid/Makefile
> > @@ -0,0 +1,40 @@
> > +#
> > +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> > +#
> > +# This program is free software; you can redistribute it and/or #
> > +modify it under the terms of the GNU General Public License as #
> > +published by the Free Software Foundation; either version 2 of # the
> > +License, or (at your option) any later version.
> > +#
> > +# This program is distributed in the hope that it will be useful, #
> > +but WITHOUT ANY WARRANTY; without even the implied warranty of #
> > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU
> > +General Public License for more details.
> > +#
> > +# You should have received a copy of the GNU General Public License #
> > +along with this program; if not, write to the Free Software #
> > +Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307
> > +USA #
> > +
> > +include $(TOPDIR)/config.mk
> > +
> > +LIB = $(obj)lib$(BOARD).o
> > +
> > +COBJS := $(BOARD).o
> > +
> > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> > +OBJS := $(addprefix $(obj),$(COBJS))
> > +SOBJS := $(addprefix $(obj),$(SOBJS))
> > +
> > +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> > + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
> > +
> > +#####################################################################
> > +####
> > +
> > +# defines $(obj).depend target
> > +include $(SRCTREE)/rules.mk
> > +
> > +sinclude $(obj).depend
> > +
> > +#####################################################################
> > +####
> > diff --git a/board/freescale/vybrid/vybrid.c
> > b/board/freescale/vybrid/vybrid.c new file mode 100644 index
> > 0000000..c2da1ff
> > --- /dev/null
> > +++ b/board/freescale/vybrid/vybrid.c
> > @@ -0,0 +1,488 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/fec.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/vybrid-pins.h>
> > +#include <asm/arch/iomux.h>
> > +#include <asm/errno.h>
> > +#include <asm/arch/sys_proto.h>
> > +#include <i2c.h>
> > +#include <mmc.h>
> > +#include <fsl_esdhc.h>
> > +#include <usb/ehci-fsl.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define DDR_IOMUX 0x00000180
> > +#define DDR_IOMUX1 0x00010180
> > +
> > +#define PHY_DQ_TIMING 0x00002613
> > +#define PHY_DQS_TIMING 0x00002615
> > +#define PHY_CTRL 0x01210080
> > +#define PHY_MASTER_CTRL 0x0001012a
> > +#define PHY_SLAVE_CTRL 0x00012020
> > +
> > +#ifdef CONFIG_FSL_ESDHC
> > +struct fsl_esdhc_cfg esdhc_cfg[2] = {
> > + {CONFIG_SYS_ESDHC1_BASE, 1},
> > + {ESDHC2_BASE_ADDR, 1},
> > +};
> > +#endif
> > +
> > +void setup_iomux_ddr(void)
> > +{
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA2);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA1);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_BA0);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CAS);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CKE);
> > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_CLK);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_CS);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D15);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D14);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D13);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D12);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D11);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D10);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D9);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D8);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D7);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D6);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D5);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D4);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D3);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D2);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D1);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_D0);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM1);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_DQM0);
> > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS1);
> > + __raw_writel(DDR_IOMUX1, IOMUXC_DDR_DQS0);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_RAS);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_WE);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT1);
> > + __raw_writel(DDR_IOMUX, IOMUXC_DDR_ODT0); }
> > +
> > +void ddr_phy_init(void)
> > +{
> > + /* phy_dq_timing_reg freq set 0 */
> > + __raw_writel(PHY_DQ_TIMING, DDR_PHY000);
> > + __raw_writel(PHY_DQ_TIMING, DDR_PHY016);
> > + __raw_writel(PHY_DQ_TIMING, DDR_PHY032);
> > + __raw_writel(PHY_DQ_TIMING, DDR_PHY048);
> > +
> > + /* phy_dqs_timing_reg freq set 0 */
> > + __raw_writel(PHY_DQS_TIMING, DDR_PHY001);
> > + __raw_writel(PHY_DQS_TIMING, DDR_PHY017);
> > + __raw_writel(PHY_DQS_TIMING, DDR_PHY033);
> > + __raw_writel(PHY_DQS_TIMING, DDR_PHY049);
> > +
> > + /* phy_gate_lpbk_ctrl_reg freq set 0 */
> > + __raw_writel(PHY_CTRL, DDR_PHY002); /* read delay bit21:19 */
> > + __raw_writel(PHY_CTRL, DDR_PHY018); /* phase_detect_sel bit18:16 */
> > + __raw_writel(PHY_CTRL, DDR_PHY034); /* bit lpbk_ctrl bit12 */
> > + __raw_writel(PHY_CTRL, DDR_PHY050);
> > +
> > + /* phy_dll_master_ctrl_reg freq set 0 */
> > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY003);
> > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY019);
> > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY035);
> > + __raw_writel(PHY_MASTER_CTRL, DDR_PHY051);
> > +
> > + /* phy_dll_slave_ctrl_reg freq set 0 */
> > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY004);
> > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY020);
> > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY036);
> > + __raw_writel(PHY_SLAVE_CTRL, DDR_PHY052);
> > +
> > + __raw_writel(0x00001105, DDR_PHY050); }
> > +
> > +unsigned long ddr_ctrl_init(void)
> > +{
> > + int dram_size, rows, cols, banks, port;
> > +
> > + __raw_writel(0x00000600, DDR_CR000); /* LPDDR2 or DDR3 */
> > + __raw_writel(0x00000020, DDR_CR002); /* TINIT */
> > + __raw_writel(0x0000007c, DDR_CR010); /* reset during power on
> */
> > + /* warm boot - 200ns */
> > + __raw_writel(0x00013880, DDR_CR011); /* 500us - 10ns */
> > + __raw_writel(0x0000050c, DDR_CR012); /* CASLAT_LIN, WRLAT */
> > + __raw_writel(0x15040404, DDR_CR013); /* trc, trrd, tccd
> > + tbst_int_interval */
> > + __raw_writel(0x1406040F, DDR_CR014); /* tfaw, tfp, twtr,
> tras_min */
> > + __raw_writel(0x04040000, DDR_CR016); /* tmrd, trtp */
> > + __raw_writel(0x006DB00C, DDR_CR017); /* tras_max, tmod */
> > + __raw_writel(0x00000403, DDR_CR018); /* tckesr, tcke */
> > +
> > + __raw_writel(0x01000000, DDR_CR020); /* ap, writrp */
> > + __raw_writel(0x06060101, DDR_CR021); /* trcd_int, tras_lockout
> > + ccAP */
> > + __raw_writel(0x000B0000, DDR_CR022); /* tdal */
> > + __raw_writel(0x03000200, DDR_CR023); /* bstlen, tmrr, tdll */
> > + __raw_writel(0x00000006, DDR_CR024); /* addr_mirror, reg_dimm
> > + trp_ab */
> > + __raw_writel(0x00010000, DDR_CR025); /* tref_enable,
> auto_refresh
> > + arefresh */
> > + __raw_writel(0x0C28002C, DDR_CR026); /* tref, trfc */
> > + __raw_writel(0x00000005, DDR_CR028); /* tref_interval fixed at
> 5 */
> > + __raw_writel(0x00000003, DDR_CR029); /* tpdex */
> > +
> > + __raw_writel(0x0000000A, DDR_CR030); /* txpdll */
> > + __raw_writel(0x00440200, DDR_CR031); /* txsnr, txsr */
> > + __raw_writel(0x00010000, DDR_CR033); /* cke_dly,
> en_quick_srefresh
> > + * srefresh_exit_no_refresh,
> > + * pwr, srefresh_exit
> > + */
> > + __raw_writel(0x00050500, DDR_CR034); /* cksrx, */
> > + /* cksre, lowpwr_ref_en */
> > +
> > + /* Frequency change */
> > + __raw_writel(0x00000100, DDR_CR038); /* freq change... */
> > + __raw_writel(0x04001002, DDR_CR039);
> > +
> > + __raw_writel(0x00000001, DDR_CR041); /* dfi_init_start */
> > + __raw_writel(0x00000000, DDR_CR045); /* wrmd */
> > + __raw_writel(0x00000000, DDR_CR046); /* rdmd */
> > + __raw_writel(0x00000000, DDR_CR047); /* REF_PER_AUTO_TEMPCHK:
> > + * LPDDR2 set to 2, else 0
> > + */
> > +
> > + /* DRAM device Mode registers */
> > + __raw_writel(0x00460420, DDR_CR048); /* mr0, ddr3 burst of 8
> only
> > + * mr1, if freq < 125
> > + * dll_dis = 1, rtt = 0
> > + * if freq > 125, dll_dis = 0
> > + * rtt = 3
> > + */
> > + __raw_writel(0x00000000, DDR_CR049); /* mr2 */
> > + __raw_writel(0x00000000, DDR_CR051); /* mr3 & mrsingle_data_0
> */
> > +
> > + __raw_writel(0x00000000, DDR_CR057); /* ctrl_raw */
> > +
> > + /* ZQ stuff */
> > + __raw_writel(0x01000200, DDR_CR066); /* zqcl, zqinit */
> > + __raw_writel(0x02000040, DDR_CR067); /* zqcs */
> > + __raw_writel(0x00000200, DDR_CR069); /* zq_on_sref_exit,
> qz_req */
> > +
> > + __raw_writel(0x00000040, DDR_CR070); /* ref_per_zq */
> > + __raw_writel(0x00000000, DDR_CR071); /* zqreset, ddr3 set to 0
> */
> > + __raw_writel(0x01000000, DDR_CR072); /* zqcs_rotate,
> no_zq_init */
> > +
> > + /* DRAM controller misc */
> > + __raw_writel(0x0a010300, DDR_CR073); /* arebit, col_diff,
> row_diff
> > + bank_diff */
> > + __raw_writel(0x0101ffff, DDR_CR074); /* bank_split,
> addr_cmp_en
> > + cmd/age cnt */
> > + __raw_writel(0x01010101, DDR_CR075); /* rw same pg, rw same en
> > + pri en, plen */
> > + __raw_writel(0x03030101, DDR_CR076); /* #q_entries_act_dis
> > + * (#cmdqueues
> > + * dis_rw_grp_w_bnk_conflict
> > + * w2r_split_en, cs_same_en */
> > + __raw_writel(0x01000101, DDR_CR077); /* cs_map,
> inhibit_dram_cmd
> > + * dis_interleave, swen */
> > + __raw_writel(0x0000000C, DDR_CR078); /* qfull, lpddr2_s4,
> reduc
> > + burst_on_fly */
> > + __raw_writel(0x01000000, DDR_CR079); /* ctrlupd_req_per aref
> en
> > + * ctrlupd_req
> > + * ctrller busy
> > + * in_ord_accept */
> > + /* disable interrupts */
> > + __raw_writel(0x1FFFFFFF, DDR_CR082);
> > +
> > + /* ODT */
> > + __raw_writel(0x01010000, DDR_CR087); /* odt: wr_map_cs0
> > + * rd_map_cs0
> > + * port_data_err_id */
> > + __raw_writel(0x00040000, DDR_CR088); /* todtl_2cmd */
> > + __raw_writel(0x00000002, DDR_CR089); /* add_odt stuff */
> > +
> > + __raw_writel(0x00020000, DDR_CR091);
> > + __raw_writel(0x00000000, DDR_CR092); /* tdqsck _min, max */
> > +
> > + __raw_writel(0x00002819, DDR_CR096); /* wlmrd, wldqsen */
> > +
> > + /* AXI ports */
> > + __raw_writel(0x00202000, DDR_CR105);
> > + __raw_writel(0x20200000, DDR_CR106);
> > + __raw_writel(0x00002020, DDR_CR110);
> > + __raw_writel(0x00202000, DDR_CR114);
> > + __raw_writel(0x20200000, DDR_CR115);
> > +
> > + __raw_writel(0x00000101, DDR_CR117); /* FIFO type (0-async, 1-
> 2:1
> > + * 2-1:2, 3- sync, w_pri
> > + * r_pri
> > + */
> > + __raw_writel(0x01010000, DDR_CR118); /* w_pri, rpri, en */
> > + __raw_writel(0x00000000, DDR_CR119); /* fifo_type */
> > +
> > + __raw_writel(0x02020000, DDR_CR120);
> > + __raw_writel(0x00000202, DDR_CR121);
> > + __raw_writel(0x01010064, DDR_CR122);
> > + __raw_writel(0x00000101, DDR_CR123);
> > + __raw_writel(0x00000064, DDR_CR124);
> > +
> > + /* TDFI */
> > + __raw_writel(0x00000000, DDR_CR125);
> > + __raw_writel(0x00000B00, DDR_CR126); /* PHY rdlat */
> > + __raw_writel(0x00000000, DDR_CR127); /* dram ck dis */
> > +
> > + __raw_writel(0x00000000, DDR_CR131);
> > + __raw_writel(0x00000506, DDR_CR132); /* wrlat, rdlat */
> > + __raw_writel(0x02000000, DDR_CR137);
> > + __raw_writel(0x04070303, DDR_CR139);
> > +
> > + __raw_writel(0x00000000, DDR_CR136);
> > +
> > + __raw_writel(0x68200000, DDR_CR154);
> > + __raw_writel(0x00000202, DDR_CR155); /* pad_ibe, _sel */
> > + __raw_writel(0x00000006, DDR_CR158); /* twr */
> > + __raw_writel(0x00000006, DDR_CR159); /* todth */
> > +
> > + ddr_phy_init();
> > +
> > + __raw_writel(0x00000601, DDR_CR000); /* LPDDR2 or DDR3, start
> */
> > +
> > + udelay(200);
> > +
> > + rows = (__raw_readl(DDR_CR001) & 0x1F) -
> > + ((__raw_readl(DDR_CR073) >> 8) & 3);
> > + cols = ((__raw_readl(DDR_CR001) >> 8) & 0xF) -
> > + ((__raw_readl(DDR_CR073) >> 16) & 7);
> > + banks = 1 << (3 - (__raw_readl(DDR_CR073) & 3));
> > + port = ((__raw_readl(DDR_CR078) >> 8) & 1) ? 1 : 2;
> > +
> > + dram_size = (1 << (rows + cols)) * banks * port;
> > +
> > + return dram_size;
> > +}
> > +
> > +int dram_init(void)
> > +{
> > + setup_iomux_ddr();
> > +#ifdef CONFIG_SYS_UBOOT_IN_GPURAM
> > + gd->ram_size = 0x80000;
> > + ddr_ctrl_init();
> > +#else
> > + gd->ram_size = ddr_ctrl_init();
> > +#endif
> > + return 0;
> > +}
> > +
> > +void setup_iomux_uart(void)
> > +{
> > + __raw_writel(0x002011a2, IOMUXC_PAD_026);
> > + __raw_writel(0x002011a1, IOMUXC_PAD_027);
> > + __raw_writel(0x002011a2, IOMUXC_PAD_028);
> > + __raw_writel(0x002011a1, IOMUXC_PAD_029);
> > + __raw_writel(0x001011a2, IOMUXC_PAD_032);
> > + __raw_writel(0x001011a1, IOMUXC_PAD_033); }
> > +
> > +#ifdef CONFIG_CMD_NET
> > +int fecpin_setclear(struct eth_device *dev, int setclear) {
> > + struct fec_info_s *info = (struct fec_info_s *)dev->priv;
> > +
> > + __raw_writel(0x00203191, IOMUXC_PAD_000); /* RMII_CLK */
> > +
> > + if (setclear) {
> > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
> > + __raw_writel(0x00103192, IOMUXC_PAD_045); /*MDC*/
> > + __raw_writel(0x00103193, IOMUXC_PAD_046); /*MDIO*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_047); /*RxDV*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_048); /*RxD1*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_049); /*RxD0*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_050); /*RxER*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_051); /*TxD1*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_052); /*TxD0*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_053); /*TxEn*/
> > + }
> > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
> > + __raw_writel(0x00103192, IOMUXC_PAD_054); /*MDC*/
> > + __raw_writel(0x00103193, IOMUXC_PAD_055); /*MDIO*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_056); /*RxDV*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_057); /*RxD1*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_058); /*RxD0*/
> > + __raw_writel(0x00103191, IOMUXC_PAD_059); /*RxER*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_060); /*TxD1*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_061); /*TxD0*/
> > + __raw_writel(0x00103192, IOMUXC_PAD_062); /*TxEn*/
> > + }
> > + } else {
> > + if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
> > + __raw_writel(0x00003192, IOMUXC_PAD_045); /*MDC*/
> > + __raw_writel(0x00003193, IOMUXC_PAD_046); /*MDIO*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_047); /*RxDV*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_048); /*RxD1*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_049); /*RxD0*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_050); /*RxER*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_051); /*TxD1*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_052); /*TxD0*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_053); /*TxEn*/
> > + }
> > + if (info->iobase == CONFIG_SYS_FEC1_IOBASE) {
> > + __raw_writel(0x00003192, IOMUXC_PAD_054); /*MDC*/
> > + __raw_writel(0x00003193, IOMUXC_PAD_055); /*MDIO*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_056); /*RxDV*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_057); /*RxD1*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_058); /*RxD0*/
> > + __raw_writel(0x00003191, IOMUXC_PAD_059); /*RxER*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_060); /*TxD1*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_061); /*TxD0*/
> > + __raw_writel(0x00003192, IOMUXC_PAD_062); /*TxEn*/
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_QUAD_SPI
> > +void setup_iomux_quadspi(void)
> > +{
> > + __raw_writel(0x001030C3, IOMUXC_PAD_079); /* SCK */
> > + __raw_writel(0x001030FF, IOMUXC_PAD_080); /* CS0 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_081); /* D3 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_082); /* D2 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_083); /* D1 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_084); /* D0 */
> > +
> > + __raw_writel(0x001030C3, IOMUXC_PAD_086); /* SCK */
> > + __raw_writel(0x001030FF, IOMUXC_PAD_087); /* CS0 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_088); /* D3 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_089); /* D2 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_090); /* D1 */
> > + __raw_writel(0x001030C3, IOMUXC_PAD_091); /* D0 */
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_FSL_ESDHC
> > +int board_mmc_getcd(struct mmc *mmc)
> > +{
> > + int ret;
> > +
> > + __raw_writel(0x005031ef, IOMUXC_PAD_014); /* clk */
> > + __raw_writel(0x005031ef, IOMUXC_PAD_015); /* cmd */
> > + __raw_writel(0x005031ef, IOMUXC_PAD_016); /* dat0 */
> > + __raw_writel(0x005031ef, IOMUXC_PAD_017); /* dat1 */
> > + __raw_writel(0x005031ef, IOMUXC_PAD_018); /* dat2 */
> > + __raw_writel(0x005031ef, IOMUXC_PAD_019); /* dat3 */
> > +
> > + ret = 1;
> > + return ret;
> > +}
> > +
> > +int board_mmc_init(bd_t *bis)
> > +{
> > + u32 index = 0;
> > + s32 status = 0;
> > +
> > + esdhc_cfg[0].sdhc_clk = 132000000;
> > + esdhc_cfg[1].sdhc_clk = 132000000;
> > + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
> > + return status;
> > +}
> > +#endif
> > +
> > +#ifdef CONFIG_NAND_FSL_NFC
> > +void setup_iomux_nfc(void)
> > +{
> > + __raw_writel(0x002038df, IOMUXC_PAD_063);
> > + __raw_writel(0x002038df, IOMUXC_PAD_064);
> > + __raw_writel(0x002038df, IOMUXC_PAD_065);
> > + __raw_writel(0x002038df, IOMUXC_PAD_066);
> > + __raw_writel(0x002038df, IOMUXC_PAD_067);
> > + __raw_writel(0x002038df, IOMUXC_PAD_068);
> > + __raw_writel(0x002038df, IOMUXC_PAD_069);
> > + __raw_writel(0x002038df, IOMUXC_PAD_070);
> > + __raw_writel(0x002038df, IOMUXC_PAD_071);
> > + __raw_writel(0x002038df, IOMUXC_PAD_072);
> > + __raw_writel(0x002038df, IOMUXC_PAD_073);
> > + __raw_writel(0x002038df, IOMUXC_PAD_074);
> > + __raw_writel(0x002038df, IOMUXC_PAD_075);
> > + __raw_writel(0x002038df, IOMUXC_PAD_076);
> > + __raw_writel(0x002038df, IOMUXC_PAD_077);
> > + __raw_writel(0x002038df, IOMUXC_PAD_078);
> > +
> > + __raw_writel(0x005038d2, IOMUXC_PAD_094);
> > + __raw_writel(0x005038d2, IOMUXC_PAD_095);
> > + __raw_writel(0x006038d2, IOMUXC_PAD_097);
> > + __raw_writel(0x005038dd, IOMUXC_PAD_099);
> > + __raw_writel(0x006038d2, IOMUXC_PAD_100);
> > + __raw_writel(0x006038d2, IOMUXC_PAD_101); } #endif
> > +
> > +int board_early_init_f(void)
> > +{
> > + setup_iomux_uart();
> > +#ifdef CONFIG_NAND_FSL_NFC
> > + setup_iomux_nfc();
> > +#endif
> > + return 0;
> > +}
> > +
> > +int board_init(void)
> > +{
> > + /* address of boot parameters */
> > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > + return 0;
> > +}
> > +
> > +#ifdef CONFIG_BOARD_LATE_INIT
> > +int board_late_init(void)
> > +{
> > +#ifdef CONFIG_MXC_SPI
> > + setup_iomux_spi();
> > +#endif
> > + return 0;
> > +}
> > +#endif
> > +
> > +int checkboard(void)
> > +{
> > + puts("Board: Vybrid\n");
> > +
> > + return 0;
> > +}
> > diff --git a/board/freescale/vybrid/vybridimage.cfg
> > b/board/freescale/vybrid/vybridimage.cfg
> > new file mode 100644
> > index 0000000..5da5659
> > --- /dev/null
> > +++ b/board/freescale/vybrid/vybridimage.cfg
> > @@ -0,0 +1,44 @@
> > +#
> > +# Copyright 2012-2013 Freescale Semiconductor, Inc.
> > +#
> > +# See file CREDITS for list of people who contributed to this #
> > +project.
> > +#
> > +# This program is free software; you can redistribute it and/or #
> > +modify it under the terms of the GNU General Public License as #
> > +published by the Free Software Foundation; either version 2 of # the
> > +License or (at your option) any later version.
> > +#
> > +# This program is distributed in the hope that it will be useful, #
> > +but WITHOUT ANY WARRANTY; without even the implied warranty of #
> > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU
> > +General Public License for more details.
> > +#
> > +# You should have received a copy of the GNU General Public License #
> > +along with this program; if not write to the Free Software #
> > +Foundation Inc. 51 Franklin Street Fifth Floor Boston, # MA
> > +02110-1301 USA # # Refer docs/README.imxmage for more details about
> > +how-to configure # and create imximage boot image # # The syntax is
> > +taken as close as possible with the kwbimage
> > +
> > +IMAGE_VERSION 2
> > +
> > +# Boot Device : one of
> > +# spi, sd (the board has no nand neither onenand)
> > +
> > +BOOT_FROM sd
> > +
> > +# Device Configuration Data (DCD)
> > +#
> > +# Each entry must have the format:
> > +# Addr-type Address Value
> > +#
> > +# where:
> > +# Addr-type register length (1,2 or 4 bytes)
> > +# Address absolute address of the register
> > +# value value to be stored in the register
> > +
> > +# Setting IOMUXC
> > diff --git a/boards.cfg b/boards.cfg
> > index 7725a15..2700a76 100644
> > --- a/boards.cfg
> > +++ b/boards.cfg
> > @@ -244,6 +244,8 @@ am335x_evm_uart5 arm armv7
> am335x ti
> > am335x_evm_usbspl arm armv7 am335x
> ti am33xx
> am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
> > pcm051 arm armv7 pcm051
> phytec am33xx pcm051
> > highbank arm armv7 highbank
> - highbank
> > +vybrid arm armv7 vybrid
> freescale vybrid
> vybrid:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
> > +vybrid_iram arm armv7 vybrid
> freescale vybrid
> vybrid_iram:VYBRID_CONFIG=board/freescale/vybrid/vybridimage.cfg
> > mx51_efikamx arm armv7 mx51_efikamx
> genesi mx5
> mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/gene
> si/mx51_efikamx/imximage_mx.cfg
> > mx51_efikasb arm armv7 mx51_efikamx
> genesi mx5
> mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/gene
> si/mx51_efikamx/imximage_sb.cfg
> > mx51evk arm armv7 mx51evk
> freescale mx5
> mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
> > diff --git a/include/configs/vybrid.h b/include/configs/vybrid.h new
> > file mode 100644 index 0000000..d915bd0
> > --- /dev/null
> > +++ b/include/configs/vybrid.h
> > @@ -0,0 +1,284 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * Configuration settings for the vybrid Board
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __CONFIG_H
> > +#define __CONFIG_H
> > +
> > + /* High Level Configuration Options */
> > +
> > +#define CONFIG_VYBRID
> > +
> > +#define CONFIG_SYS_VYBRID_HCLK 24000000
> > +#define CONFIG_SYS_VYBRID_CLK32 32768
> > +#define CONFIG_DISPLAY_CPUINFO
> > +#define CONFIG_DISPLAY_BOARDINFO
> > +#define CONFIG_SYS_IPG
> > +
> > +#define CONFIG_SYS_ICACHE_OFF
> > +#define CONFIG_SYS_CACHELINE_SIZE 64
> > +
> > +#include <asm/arch/vybrid-regs.h>
> > +
> > +/*
> > + * Disabled for now due to build problems under Debian and a
> > +significant
> > + * increase in the final file size: 144260 vs. 109536 Bytes.
> > + */
> > +
> > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> > +#undef CONFIG_SETUP_MEMORY_TAGS
> > +#undef CONFIG_INITRD_TAG
> > +
> > +#undef CONFIG_OF_LIBFDT
> > +
> > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
> > +/* Size of malloc() pool */
> > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 *
> 1024)
> > +
> > +#define CONFIG_BOARD_LATE_INIT
> > +
> > +/* Hardware drivers */
> > +#define CONFIG_VYBRID_UART
> > +#define CONFIG_VYBRID_UART_BASE UART0_BASE
> > +#define CONFIG_VYBRID_GPIO
> > +
> > +/* allow to overwrite serial and ethaddr */ #define
> > +CONFIG_ENV_OVERWRITE
> > +#define CONFIG_SYS_UART_PORT (1)
> > +#define CONFIG_BAUDRATE 115200
> > +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600,
> 115200}
> > +
> > +/* Command definition */
> > +#include <config_cmd_default.h>
> > +
> > +#define CONFIG_CMD_BDI /* bdinfo */
> > +#define CONFIG_CMD_BOOTD
> > +#define CONFIG_CMD_CONSOLE /* coninfo */
> > +#define CONFIG_CMD_DHCP
> > +#define CONFIG_CMD_ELF
> > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest
> */
> > +#define CONFIG_CMD_MISC
> > +#define CONFIG_CMD_MII
> > +#define CONFIG_CMD_NET
> > +#undef CONFIG_CMD_NFS /* NFS support */
> > +#define CONFIG_CMD_PING
> > +#undef CONFIG_CMD_NAND
> > +#undef CONFIG_CMD_DATE
> > +#undef CONFIG_CMD_IMI /* iminfo */
> > +#undef CONFIG_CMD_IMLS
> > +#undef CONFIG_CMD_LOADB /* loadb */
> > +#undef CONFIG_CMD_LOADS /* loads */
> > +
> > +#define CONFIG_SYS_TEXT_BASE 0x3f000800
> > +
> > +#define CONFIG_MMC
> > +#ifdef CONFIG_MMC
> > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
> > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> > +
> > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define
> > +CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define
> > +CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
> > +
> > +#define CONFIG_CMD_MMC
> > +#define CONFIG_GENERIC_MMC
> > +#define CONFIG_CMD_FAT
> > +#define CONFIG_DOS_PARTITION
> > +#endif
> > +
> > +/*
> > + * NAND FLASH
> > + */
> > +#ifdef CONFIG_CMD_NAND
> > +#define CONFIG_MTD_NAND_FSL_NFC_SWECC 1
> > +#define CONFIG_JFFS2_NAND
> > +#define CONFIG_NAND_FSL_NFC
> > +#define CONFIG_SYS_NAND_BASE 0x400E0000
> > +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
> > +#define CONFIG_SYS_NAND_SELECT_DEVICE
> > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> > +#endif
> > +
> > +#define CONFIG_QUAD_SPI
> > +
> > +/* Network configuration */
> > +#define CONFIG_MCFFEC
> > +#ifdef CONFIG_MCFFEC
> > +# define CONFIG_MII 1
> > +# define CONFIG_MII_INIT 1
> > +# define CONFIG_SYS_DISCOVER_PHY
> > +# define CONFIG_SYS_RX_ETH_BUFFER 8
> > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> > +
> > +# define CONFIG_SYS_FEC0_PINMUX 0
> > +# define CONFIG_SYS_FEC1_PINMUX 0
> > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
> > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
> > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
> > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
> > +# define MCFFEC_TOUT_LOOP 50000
> > +# undef CONFIG_HAS_ETH1
> > +
> > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
> > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
> > +# define CONFIG_ETHPRIME "FEC0"
> > +# define CONFIG_IPADDR 10.81.67.175
> > +# define CONFIG_NETMASK 255.255.252.0
> > +# define CONFIG_SERVERIP 10.81.64.153
> > +# define CONFIG_GATEWAYIP 10.81.67.254
> > +# define CONFIG_OVERWRITE_ETHADDR_ONCE
> > +
> > +/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
> > +# ifndef CONFIG_SYS_DISCOVER_PHY
> > +# define FECDUPLEX FULL
> > +# define FECSPEED _100BASET
> > +# else
> > +# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> > +# endif
> > +# endif /* CONFIG_SYS_DISCOVER_PHY */
> > +#endif
> > +
> > +#define CONFIG_BOOTDELAY 3
> > +#define CONFIG_ETHPRIME "FEC0"
> > +#define CONFIG_LOADADDR 0x80010000 /* loadaddr env var
> */
> > +#define CONFIG_ARP_TIMEOUT 200UL
> > +
> > +/* Miscellaneous configurable options */
> > +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +#define CONFIG_SYS_PROMPT "Vybrid U-Boot > "
> > +#undef CONFIG_AUTO_COMPLETE
> > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> > +/* Print Buffer Size */
> > +#define CONFIG_SYS_PBSIZE \
> > + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args
> */
> > +/* Boot Argument Buffer Size */
> > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> > +
> > +#define CONFIG_SYS_MEMTEST_START 0x80010000
> > +#define CONFIG_SYS_MEMTEST_END 0x87C00000
> > +
> > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_HZ 1000
> > +#undef CONFIG_CMDLINE_EDITING
> > +
> > +#define CONFIG_PRAM 2048
> > +
> > +/*
> > + * Stack sizes
> > + * The stack sizes are set up in start.S using the settings below */
> > +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
> > +
> > +/* Physical Memory Map */
> > +#define CONFIG_NR_DRAM_BANKS 1
> > +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
> > +
> > +#define CONFIG_SYS_SDRAM_BASE (0x80000000)
> > +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> > +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> > +
> > +#define CONFIG_BOARD_EARLY_INIT_F
> > +
> > +#define CONFIG_SYS_INIT_SP_OFFSET \
> > + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define
> > +CONFIG_SYS_INIT_SP_ADDR \
> > + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> > +
> > +/* timer */
> > +#define FTM_BASE_ADDR FTM0_BASE_ADDR
> > +#define CONFIG_TMR_USEPIT
> > +
> > +/* clock/PLL configuration */
> > +/* uart0-2 */
> > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
> > +/* crc, pit, ftm0/1, a5/m4 wdog */
> > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
> > +/* lptmr, qspi0, iomuxc, gpio */
> > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
> > +/* anadig, scscm*/
> > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
> > +/* acrc, i2c0/1, wkup, ccm, gpc, src */
> > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
> > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
> > +/* ocotp, snvs, wdog_snvs, ddrmc */
> > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
> > +/* usb1, sdhc0/1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
> > +/* qspi1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
> > +/* enet0/1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
> > +/* nfc */
> > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
> > +/* caam */
> > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
> > +
> > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
> > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
> > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
> > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
> > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
> > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
> > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
> > +
> > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
> > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
> > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
> > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000
> > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
> > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
> > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
> > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
> > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
> > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
> > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
> > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
> > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
> > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
> > +
> > +/* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH
> > +
> > +#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
> > +#define CONFIG_ENV_SIZE (8 * 1024)
> > +#define CONFIG_ENV_IS_IN_MMC
> > +#define CONFIG_SYS_MMC_ENV_DEV 0
> > +
> > +#endif
> > diff --git a/include/configs/vybrid_iram.h
> > b/include/configs/vybrid_iram.h new file mode 100644 index
> > 0000000..f88050e
> > --- /dev/null
> > +++ b/include/configs/vybrid_iram.h
> > @@ -0,0 +1,284 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * Configuration settings for the vybrid Board
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
>
> As the name suggest, I am expecting that <soc>_iram.h contains the layout
> of the internal RAM, IRAM on Freescale's SOC. So the name is inconsistent
> with a board name.
>
> > +#ifndef __CONFIG_H
> > +#define __CONFIG_H
> > +
> > +/* High Level Configuration Options */
> > +
> > +#define CONFIG_VYBRID
> > +
> > +#define CONFIG_SYS_VYBRID_HCLK 24000000
> > +#define CONFIG_SYS_VYBRID_CLK32 32768
>
> As I have already said, each CONFIG_SYS must be documented. Anyway, we
> get rid of these two defines in MX2x / MX3 /.. Do we really need them ?
[Alison Wang] Agree, I will remove these two defines in the next version patches. Thanks.
>
> > +#define CONFIG_SYS_UBOOT_IN_GPURAM
>
> ???
>
> > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
> > +#undef CONFIG_SETUP_MEMORY_TAGS
> > +#undef CONFIG_INITRD_TAG
> > +
> > +#undef CONFIG_OF_LIBFDT
> > +
> > +#define CONFIG_MACH_TYPE MACH_TYPE_VYBRID_VF6XX
>
> Set MACH_TYPE_VYBRID_VF6XX in this file
[Alison Wang] Agree. Thanks.
>
> > +/* Command definition */
> > +#include <config_cmd_default.h>
> > +
> > +#define CONFIG_CMD_BDI /* bdinfo */
> > +#define CONFIG_CMD_BOOTD
> > +#define CONFIG_CMD_CONSOLE /* coninfo */
> > +#define CONFIG_CMD_DHCP
> > +#define CONFIG_CMD_ELF
> > +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest
> */
> > +#define CONFIG_CMD_MISC
> > +#define CONFIG_CMD_MII
> > +#define CONFIG_CMD_NET
> > +#undef CONFIG_CMD_NFS /* NFS support */
> > +#define CONFIG_CMD_PING
> > +#undef CONFIG_CMD_DATE
> > +#undef CONFIG_CMD_IMI /* iminfo */
> > +#undef CONFIG_CMD_IMLS
> > +#undef CONFIG_CMD_LOADB /* loadb */
> > +#undef CONFIG_CMD_LOADS /* loads */
> > +
> > +#define CONFIG_SYS_TEXT_BASE 0x3f000800
> > +
> > +#define CONFIG_MMC
> > +#ifdef CONFIG_MMC
> > +#define CONFIG_SYS_ESDHC1_BASE ESDHC2_BASE_ADDR
> > +#define CONFIG_SYS_ESDHC2_BASE ESDHC2_BASE_ADDR
> > +#define CONFIG_FSL_ESDHC
> > +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
> > +#define CONFIG_SYS_FSL_ESDHC_NUM 1
> > +
> > +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define
> > +CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define
> > +CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
>
> Maybe correct, but they are up now defined only in PowerPC boards. Do you
> confirm that they are needed ?
[Alison Wang] They are not needed. I will remove them in the next version patches. Thanks.
>
> > +/*
> > + * NAND FLASH
> > + */
> > +#ifdef CONFIG_CMD_NAND
> > +#define CONFIG_JFFS2_NAND
> > +#define CONFIG_NAND_FSL_NFC
> > +#define CONFIG_SYS_NAND_BASE 0x400E0000
> > +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> > +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
> > +#define CONFIG_SYS_NAND_SELECT_DEVICE
> > +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
> > +#endif
>
> Does the board have NAND ? I do not see the nand driver.
[Alison Wang] I will add nand driver later.
>
>
> > +
> > +/* Network configuration */
> > +#define CONFIG_MCFFEC
> > +#ifdef CONFIG_MCFFEC
> > +# define CONFIG_MII 1
> > +# define CONFIG_MII_INIT 1
> > +# define CONFIG_SYS_DISCOVER_PHY
> > +# define CONFIG_SYS_RX_ETH_BUFFER 8
> > +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> > +
> > +# define CONFIG_SYS_FEC0_PINMUX 0
> > +# define CONFIG_SYS_FEC1_PINMUX 0
> > +# define CONFIG_SYS_FEC0_IOBASE MACNET0_BASE_ADDR
> > +# define CONFIG_SYS_FEC1_IOBASE MACNET1_BASE_ADDR
> > +# define CONFIG_SYS_FEC0_MIIBASE MACNET0_BASE_ADDR
> > +# define CONFIG_SYS_FEC1_MIIBASE MACNET0_BASE_ADDR
> > +# define MCFFEC_TOUT_LOOP 50000
> > +# undef CONFIG_HAS_ETH1
> > +
> > +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
> > +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
>
> Do not hardcode network addresses in u-boot
[Alison Wang] Agree. Thanks.
>
> > +/* timer */
> > +#define FTM_BASE_ADDR FTM0_BASE_ADDR
> > +#define CONFIG_TMR_USEPIT
> > +
> > +/* clock/PLL configuration */
> > +/* uart0-2 */
> > +#define CONFIG_SYS_CLKCTL_CCGR0 0x000FC000
> > +/* crc, pit, ftm0/1, a5/m4 wdog */
> > +#define CONFIG_SYS_CLKCTL_CCGR1 0xF00FC0C0
> > +/* lptmr, qspi0, iomuxc, gpio */
> > +#define CONFIG_SYS_CLKCTL_CCGR2 0x0FFF0303
> > +/* anadig, scscm*/
> > +#define CONFIG_SYS_CLKCTL_CCGR3 0x00000033
> > +/* acrc, i2c0/1, wkup, ccm, gpc, src */
> > +#define CONFIG_SYS_CLKCTL_CCGR4 0x33f0f003
> > +#define CONFIG_SYS_CLKCTL_CCGR5 0xFFFFFFFF
> > +/* ocotp, snvs, wdog_snvs, ddrmc */
> > +#define CONFIG_SYS_CLKCTL_CCGR6 0x3003cc00
> > +/* usb1, sdhc0/1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR7 0x0000033c
> > +/* qspi1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR8 0x00000300
> > +/* enet0/1 */
> > +#define CONFIG_SYS_CLKCTL_CCGR9 0x0000000f
> > +/* nfc */
> > +#define CONFIG_SYS_CLKCTL_CCGR10 0x00000003
> > +/* caam */
> > +#define CONFIG_SYS_CLKCTL_CCGR11 0x00000003
> > +
> > +#define CONFIG_SYS_CLKCTRL_CCR 0x00010005
> > +#define CONFIG_SYS_CLKCTRL_CCSR 0x0003FF64
> > +#define CONFIG_SYS_CLKCTRL_CACRR 0x00000810
> > +#define CONFIG_SYS_CLKCTRL_CSCMR1 0x03CA0000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR1 0x01000000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR2 0x30114240
> > +#define CONFIG_SYS_CLKCTRL_CSCDR3 0x00003F1F
> > +#define CONFIG_SYS_CLKCTRL_CSCMR2 0x00000000
> > +#define CONFIG_SYS_CLKCTRL_CSCDR4 0x00000000
> > +#define CONFIG_SYS_CLKCTRL_CLPCR 0x00000078
> > +
> > +#define CONFIG_SYS_ANADIG_USB1_CTRL 0x00012000
> > +#define CONFIG_SYS_ANADIG_USB2_CTRL 0x00012000
> > +#define CONFIG_SYS_ANADIG_528_CTRL 0x00002001
> > +#define CONFIG_SYS_ANADIG_528_SS 0x00000000
> > +#define CONFIG_SYS_ANADIG_528_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_528_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_VID_CTRL 0x00011028
> > +#define CONFIG_SYS_ANADIG_VID_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_VID_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_ENET_CTRL 0x00011001
> > +#define CONFIG_SYS_ANADIG_PFD_USB1 0x1B1D1A1C
> > +#define CONFIG_SYS_ANADIG_PFD_528 0x171C1813
> > +#define CONFIG_SYS_ANADIG_USB1_MISC 0x00000002
> > +#define CONFIG_SYS_ANADIG_USB2_VBUS 0x00100004
> > +#define CONFIG_SYS_ANADIG_USB2_CHRG 0x00000000
> > +#define CONFIG_SYS_ANADIG_USB2_MISC 0x00000002
> > +#define CONFIG_SYS_ANADIG_SYS_CTRL 0x00002001
> > +#define CONFIG_SYS_ANADIG_SYS_SS 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_NUM 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_DENOM 0x00000012
> > +#define CONFIG_SYS_ANADIG_SYS_PFD_528 0x00000000
> > +#define CONFIG_SYS_ANADIG_SYS_PLL_LOCK 0x00000000
> > +
>
> See my previous comments about this stuff.
[Alison Wang] Agree.
>
Thanks a lot!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 3/5] vybrid: add uart driver support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
2013-04-12 6:53 ` [U-Boot] [PATCH 1/5] vybrid: add vybrid CPU support Alison Wang
2013-04-12 6:53 ` [U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support Alison Wang
@ 2013-04-12 6:53 ` Alison Wang
2013-04-12 11:42 ` Fabio Estevam
2013-04-13 20:38 ` Stefano Babic
2013-04-12 6:53 ` [U-Boot] [PATCH 4/5] vybrid: add eSDHC " Alison Wang
` (3 subsequent siblings)
6 siblings, 2 replies; 27+ messages in thread
From: Alison Wang @ 2013-04-12 6:53 UTC (permalink / raw)
To: u-boot
This patch adds uart driver support for vybrid platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/serial/Makefile | 1 +
drivers/serial/serial.c | 2 +
drivers/serial/serial_vybrid.c | 129 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 drivers/serial/serial_vybrid.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index de3f471..776e018 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_VYBRID_UART) += serial_vybrid.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 7922bf0..903a520 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -178,6 +178,7 @@ serial_initfunc(pl01x_serial_initialize);
serial_initfunc(s3c44b0_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
serial_initfunc(sh_serial_initialize);
+serial_initfunc(vybrid_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@@ -272,6 +273,7 @@ void serial_initialize(void)
s3c44b0_serial_initialize();
sa1100_serial_initialize();
sh_serial_initialize();
+ vybrid_serial_initialize();
serial_assign(default_serial_console()->name);
}
diff --git a/drivers/serial/serial_vybrid.c b/drivers/serial/serial_vybrid.c
new file mode 100644
index 0000000..4dd9b52
--- /dev/null
+++ b/drivers/serial/serial_vybrid.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/serial-vybrid.h>
+#include <asm/arch/clock.h>
+
+#ifndef CONFIG_VYBRID_UART_BASE
+#error "define CONFIG_VYBRID_UART_BASE to use the VYBRID UART driver"
+#endif
+
+#define UART_CONSOLE \
+ (CONFIG_VYBRID_UART_BASE + (CONFIG_SYS_UART_PORT * 0x1000))
+
+#ifdef CONFIG_SERIAL_MULTI
+#warning "Vybrid driver does not support MULTI serials."
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void vybrid_serial_setbrg(void)
+{
+ u32 clk = vybrid_get_uartclk();
+ u16 sbr;
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd->baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ out_8((UART_CONSOLE + UBDH), (sbr >> 8));
+ out_8((UART_CONSOLE + UBDL), (sbr & 0xFF));
+}
+
+static int vybrid_serial_getc(void)
+{
+ while (!(in_8(UART_CONSOLE + US1) & US1_RDRF))
+ WATCHDOG_RESET();
+
+ setbits_8((UART_CONSOLE + US1), US1_RDRF);
+
+ return in_8(UART_CONSOLE + UD);
+}
+
+static void vybrid_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(in_8(UART_CONSOLE + US1) & US1_TDRE))
+ WATCHDOG_RESET();
+
+ out_8((UART_CONSOLE + UD), c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int vybrid_serial_tstc(void)
+{
+ if (in_8(UART_CONSOLE + URCFIFO) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int vybrid_serial_init(void)
+{
+ clrbits_8((UART_CONSOLE + UC2), UC2_RE);
+ clrbits_8((UART_CONSOLE + UC2), UC2_TE);
+
+ out_8((UART_CONSOLE + UMODEM), 0);
+ out_8((UART_CONSOLE + UC1), 0);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ out_8((UART_CONSOLE + UC2), (UC2_RE | UC2_TE));
+
+ return 0;
+}
+
+static struct serial_device vybrid_serial_drv = {
+ .name = "vybrid_serial",
+ .start = vybrid_serial_init,
+ .stop = NULL,
+ .setbrg = vybrid_serial_setbrg,
+ .putc = vybrid_serial_putc,
+ .puts = default_serial_puts,
+ .getc = vybrid_serial_getc,
+ .tstc = vybrid_serial_tstc,
+};
+
+void vybrid_serial_initialize(void)
+{
+ serial_register(&vybrid_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &vybrid_serial_drv;
+}
--
1.8.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 3/5] vybrid: add uart driver support
2013-04-12 6:53 ` [U-Boot] [PATCH 3/5] vybrid: add uart driver support Alison Wang
@ 2013-04-12 11:42 ` Fabio Estevam
2013-04-13 20:38 ` Stefano Babic
1 sibling, 0 replies; 27+ messages in thread
From: Fabio Estevam @ 2013-04-12 11:42 UTC (permalink / raw)
To: u-boot
On Fri, Apr 12, 2013 at 3:53 AM, Alison Wang <b18965@freescale.com> wrote:
> This patch adds uart driver support for vybrid platform.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> drivers/serial/Makefile | 1 +
> drivers/serial/serial.c | 2 +
> drivers/serial/serial_vybrid.c | 129 +++++++++++++++++++++++++++++++++++++++++
Do we really need to add a new serial driver?
Can't we re-use the imx serial driver?
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 3/5] vybrid: add uart driver support
2013-04-12 6:53 ` [U-Boot] [PATCH 3/5] vybrid: add uart driver support Alison Wang
2013-04-12 11:42 ` Fabio Estevam
@ 2013-04-13 20:38 ` Stefano Babic
2013-04-28 11:03 ` Wang Huan-B18965
1 sibling, 1 reply; 27+ messages in thread
From: Stefano Babic @ 2013-04-13 20:38 UTC (permalink / raw)
To: u-boot
On 12/04/2013 08:53, Alison Wang wrote:
> This patch adds uart driver support for vybrid platform.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
Hi Alison
> diff --git a/drivers/serial/serial_vybrid.c b/drivers/serial/serial_vybrid.c
> new file mode 100644
> index 0000000..4dd9b52
> --- /dev/null
> +++ b/drivers/serial/serial_vybrid.c
> @@ -0,0 +1,129 @@
> +/*
> + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#include <common.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <serial.h>
> +#include <linux/compiler.h>
> +#include <asm/arch/vybrid-regs.h>
> +#include <asm/arch/serial-vybrid.h>
> +#include <asm/arch/clock.h>
> +
> +#ifndef CONFIG_VYBRID_UART_BASE
> +#error "define CONFIG_VYBRID_UART_BASE to use the VYBRID UART driver"
> +#endif
> +
> +#define UART_CONSOLE \
> + (CONFIG_VYBRID_UART_BASE + (CONFIG_SYS_UART_PORT * 0x1000))
> +
> +#ifdef CONFIG_SERIAL_MULTI
> +#warning "Vybrid driver does not support MULTI serials."
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static void vybrid_serial_setbrg(void)
> +{
> + u32 clk = vybrid_get_uartclk();
> + u16 sbr;
> +
> + if (!gd->baudrate)
> + gd->baudrate = CONFIG_BAUDRATE;
> +
> + sbr = (u16)(clk / (16 * gd->baudrate));
> + /* place adjustment later - n/32 BRFA */
> +
> + out_8((UART_CONSOLE + UBDH), (sbr >> 8));
> + out_8((UART_CONSOLE + UBDL), (sbr & 0xFF));
> +}
> +
> +static int vybrid_serial_getc(void)
> +{
> + while (!(in_8(UART_CONSOLE + US1) & US1_RDRF))
> + WATCHDOG_RESET();
> +
Generally : do not use BASE + offset as here. Use C structures, instead.
We have already ARM accessors (in8 is defined for powerpc). Use
functions in io.h
This driver is very simple, and it is similar to already implemented
drivers. Sure that we cannot reuse other code ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 3/5] vybrid: add uart driver support
2013-04-13 20:38 ` Stefano Babic
@ 2013-04-28 11:03 ` Wang Huan-B18965
0 siblings, 0 replies; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 11:03 UTC (permalink / raw)
To: u-boot
> On 12/04/2013 08:53, Alison Wang wrote:
> > This patch adds uart driver support for vybrid platform.
> >
> > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
>
> Hi Alison
>
> > diff --git a/drivers/serial/serial_vybrid.c
> > b/drivers/serial/serial_vybrid.c new file mode 100644 index
> > 0000000..4dd9b52
> > --- /dev/null
> > +++ b/drivers/serial/serial_vybrid.c
> > @@ -0,0 +1,129 @@
> > +/*
> > + * Copyright 2012-2013 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License as published
> > +by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
> > +02111-1307 USA
> > + *
> > + */
> > +
> > +#include <common.h>
> > +#include <watchdog.h>
> > +#include <asm/io.h>
> > +#include <serial.h>
> > +#include <linux/compiler.h>
> > +#include <asm/arch/vybrid-regs.h>
> > +#include <asm/arch/serial-vybrid.h>
> > +#include <asm/arch/clock.h>
> > +
> > +#ifndef CONFIG_VYBRID_UART_BASE
> > +#error "define CONFIG_VYBRID_UART_BASE to use the VYBRID UART driver"
> > +#endif
> > +
> > +#define UART_CONSOLE \
> > + (CONFIG_VYBRID_UART_BASE + (CONFIG_SYS_UART_PORT * 0x1000))
> > +
> > +#ifdef CONFIG_SERIAL_MULTI
> > +#warning "Vybrid driver does not support MULTI serials."
> > +#endif
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static void vybrid_serial_setbrg(void) {
> > + u32 clk = vybrid_get_uartclk();
> > + u16 sbr;
> > +
> > + if (!gd->baudrate)
> > + gd->baudrate = CONFIG_BAUDRATE;
> > +
> > + sbr = (u16)(clk / (16 * gd->baudrate));
> > + /* place adjustment later - n/32 BRFA */
> > +
> > + out_8((UART_CONSOLE + UBDH), (sbr >> 8));
> > + out_8((UART_CONSOLE + UBDL), (sbr & 0xFF)); }
> > +
> > +static int vybrid_serial_getc(void)
> > +{
> > + while (!(in_8(UART_CONSOLE + US1) & US1_RDRF))
> > + WATCHDOG_RESET();
> > +
>
> Generally : do not use BASE + offset as here. Use C structures, instead.
> We have already ARM accessors (in8 is defined for powerpc). Use functions
> in io.h
[Alison Wang] Agree. I will modify to use C structures and use functions in io.h in the next version patches. Thanks a lot.
>
> This driver is very simple, and it is similar to already implemented
> drivers. Sure that we cannot reuse other code ?
[Alison Wang] As they are different IPs, I don't think we can reuse the UART driver for I.MX family.
>
Thanks!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 4/5] vybrid: add eSDHC driver support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
` (2 preceding siblings ...)
2013-04-12 6:53 ` [U-Boot] [PATCH 3/5] vybrid: add uart driver support Alison Wang
@ 2013-04-12 6:53 ` Alison Wang
2013-04-13 20:41 ` Stefano Babic
2013-04-12 6:53 ` [U-Boot] [PATCH 5/5] vybrid: add ethernet " Alison Wang
` (2 subsequent siblings)
6 siblings, 1 reply; 27+ messages in thread
From: Alison Wang @ 2013-04-12 6:53 UTC (permalink / raw)
To: u-boot
This patch adds eSDHC driver support for vybrid platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
drivers/mmc/fsl_esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 35f879e..f258868 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
@@ -479,7 +479,7 @@ static int esdhc_init(struct mmc *mmc)
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
-#ifndef ARCH_MXC
+#if !defined(ARCH_MXC) && !defined(CONFIG_VYBRID)
/* Enable cache snooping */
esdhc_write32(®s->scr, 0x00000040);
#endif
--
1.8.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 4/5] vybrid: add eSDHC driver support
2013-04-12 6:53 ` [U-Boot] [PATCH 4/5] vybrid: add eSDHC " Alison Wang
@ 2013-04-13 20:41 ` Stefano Babic
2013-04-28 11:07 ` Wang Huan-B18965
0 siblings, 1 reply; 27+ messages in thread
From: Stefano Babic @ 2013-04-13 20:41 UTC (permalink / raw)
To: u-boot
On 12/04/2013 08:53, Alison Wang wrote:
> This patch adds eSDHC driver support for vybrid platform.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> drivers/mmc/fsl_esdhc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 35f879e..f258868 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> + * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc
I do not think you can change the Copyright line only for adding a line
of code.
> -#ifndef ARCH_MXC
> +#if !defined(ARCH_MXC) && !defined(CONFIG_VYBRID)
> /* Enable cache snooping */
> esdhc_write32(®s->scr, 0x00000040);
> #endif
I am also not sure if we need CONFIG_VYBRID (but then it should be
ARCH_VYBRID) or we can let flow these processors into the i.MX family.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 4/5] vybrid: add eSDHC driver support
2013-04-13 20:41 ` Stefano Babic
@ 2013-04-28 11:07 ` Wang Huan-B18965
0 siblings, 0 replies; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 11:07 UTC (permalink / raw)
To: u-boot
>
> On 12/04/2013 08:53, Alison Wang wrote:
> > This patch adds eSDHC driver support for vybrid platform.
> >
> > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > ---
> > drivers/mmc/fsl_esdhc.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index
> > 35f879e..f258868 100644
> > --- a/drivers/mmc/fsl_esdhc.c
> > +++ b/drivers/mmc/fsl_esdhc.c
> > @@ -1,5 +1,5 @@
> > /*
> > - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> > + * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc
>
> I do not think you can change the Copyright line only for adding a line
> of code.
[Alison Wang] Agree.
>
> > -#ifndef ARCH_MXC
> > +#if !defined(ARCH_MXC) && !defined(CONFIG_VYBRID)
> > /* Enable cache snooping */
> > esdhc_write32(®s->scr, 0x00000040); #endif
>
> I am also not sure if we need CONFIG_VYBRID (but then it should be
> ARCH_VYBRID) or we can let flow these processors into the i.MX family.
[Alison Wang] Agree, I will remove this modification and let Vybrid into the i.MX family in the next version patches. Thanks.
>
Thanks!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 5/5] vybrid: add ethernet driver support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
` (3 preceding siblings ...)
2013-04-12 6:53 ` [U-Boot] [PATCH 4/5] vybrid: add eSDHC " Alison Wang
@ 2013-04-12 6:53 ` Alison Wang
2013-04-12 11:45 ` Fabio Estevam
2013-04-13 18:31 ` [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Stefano Babic
2013-04-15 2:03 ` Liu Hui-R64343
6 siblings, 1 reply; 27+ messages in thread
From: Alison Wang @ 2013-04-12 6:53 UTC (permalink / raw)
To: u-boot
This patch adds ethernet driver support for vybrid platform.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/arm/include/asm/fec.h | 302 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/u-boot.h | 3 +
drivers/net/mcffec.c | 18 ++-
drivers/net/mcfmii.c | 5 +-
4 files changed, 322 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/fec.h
diff --git a/arch/arm/include/asm/fec.h b/arch/arm/include/asm/fec.h
new file mode 100644
index 0000000..5bb946e
--- /dev/null
+++ b/arch/arm/include/asm/fec.h
@@ -0,0 +1,302 @@
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ *
+ * Add FEC Structure and definitions
+ * Copyright 2004-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef fec_h
+#define fec_h
+
+/* Buffer descriptors used FEC */
+typedef struct cpm_buf_desc {
+ ushort cbd_datlen; /* Data length in buffer */
+ ushort cbd_sc; /* Status and Control */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive */
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
+#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit */
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/* FEC private information */
+struct fec_info_s {
+ int index;
+ u32 iobase;
+ u32 pinmux;
+ u32 miibase;
+ int phy_addr;
+ int dup_spd;
+ char *phy_name;
+ int phyname_init;
+ cbd_t *rxbd; /* Rx BD */
+ cbd_t *txbd; /* Tx BD */
+ uint rxIdx;
+ uint txIdx;
+ char *txbuf;
+ int initialized;
+ struct fec_info_s *next;
+};
+
+#ifdef CONFIG_MCFFEC
+/* Register read/write struct */
+typedef struct fec {
+ u8 resv0[0x4];
+ u32 eir;
+ u32 eimr;
+ u8 resv1[0x4];
+ u32 rdar;
+ u32 tdar;
+ u8 resv2[0xC];
+ u32 ecr;
+ u8 resv3[0x18];
+ u32 mmfr;
+ u32 mscr;
+ u8 resv4[0x1C];
+ u32 mibc;
+ u8 resv5[0x1C];
+ u32 rcr;
+ u8 resv6[0x3C];
+ u32 tcr;
+ u8 resv7[0x1C];
+ u32 palr;
+ u32 paur;
+ u32 opd;
+ u8 resv8[0x28];
+ u32 iaur;
+ u32 ialr;
+ u32 gaur;
+ u32 galr;
+ u8 resv9[0x1C];
+ u32 tfwr;
+ u8 resv10[0x4];
+ u32 frbr;
+ u32 frsr;
+ u8 resv11[0x2C];
+ u32 erdsr;
+ u32 etdsr;
+ u32 emrbr;
+ u8 resv12[0x74];
+
+ u32 rmon_t_drop;
+ u32 rmon_t_packets;
+ u32 rmon_t_bc_pkt;
+ u32 rmon_t_mc_pkt;
+ u32 rmon_t_crc_align;
+ u32 rmon_t_undersize;
+ u32 rmon_t_oversize;
+ u32 rmon_t_frag;
+ u32 rmon_t_jab;
+ u32 rmon_t_col;
+ u32 rmon_t_p64;
+ u32 rmon_t_p65to127;
+ u32 rmon_t_p128to255;
+ u32 rmon_t_p256to511;
+ u32 rmon_t_p512to1023;
+ u32 rmon_t_p1024to2047;
+ u32 rmon_t_p_gte2048;
+ u32 rmon_t_octets;
+
+ u32 ieee_t_drop;
+ u32 ieee_t_frame_ok;
+ u32 ieee_t_1col;
+ u32 ieee_t_mcol;
+ u32 ieee_t_def;
+ u32 ieee_t_lcol;
+ u32 ieee_t_excol;
+ u32 ieee_t_macerr;
+ u32 ieee_t_cserr;
+ u32 ieee_t_sqe;
+ u32 ieee_t_fdxfc;
+ u32 ieee_t_octets_ok;
+ u8 resv13[0x8];
+
+ u32 rmon_r_drop;
+ u32 rmon_r_packets;
+ u32 rmon_r_bc_pkt;
+ u32 rmon_r_mc_pkt;
+ u32 rmon_r_crc_align;
+ u32 rmon_r_undersize;
+ u32 rmon_r_oversize;
+ u32 rmon_r_frag;
+ u32 rmon_r_jab;
+ u32 rmon_r_resvd_0;
+ u32 rmon_r_p64;
+ u32 rmon_r_p65to127;
+ u32 rmon_r_p128to255;
+ u32 rmon_r_p256to511;
+ u32 rmon_r_p512to1023;
+ u32 rmon_r_p1024to2047;
+ u32 rmon_r_p_gte2048;
+ u32 rmon_r_octets;
+
+ u32 ieee_r_drop;
+ u32 ieee_r_frame_ok;
+ u32 ieee_r_crc;
+ u32 ieee_r_align;
+ u32 ieee_r_macerr;
+ u32 ieee_r_fdxfc;
+ u32 ieee_r_octets_ok;
+} fec_t;
+#endif /* CONFIG_MCFFEC */
+
+#define FEC_EIR_CLEAR_ALL (0xFFF80000)
+#define FEC_EIR_HBERR (0x80000000)
+#define FEC_EIR_BABR (0x40000000)
+#define FEC_EIR_BABT (0x20000000)
+#define FEC_EIR_GRA (0x10000000)
+#define FEC_EIR_TXF (0x08000000)
+#define FEC_EIR_TXB (0x04000000)
+#define FEC_EIR_RXF (0x02000000)
+#define FEC_EIR_RXB (0x01000000)
+#define FEC_EIR_MII (0x00800000)
+#define FEC_EIR_EBERR (0x00400000)
+#define FEC_EIR_LC (0x00200000)
+#define FEC_EIR_RL (0x00100000)
+#define FEC_EIR_UN (0x00080000)
+
+#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
+
+#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
+
+#define FEC_ECR_ETHER_EN (0x00000002)
+#define FEC_ECR_RESET (0x00000001)
+
+#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
+#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
+#define FEC_MMFR_ST_01 (0x40000000)
+#define FEC_MMFR_OP_RD (0x20000000)
+#define FEC_MMFR_OP_WR (0x10000000)
+#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
+#define FEC_MMFR_TA_10 (0x00020000)
+
+#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
+#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
+
+#define FEC_MIBC_MIB_DISABLE (0x80000000)
+#define FEC_MIBC_MIB_IDLE (0x40000000)
+
+#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
+#define FEC_RCR_FCE (0x00000020)
+#define FEC_RCR_BC_REJ (0x00000010)
+#define FEC_RCR_PROM (0x00000008)
+#define FEC_RCR_MII_MODE (0x00000004)
+#define FEC_RCR_DRT (0x00000002)
+#define FEC_RCR_LOOP (0x00000001)
+
+#define FEC_TCR_RFC_PAUSE (0x00000010)
+#define FEC_TCR_TFC_PAUSE (0x00000008)
+#define FEC_TCR_FDEN (0x00000004)
+#define FEC_TCR_HBC (0x00000002)
+#define FEC_TCR_GTS (0x00000001)
+
+#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
+
+#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
+
+#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
+#define FEC_TFWR_X_WMRK_64 (0x01)
+#define FEC_TFWR_X_WMRK_128 (0x02)
+#define FEC_TFWR_X_WMRK_192 (0x03)
+
+#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
+
+#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
+
+#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
+
+#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
+
+#define FEC_RESET_DELAY 100
+#define FEC_RX_TOUT 100
+
+int fecpin_setclear(struct eth_device *dev, int setclear);
+
+#ifdef CONFIG_SYS_DISCOVER_PHY
+void __mii_init(void);
+uint mii_send(uint mii_cmd);
+int mii_discover_phy(struct eth_device *dev);
+int mcffec_miiphy_read(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int mcffec_miiphy_write(const char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+#endif
+
+#endif /* fec_h */
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index 2ba98bc..56c07d8 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -48,6 +48,9 @@ typedef struct bd_info {
ulong start;
ulong size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
+#ifdef CONFIG_VYBRID
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
+#endif
} bd_t;
/* For image.h:image_check_target_arch() */
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index ed7459c..bef33ad 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd at denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007-2013 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -33,7 +33,9 @@
#include <miiphy.h>
#include <asm/fec.h>
+#ifdef CONFIG_COLDFIRE
#include <asm/immap.h>
+#endif
#undef ET_DEBUG
#undef MII_DEBUG
@@ -115,7 +117,7 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
}
if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_VYBRID)
fecp->rcr &= ~0x200; /* disabled 10T base */
#endif
#ifdef MII_DEBUG
@@ -123,7 +125,7 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
#endif
bd->bi_ethspeed = 100;
} else {
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_VYBRID)
fecp->rcr |= 0x200; /* enabled 10T base */
#endif
#ifdef MII_DEBUG
@@ -181,7 +183,7 @@ static int fec_send(struct eth_device *dev, void *packet, int length)
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) {
- udelay(1);
+ udelay(10);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
@@ -514,7 +516,12 @@ int fec_init(struct eth_device *dev, bd_t * bd)
fecp->etdsr = (unsigned int)(&info->txbd[0]);
/* Now enable the transmit and receive processing */
+#ifdef CONFIG_VYBRID
+ /* Big Endian */
+ fecp->ecr |= FEC_ECR_ETHER_EN | 0x100;
+#else
fecp->ecr |= FEC_ECR_ETHER_EN;
+#endif
/* And last, try to fill Rx Buffer Descriptors */
fecp->rdar = 0x01000000; /* Descriptor polling active */
@@ -620,6 +627,7 @@ int mcffec_initialize(bd_t * bis)
/* default speed */
bis->bi_ethspeed = 10;
-
+ /* Ugly workaround for FEC to work in kernel, TODO Jason */
+ mii_init();
return 0;
}
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 5e64dbd..da0951f 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2013 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew at freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -31,7 +31,9 @@
#else
#include <asm/fec.h>
#endif
+#ifdef CONFIG_COLDFIRE
#include <asm/immap.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -83,6 +85,7 @@ phy_info_t phyinfo[] = {
{0x20005CE1, "N83640"}, /* National 83640 */
{0x20005C90, "N83848"}, /* National 83848 */
{0x20005CA2, "N83849"}, /* National 83849 */
+ {0x0007C0F1, "SMSC8720A"}, /* SMSC 8720a */
{0x01814400, "QS6612"}, /* QS6612 */
#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
{CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
--
1.8.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 5/5] vybrid: add ethernet driver support
2013-04-12 6:53 ` [U-Boot] [PATCH 5/5] vybrid: add ethernet " Alison Wang
@ 2013-04-12 11:45 ` Fabio Estevam
0 siblings, 0 replies; 27+ messages in thread
From: Fabio Estevam @ 2013-04-12 11:45 UTC (permalink / raw)
To: u-boot
On Fri, Apr 12, 2013 at 3:53 AM, Alison Wang <b18965@freescale.com> wrote:
> This patch adds ethernet driver support for vybrid platform.
>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> ---
> arch/arm/include/asm/fec.h | 302 ++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/u-boot.h | 3 +
> drivers/net/mcffec.c | 18 ++-
> drivers/net/mcfmii.c | 5 +-
Can't we use the mxc_fec driver here?
In the kernel we have only one FEC driver that is common to Coldfire,
imx and MPC.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
` (4 preceding siblings ...)
2013-04-12 6:53 ` [U-Boot] [PATCH 5/5] vybrid: add ethernet " Alison Wang
@ 2013-04-13 18:31 ` Stefano Babic
2013-04-28 10:01 ` Wang Huan-B18965
2013-04-15 2:03 ` Liu Hui-R64343
6 siblings, 1 reply; 27+ messages in thread
From: Stefano Babic @ 2013-04-13 18:31 UTC (permalink / raw)
To: u-boot
On 12/04/2013 08:53, Alison Wang wrote:
> This series contains the support for vybrid CPU and vf600 tower board.
>
> The Vybrid devices are a family of Freescale's latest Dual Single
> Core offering with ARM Cortex A5 and CM4 based processors for
> Advanced Connected Radio, Entry Infotainment, and Cluster as well
> as high end industrial and general purpose applications.
>
>
Hi Alison,
because there is not yet documentation about this family on Freescale's
webiste, could you please mention something more about this processor ?
This helps to better understand where we can put support inside U-Boot.
More or less the following information are very valueable :
- Are there common part (peripheral, controller,..) with other
Freescale's processors ? I doubt there is no point of contact, at least
with i.MX6.
- Which peripheral are reused in this SOC ? I understand in your
patchset that ESDHC is reused, I think also FEC, I wonder that UART is not.
- Which image is produced ? I do not understand why you need a new type
if you reuse the same rule (mkimage for imx) we have.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
2013-04-13 18:31 ` [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Stefano Babic
@ 2013-04-28 10:01 ` Wang Huan-B18965
0 siblings, 0 replies; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 10:01 UTC (permalink / raw)
To: u-boot
> On 12/04/2013 08:53, Alison Wang wrote:
> > This series contains the support for vybrid CPU and vf600 tower board.
> >
> > The Vybrid devices are a family of Freescale's latest Dual Single Core
> > offering with ARM Cortex A5 and CM4 based processors for Advanced
> > Connected Radio, Entry Infotainment, and Cluster as well as high end
> > industrial and general purpose applications.
> >
> >
>
> Hi Alison,
>
> because there is not yet documentation about this family on Freescale's
> webiste, could you please mention something more about this processor ?
>
> This helps to better understand where we can put support inside U-Boot.
>
> More or less the following information are very valueable :
>
> - Are there common part (peripheral, controller,..) with other
> Freescale's processors ? I doubt there is no point of contact, at least
> with i.MX6.
[Alison Wang] This Vybird VF600 family is a heterogeneous dual-core eMPU family combining the ARM(r) Cortex(tm)-A5 and Cortex(tm)-M4 cores. The u-boot and kernel are implemented on the A5 core. So the core is different with current I.MX family. However, this SOC still shares some IPs with I.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI.This SOC also shares some IPs with ColdFire platform, such as eDMA and DSPI. And this SOC still has its own IPs such as PIT, SAI, UART, QSPI and DCU.
More documents for this soc can be found at:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xx&fsrch=1&sr=5
http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID
I will include this kind of descriptions in the next version patches.
Specially for the u-boot porting, the system clock settings such as the CCM and ANADIG, the timer and the iomux on this platform are not identical with the I.MX platform. More following discussions will be put on that. Thanks.
>
> - Which peripheral are reused in this SOC ? I understand in your patchset
> that ESDHC is reused, I think also FEC, I wonder that UART is not.
[Alison Wang] Yes, ESDHC and FEC could be reused with the current code. UART needs to be written as a new driver.
>
> - Which image is produced ? I do not understand why you need a new type
> if you reuse the same rule (mkimage for imx) we have.
>
[Alison Wang] There are still some differences with the I.MX family as described above, so I used different type in the last patch. I'm trying to align the vybrid with imx platform and this kind of reuse will be found in next version patches.
Thanks a lot!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
2013-04-12 6:53 [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Alison Wang
` (5 preceding siblings ...)
2013-04-13 18:31 ` [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support Stefano Babic
@ 2013-04-15 2:03 ` Liu Hui-R64343
2013-04-28 5:47 ` Wang Huan-B18965
6 siblings, 1 reply; 27+ messages in thread
From: Liu Hui-R64343 @ 2013-04-15 2:03 UTC (permalink / raw)
To: u-boot
>-----Original Message-----
>From: Wang Huan-B18965
>Sent: Friday, April 12, 2013 2:54 PM
>To: u-boot at lists.denx.de
>Cc: sbabic at denx.de; Liu Hui-R64343; Estevam Fabio-R49496
>Subject: [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board
>support
>
>This series contains the support for vybrid CPU and vf600 tower board.
>
>The Vybrid devices are a family of Freescale's latest Dual Single Core
>offering with ARM Cortex A5 and CM4 based processors for Advanced
>Connected Radio, Entry Infotainment, and Cluster as well as high end
>industrial and general purpose applications.
>
>
>Alison Wang (5):
> vybrid: add vybrid CPU support
> vybrid: add Freescale vybrid vf600 tower board support
> vybrid: add uart driver support
> vybrid: add eSDHC driver support
> vybrid: add ethernet driver support
Typically, the sequence for the new CPU/board support is:
- CPU MSL support (clock/iomux/gpio/low level init/
- Driver support,
- Board support,
Jason Liu
>
> Makefile | 8 ++
> arch/arm/cpu/armv7/vybrid-common/Makefile | 46 +++++++
> arch/arm/cpu/armv7/vybrid-common/cpu.c | 127
>++++++++++++++++++
> arch/arm/cpu/armv7/vybrid-common/speed.c | 37 +++++
> arch/arm/cpu/armv7/vybrid-common/timer.c | 140
>+++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/Makefile | 45 +++++++
> arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 ++++++++++
> arch/arm/cpu/armv7/vybrid/clock.c | 278
>++++++++++++++++++++++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/iomux.c | 42 ++++++
> arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 128
>++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/soc.c | 42 ++++++
> arch/arm/include/asm/arch-vybrid/clock.h | 41 ++++++
> arch/arm/include/asm/arch-vybrid/iomux.h | 323
>++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213
>+++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 +++++
> arch/arm/include/asm/arch-vybrid/timer.h | 405
>+++++++++++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 ++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735
>++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>++++++++++++++++++++++++++++
> arch/arm/include/asm/fec.h | 302
>+++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/global_data.h | 3 +
> arch/arm/include/asm/mach-types.h | 56 ++++++++
> arch/arm/include/asm/u-boot.h | 3 +
> board/freescale/vybrid/Makefile | 40 ++++++
> board/freescale/vybrid/vybrid.c | 488
>++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> board/freescale/vybrid/vybridimage.cfg | 44 ++++++
> boards.cfg | 2 +
> drivers/mmc/fsl_esdhc.c | 4 +-
> drivers/net/mcffec.c | 18 ++-
> drivers/net/mcfmii.c | 5 +-
> drivers/serial/Makefile | 1 +
> drivers/serial/serial.c | 2 +
> drivers/serial/serial_vybrid.c | 129
>++++++++++++++++++
> include/configs/vybrid.h | 284
>+++++++++++++++++++++++++++++++++++++++
> include/configs/vybrid_iram.h | 284
>+++++++++++++++++++++++++++++++++++++++
> 34 files changed, 4455 insertions(+), 8 deletions(-) create mode
>100644 arch/arm/cpu/armv7/vybrid-common/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c create mode
>100644 arch/arm/cpu/armv7/vybrid/iomux.c create mode 100644
>arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c create mode 100644
>arch/arm/include/asm/arch-vybrid/clock.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
> create mode 100644 arch/arm/include/asm/fec.h create mode 100644
>board/freescale/vybrid/Makefile create mode 100644
>board/freescale/vybrid/vybrid.c create mode 100644
>board/freescale/vybrid/vybridimage.cfg
> create mode 100644 drivers/serial/serial_vybrid.c create mode 100644
>include/configs/vybrid.h create mode 100644
>include/configs/vybrid_iram.h
>
^ permalink raw reply [flat|nested] 27+ messages in thread* [U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
2013-04-15 2:03 ` Liu Hui-R64343
@ 2013-04-28 5:47 ` Wang Huan-B18965
0 siblings, 0 replies; 27+ messages in thread
From: Wang Huan-B18965 @ 2013-04-28 5:47 UTC (permalink / raw)
To: u-boot
Hi, Liu Hui,
-----Original Message-----
From: Liu Hui-R64343
Sent: Monday, April 15, 2013 10:04 AM
To: Wang Huan-B18965; u-boot at lists.denx.de
Cc: sbabic at denx.de; Estevam Fabio-R49496
Subject: RE: [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
>-----Original Message-----
>From: Wang Huan-B18965
>Sent: Friday, April 12, 2013 2:54 PM
>To: u-boot at lists.denx.de
>Cc: sbabic at denx.de; Liu Hui-R64343; Estevam Fabio-R49496
>Subject: [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board
>support
>
>This series contains the support for vybrid CPU and vf600 tower board.
>
>The Vybrid devices are a family of Freescale's latest Dual Single Core
>offering with ARM Cortex A5 and CM4 based processors for Advanced
>Connected Radio, Entry Infotainment, and Cluster as well as high end
>industrial and general purpose applications.
>
>
>Alison Wang (5):
> vybrid: add vybrid CPU support
> vybrid: add Freescale vybrid vf600 tower board support
> vybrid: add uart driver support
> vybrid: add eSDHC driver support
> vybrid: add ethernet driver support
Typically, the sequence for the new CPU/board support is:
- CPU MSL support (clock/iomux/gpio/low level init/
- Driver support,
- Board support,
[Alison Wang] I will modify in the next version.
Jason Liu
>
> Makefile | 8 ++
> arch/arm/cpu/armv7/vybrid-common/Makefile | 46 +++++++
> arch/arm/cpu/armv7/vybrid-common/cpu.c | 127
>++++++++++++++++++
> arch/arm/cpu/armv7/vybrid-common/speed.c | 37 +++++
> arch/arm/cpu/armv7/vybrid-common/timer.c | 140
>+++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/Makefile | 45 +++++++
> arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 ++++++++++
> arch/arm/cpu/armv7/vybrid/clock.c | 278
>++++++++++++++++++++++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/iomux.c | 42 ++++++
> arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 128
>++++++++++++++++++
> arch/arm/cpu/armv7/vybrid/soc.c | 42 ++++++
> arch/arm/include/asm/arch-vybrid/clock.h | 41 ++++++
> arch/arm/include/asm/arch-vybrid/iomux.h | 323
>++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213
>+++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 +++++
> arch/arm/include/asm/arch-vybrid/timer.h | 405
>+++++++++++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 ++++++++++++
> arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735
>++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>++++++++++++++++++++++++++++
> arch/arm/include/asm/fec.h | 302
>+++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/global_data.h | 3 +
> arch/arm/include/asm/mach-types.h | 56 ++++++++
> arch/arm/include/asm/u-boot.h | 3 +
> board/freescale/vybrid/Makefile | 40 ++++++
> board/freescale/vybrid/vybrid.c | 488
>++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> board/freescale/vybrid/vybridimage.cfg | 44 ++++++
> boards.cfg | 2 +
> drivers/mmc/fsl_esdhc.c | 4 +-
> drivers/net/mcffec.c | 18 ++-
> drivers/net/mcfmii.c | 5 +-
> drivers/serial/Makefile | 1 +
> drivers/serial/serial.c | 2 +
> drivers/serial/serial_vybrid.c | 129
>++++++++++++++++++
> include/configs/vybrid.h | 284
>+++++++++++++++++++++++++++++++++++++++
> include/configs/vybrid_iram.h | 284
>+++++++++++++++++++++++++++++++++++++++
> 34 files changed, 4455 insertions(+), 8 deletions(-) create mode
>100644 arch/arm/cpu/armv7/vybrid-common/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c
> create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile
> create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c
> create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c create mode
>100644 arch/arm/cpu/armv7/vybrid/iomux.c create mode 100644
>arch/arm/cpu/armv7/vybrid/lowlevel_init.S
> create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c create mode 100644
>arch/arm/include/asm/arch-vybrid/clock.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h
> create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h
> create mode 100644 arch/arm/include/asm/fec.h create mode 100644
>board/freescale/vybrid/Makefile create mode 100644
>board/freescale/vybrid/vybrid.c create mode 100644
>board/freescale/vybrid/vybridimage.cfg
> create mode 100644 drivers/serial/serial_vybrid.c create mode 100644
>include/configs/vybrid.h create mode 100644
>include/configs/vybrid_iram.h
>
Thanks!
Best Regards,
Alison Wang
^ permalink raw reply [flat|nested] 27+ messages in thread