* [PATCH v3 00/16] x86: support AVX10
@ 2024-12-11 10:09 Jan Beulich
2024-12-11 10:11 ` [PATCH v3 01/16] x86/CPUID: enable AVX10 leaf Jan Beulich
` (16 more replies)
0 siblings, 17 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:09 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
AVX10.1 is just a re-branding of certain AVX512 (sub)features, i.e.
adds no new instructions. Therefore it's mostly relaxation that needs
doing, plus dealing with the 256-bit-only case that AVX512 itself
does not allow for. Luckily an unnecessary restriction on the mask
register insns was taken out again, simplifying the actual emulator
adjustments quite a bit.
AVX10.2 is adding quite a few new insns, support for which (new in v3)
is roughly added chapter-wise as the spec has them (perhaps not in the
order of the chapters there).
While it probably can be rebased ahead, the series in this form
depends on the previously submitted "[PATCH v5 0/3] x86/CPUID: leaf
pruning". It also is assumed to go on top of "[PATCH v7 0/7] x86emul:
misc additions", albeit at most contextual dependencies ought to exit
there.
I've tried to be very careful in rebasing ahead of other emulator
patches I've been carrying, but almost all testing I've done is with
all of those collectively in place.
01: x86/CPUID: enable AVX10 leaf
02: x86emul: support AVX10.1
03: x86emul/test: use simd_check_avx512*() in main()
04: x86emul/test: drop cpu_has_avx512vl
05: x86emul: AVX10.1 testing
06: x86emul/test: engage AVX512VL via command line option
07: x86emul: support AVX10.2 256-bit embedded rounding / SAE
08: x86emul: support AVX10.2 scalar compare insns
09: x86emul: support AVX10.2 partial copy insns
10: x86emul: support AVX10.2 media insns
11: x86emul: support AVX10.2 minmax insns
12: x86emul: support AVX10.2 media insns
13: x86emul: support AVX10.2 saturating convert insns
14: x86emul: support other AVX10.2 convert insns
15: x86emul: support SIMD MOVRS
16: x86emul: support AVX10.2 forms of SM4 insns
Jan
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 01/16] x86/CPUID: enable AVX10 leaf
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
@ 2024-12-11 10:11 ` Jan Beulich
2024-12-11 10:11 ` [PATCH v3 02/16] x86emul: support AVX10.1 Jan Beulich
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:11 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
This requires bumping the number of basic leaves we support. Apart from
this the logic is modeled as closely as possible after that of leaf 7
handling.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
The gen-cpuid.py adjustment is merely the minimum needed. It's not
really clear to me whether someone turning off e.g. AVX512BW might then
also validly expect AVX10 to be turned off.
Spec version 2 leaves unclear what the xstate components are which would
need enabling for AVX10/256. recalculate_{xstate,misc}() are therefore
conservative for now.
Do we want to synthesize AVX10 in the policy when all necessary AVX512*
features are available, thus allowing migration from an AVX10 host to a
suitable non-AVX10 one?
The prior vsz128 bit is now defined as reserved-at-1: No idea yet how to
represent this.
How a toolstack side equivalent (if any) of the init_dom0_cpuid_policy()
change would look like is entirely unclear to me. How much should we
take from the max policy, and how much should we require the user to
specify (and how would the latter look like)?
---
v3: Re-base.
v2: Add logic to init_dom0_cpuid_policy(). Drop vsz128 field. Re-base.
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -210,7 +210,7 @@ static void recalculate_xstate(struct cp
if ( p->feat.mpx )
xstates |= X86_XCR0_BNDREGS | X86_XCR0_BNDCSR;
- if ( p->feat.avx512f )
+ if ( p->feat.avx512f || (p->feat.avx10 && p->avx10.vsz512) )
xstates |= X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM;
if ( p->feat.pku )
@@ -271,6 +271,16 @@ static void recalculate_misc(struct cpu_
p->basic.raw[0xc] = EMPTY_LEAF;
+ zero_leaves(p->basic.raw, 0xe, 0x23);
+
+ p->avx10.raw[0].b &= 0x000700ff;
+ p->avx10.raw[0].c = p->avx10.raw[0].d = 0;
+ if ( !p->feat.avx10 || !p->avx10.version || !p->avx10.vsz512 )
+ {
+ p->feat.avx10 = false;
+ memset(p->avx10.raw, 0, sizeof(p->avx10.raw));
+ }
+
p->extd.e1d &= ~CPUID_COMMON_1D_FEATURES;
/* Most of Power/RAS hidden from guests. */
@@ -394,6 +404,7 @@ static void __init guest_common_max_leav
{
p->basic.max_leaf = ARRAY_SIZE(p->basic.raw) - 1;
p->feat.max_subleaf = ARRAY_SIZE(p->feat.raw) - 1;
+ p->avx10.max_subleaf = ARRAY_SIZE(p->avx10.raw) - 1;
p->extd.max_leaf = 0x80000000U + ARRAY_SIZE(p->extd.raw) - 1;
}
@@ -402,6 +413,7 @@ static void __init guest_common_default_
{
p->basic.max_leaf = host_cpu_policy.basic.max_leaf;
p->feat.max_subleaf = host_cpu_policy.feat.max_subleaf;
+ p->avx10.max_subleaf = host_cpu_policy.avx10.max_subleaf;
p->extd.max_leaf = host_cpu_policy.extd.max_leaf;
}
@@ -905,6 +917,7 @@ void recalculate_cpuid_policy(struct dom
p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf);
p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
+ p->avx10.max_subleaf = min(p->avx10.max_subleaf, max->avx10.max_subleaf);
p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff,
((p->x86_vendor & (X86_VENDOR_AMD |
X86_VENDOR_HYGON))
@@ -951,6 +964,8 @@ void recalculate_cpuid_policy(struct dom
if ( p->basic.max_leaf < XSTATE_CPUID )
__clear_bit(X86_FEATURE_XSAVE, fs);
+ if ( p->basic.max_leaf < 0x24 )
+ __clear_bit(X86_FEATURE_AVX10, fs);
sanitise_featureset(fs);
@@ -1020,9 +1035,18 @@ void __init init_dom0_cpuid_policy(struc
/* Apply dom0-cpuid= command line settings, if provided. */
if ( dom0_cpuid_cmdline )
{
+ const struct cpu_policy *max = is_pv_domain(d)
+ ? (IS_ENABLED(CONFIG_PV) ? &pv_max_cpu_policy : NULL)
+ : (IS_ENABLED(CONFIG_HVM) ? &hvm_max_cpu_policy : NULL);
uint32_t fs[FSCAPINTS];
unsigned int i;
+ if ( !max )
+ {
+ ASSERT_UNREACHABLE();
+ return;
+ }
+
x86_cpu_policy_to_featureset(p, fs);
for ( i = 0; i < ARRAY_SIZE(fs); ++i )
@@ -1032,6 +1056,13 @@ void __init init_dom0_cpuid_policy(struc
}
x86_cpu_featureset_to_policy(fs, p);
+
+ /*
+ * Default-off features with their own leaves need those leaves
+ * re-populated from the max policy.
+ */
+ if ( p->feat.avx10 )
+ p->avx10 = max->avx10;
}
/*
@@ -1064,6 +1095,8 @@ static void __init __maybe_unused build_
sizeof(raw_cpu_policy.feat.raw));
BUILD_BUG_ON(sizeof(raw_cpu_policy.xstate) !=
sizeof(raw_cpu_policy.xstate.raw));
+ BUILD_BUG_ON(sizeof(raw_cpu_policy.avx10) !=
+ sizeof(raw_cpu_policy.avx10.raw));
BUILD_BUG_ON(sizeof(raw_cpu_policy.extd) !=
sizeof(raw_cpu_policy.extd.raw));
}
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -87,6 +87,15 @@ void guest_cpuid(const struct vcpu *v, u
*res = array_access_nospec(p->xstate.raw, subleaf);
break;
+ case 0x24:
+ ASSERT(p->avx10.max_subleaf < ARRAY_SIZE(p->avx10.raw));
+ if ( subleaf > min_t(uint32_t, p->avx10.max_subleaf,
+ ARRAY_SIZE(p->avx10.raw) - 1) )
+ return;
+
+ *res = array_access_nospec(p->avx10.raw, subleaf);
+ break;
+
default:
*res = array_access_nospec(p->basic.raw, leaf);
break;
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -355,6 +355,7 @@ XEN_CPUFEATURE(UTMR, 15*32
XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instructions */
XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructions */
XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */
+XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector ISA */
/* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */
XEN_CPUFEATURE(RDCL_NO, 16*32+ 0) /*A No Rogue Data Cache Load (Meltdown) */
--- a/xen/include/xen/lib/x86/cpu-policy.h
+++ b/xen/include/xen/lib/x86/cpu-policy.h
@@ -85,11 +85,12 @@ unsigned int x86_cpuid_lookup_vendor(uin
*/
const char *x86_cpuid_vendor_to_str(unsigned int vendor);
-#define CPUID_GUEST_NR_BASIC (0xdu + 1)
+#define CPUID_GUEST_NR_BASIC (0x24u + 1)
#define CPUID_GUEST_NR_CACHE (5u + 1)
#define CPUID_GUEST_NR_FEAT (2u + 1)
#define CPUID_GUEST_NR_TOPO (1u + 1)
#define CPUID_GUEST_NR_XSTATE (62u + 1)
+#define CPUID_GUEST_NR_AVX10 (0u + 1)
#define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1)
#define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1)
#define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \
@@ -255,6 +256,19 @@ struct cpu_policy
} comp[CPUID_GUEST_NR_XSTATE];
} xstate;
+ /* Structured AVX10 information leaf: 0x000000024[xx] */
+ union {
+ struct cpuid_leaf raw[CPUID_GUEST_NR_AVX10];
+ struct {
+ /* Subleaf 0. */
+ uint32_t max_subleaf;
+ uint32_t version:8, :9;
+ bool vsz256:1, vsz512:1;
+ uint32_t :13;
+ uint32_t /* c */:32, /* d */:32;
+ };
+ } avx10;
+
/* Extended leaves: 0x800000xx */
union {
struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD];
--- a/xen/lib/x86/cpuid.c
+++ b/xen/lib/x86/cpuid.c
@@ -123,6 +123,7 @@ void x86_cpu_policy_fill_native(struct c
switch ( i )
{
case 0x4: case 0x7: case 0xb: case 0xd:
+ case 0x24:
/* Multi-invocation leaves. Deferred. */
continue;
}
@@ -216,6 +217,15 @@ void x86_cpu_policy_fill_native(struct c
}
}
+ if ( p->basic.max_leaf >= 0x24 )
+ {
+ cpuid_count_leaf(0x24, 0, &p->avx10.raw[0]);
+
+ for ( i = 1; i <= MIN(p->avx10.max_subleaf,
+ ARRAY_SIZE(p->avx10.raw) - 1); ++i )
+ cpuid_count_leaf(0x24, i, &p->avx10.raw[i]);
+ }
+
/* Extended leaves. */
cpuid_leaf(0x80000000U, &p->extd.raw[0]);
for ( i = 1; i <= MIN(p->extd.max_leaf & 0xffffU,
@@ -285,6 +295,9 @@ void x86_cpu_policy_clear_out_of_range_l
ARRAY_SIZE(p->xstate.raw) - 1);
}
+ if ( p->basic.max_leaf < 0x24 )
+ memset(p->avx10.raw, 0, sizeof(p->avx10.raw));
+
zero_leaves(p->extd.raw,
((p->extd.max_leaf >> 16) == 0x8000
? (p->extd.max_leaf & 0xffff) + 1 : 0),
@@ -297,6 +310,8 @@ void __init x86_cpu_policy_bound_max_lea
min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1);
p->feat.max_subleaf =
min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1);
+ p->avx10.max_subleaf =
+ min_t(uint32_t, p->avx10.max_subleaf, ARRAY_SIZE(p->avx10.raw) - 1);
p->extd.max_leaf = 0x80000000U | min_t(uint32_t, p->extd.max_leaf & 0xffff,
ARRAY_SIZE(p->extd.raw) - 1);
}
@@ -324,6 +339,8 @@ void x86_cpu_policy_shrink_max_leaves(st
*/
p->basic.raw[0xd] = p->xstate.raw[0];
+ p->basic.raw[0x24] = p->avx10.raw[0];
+
for ( i = p->basic.max_leaf; i; --i )
if ( p->basic.raw[i].a | p->basic.raw[i].b |
p->basic.raw[i].c | p->basic.raw[i].d )
@@ -457,6 +474,13 @@ int x86_cpuid_copy_to_buffer(const struc
break;
}
+ case 0x24:
+ for ( subleaf = 0;
+ subleaf <= MIN(p->avx10.max_subleaf,
+ ARRAY_SIZE(p->avx10.raw) - 1); ++subleaf )
+ COPY_LEAF(leaf, subleaf, &p->avx10.raw[subleaf]);
+ break;
+
default:
COPY_LEAF(leaf, XEN_CPUID_NO_SUBLEAF, &p->basic.raw[leaf]);
break;
@@ -549,6 +573,13 @@ int x86_cpuid_copy_from_buffer(struct cp
array_access_nospec(p->xstate.raw, data.subleaf) = l;
break;
+ case 0x24:
+ if ( data.subleaf >= ARRAY_SIZE(p->avx10.raw) )
+ goto out_of_range;
+
+ array_access_nospec(p->avx10.raw, data.subleaf) = l;
+ break;
+
default:
if ( data.subleaf != XEN_CPUID_NO_SUBLEAF )
goto out_of_range;
--- a/xen/lib/x86/policy.c
+++ b/xen/lib/x86/policy.c
@@ -21,6 +21,12 @@ int x86_cpu_policies_are_compatible(cons
if ( guest->feat.max_subleaf > host->feat.max_subleaf )
FAIL_CPUID(7, 0);
+ if ( guest->avx10.version > host->avx10.version ||
+ (guest->avx10.vsz512
+ ? !host->avx10.vsz512
+ : guest->avx10.vsz256 && !host->avx10.vsz256 && !host->avx10.vsz512) )
+ FAIL_CPUID(0x24, 0);
+
if ( guest->extd.max_leaf > host->extd.max_leaf )
FAIL_CPUID(0x80000000U, NA);
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -286,7 +286,7 @@ def crunch_numbers(state):
# enabled. Certain later extensions, acting on 256-bit vectors of
# integers, better depend on AVX2 than AVX.
AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8,
- AVX_VNNI_INT16, SHA512, SM4],
+ AVX_VNNI_INT16, SHA512, SM4, AVX10],
# AVX512F is taken to mean hardware support for 512bit registers
# (which in practice depends on the EVEX prefix to encode) as well
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 02/16] x86emul: support AVX10.1
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
2024-12-11 10:11 ` [PATCH v3 01/16] x86/CPUID: enable AVX10 leaf Jan Beulich
@ 2024-12-11 10:11 ` Jan Beulich
2024-12-11 10:12 ` [PATCH v3 03/16] x86emul/test: use simd_check_avx512*() in main() Jan Beulich
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:11 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper, Roger Pau Monné, Oleksii Kurochko
This requires relaxing various pre-existing AVX512* checks, as AVX10.1
covers all AVX512* except PF, ER, 4FMAPS, 4VNNIW (support for all of
which was removed meanwhile anyway), and VP2INTERSECT. Yet potentially
with only less than 512-bit vector width, while otoh guaranteeing more
narrow widths being available when wider are (i.e. unlike AVX512VL being
an add-on feature on top of AVX512F).
Note that visa_check(), replacing host_and_vcpu_must_have() uses, checks
only the guest capability: We wouldn't expose AVX512* (nor AVX10)
without the hardware supporting it. Similarly in vlen_check() the
original host_and_vcpu_must_have() is reduced to the equivalent of just
vcpu_must_have(). This also simplifies (resulting) code in the test and
fuzzing harnesses, as there the XCR0 checks that are part of
cpu_has_avx512* are only needed in local code, not in the emulator
itself (where respective checking occurs elsewhere anyway, utilizing
emul_test_read_xcr()).
While in most cases the changes to x86_emulate() are entirely
mechanical, for opmask insns earlier unconditional AVX512F checks are
converted into "else" clauses to existing if/else-if ones.
To be certain that no uses remain, also drop respective cpu_has_avx512*
(except in the test harness) and vcpu_has_avx512*().
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Probably avx512_vlen_check() should have the avx512_ prefix dropped, now
that it also covers AVX10. But if so that wants to be either a prereq or
a follow-on patch.
visa_check() won't cover AVX10.2 and higher, but probably we will want
independent checking logic for that anyway.
Spec version 2 still leaves unclear what the xstate components are which
would need enabling for AVX10/256. x86emul_get_fpu() is therefore
untouched for now.
Since it'll be reducing code size, we may want to further convert
host_and_vcpu_must_have() to just vcpu_must_have() where appropriate
(should be [almost?] everywhere).
---
v3: Add ChangeLog entry.
v2: Drop use of vsz128 field. Re-base, in particular over dropping of
Xeon Phi support.
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -18,6 +18,7 @@ The format is based on [Keep a Changelog
- Experimental support for Armv8-R.
- On x86:
- xl suspend/resume subcommands.
+ - Add support for AVX10.1. (Experimental)
### Removed
- On x86:
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -133,29 +133,18 @@ static inline bool boot_cpu_has(unsigned
#define cpu_has_pqe boot_cpu_has(X86_FEATURE_PQE)
#define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL))
#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
-#define cpu_has_avx512f boot_cpu_has(X86_FEATURE_AVX512F)
-#define cpu_has_avx512dq boot_cpu_has(X86_FEATURE_AVX512DQ)
#define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED)
#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
-#define cpu_has_avx512_ifma boot_cpu_has(X86_FEATURE_AVX512_IFMA)
#define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT)
#define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB)
-#define cpu_has_avx512cd boot_cpu_has(X86_FEATURE_AVX512CD)
#define cpu_has_proc_trace boot_cpu_has(X86_FEATURE_PROC_TRACE)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
-#define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW)
-#define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL)
/* CPUID level 0x00000007:0.ecx */
-#define cpu_has_avx512_vbmi boot_cpu_has(X86_FEATURE_AVX512_VBMI)
#define cpu_has_pku boot_cpu_has(X86_FEATURE_PKU)
-#define cpu_has_avx512_vbmi2 boot_cpu_has(X86_FEATURE_AVX512_VBMI2)
#define cpu_has_gfni boot_cpu_has(X86_FEATURE_GFNI)
#define cpu_has_vaes boot_cpu_has(X86_FEATURE_VAES)
#define cpu_has_vpclmulqdq boot_cpu_has(X86_FEATURE_VPCLMULQDQ)
-#define cpu_has_avx512_vnni boot_cpu_has(X86_FEATURE_AVX512_VNNI)
-#define cpu_has_avx512_bitalg boot_cpu_has(X86_FEATURE_AVX512_BITALG)
-#define cpu_has_avx512_vpopcntdq boot_cpu_has(X86_FEATURE_AVX512_VPOPCNTDQ)
#define cpu_has_rdpid boot_cpu_has(X86_FEATURE_RDPID)
#define cpu_has_movdiri boot_cpu_has(X86_FEATURE_MOVDIRI)
#define cpu_has_movdir64b boot_cpu_has(X86_FEATURE_MOVDIR64B)
@@ -180,7 +169,6 @@ static inline bool boot_cpu_has(unsigned
#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)
#define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE)
#define cpu_has_hybrid boot_cpu_has(X86_FEATURE_HYBRID)
-#define cpu_has_avx512_fp16 boot_cpu_has(X86_FEATURE_AVX512_FP16)
#define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS)
/* CPUID level 0x00000007:1.eax */
@@ -188,7 +176,6 @@ static inline bool boot_cpu_has(unsigned
#define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3)
#define cpu_has_sm4 boot_cpu_has(X86_FEATURE_SM4)
#define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI)
-#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16)
#define cpu_has_cmpccxadd boot_cpu_has(X86_FEATURE_CMPCCXADD)
#define cpu_has_avx_ifma boot_cpu_has(X86_FEATURE_AVX_IFMA)
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -562,26 +562,15 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_invpcid() (ctxt->cpuid->feat.invpcid)
#define vcpu_has_rtm() (ctxt->cpuid->feat.rtm)
#define vcpu_has_mpx() (ctxt->cpuid->feat.mpx)
-#define vcpu_has_avx512f() (ctxt->cpuid->feat.avx512f)
-#define vcpu_has_avx512dq() (ctxt->cpuid->feat.avx512dq)
#define vcpu_has_rdseed() (ctxt->cpuid->feat.rdseed)
#define vcpu_has_adx() (ctxt->cpuid->feat.adx)
#define vcpu_has_smap() (ctxt->cpuid->feat.smap)
-#define vcpu_has_avx512_ifma() (ctxt->cpuid->feat.avx512_ifma)
#define vcpu_has_clflushopt() (ctxt->cpuid->feat.clflushopt)
#define vcpu_has_clwb() (ctxt->cpuid->feat.clwb)
-#define vcpu_has_avx512cd() (ctxt->cpuid->feat.avx512cd)
#define vcpu_has_sha() (ctxt->cpuid->feat.sha)
-#define vcpu_has_avx512bw() (ctxt->cpuid->feat.avx512bw)
-#define vcpu_has_avx512vl() (ctxt->cpuid->feat.avx512vl)
-#define vcpu_has_avx512_vbmi() (ctxt->cpuid->feat.avx512_vbmi)
-#define vcpu_has_avx512_vbmi2() (ctxt->cpuid->feat.avx512_vbmi2)
#define vcpu_has_gfni() (ctxt->cpuid->feat.gfni)
#define vcpu_has_vaes() (ctxt->cpuid->feat.vaes)
#define vcpu_has_vpclmulqdq() (ctxt->cpuid->feat.vpclmulqdq)
-#define vcpu_has_avx512_vnni() (ctxt->cpuid->feat.avx512_vnni)
-#define vcpu_has_avx512_bitalg() (ctxt->cpuid->feat.avx512_bitalg)
-#define vcpu_has_avx512_vpopcntdq() (ctxt->cpuid->feat.avx512_vpopcntdq)
#define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid)
#define vcpu_has_movdiri() (ctxt->cpuid->feat.movdiri)
#define vcpu_has_movdir64b() (ctxt->cpuid->feat.movdir64b)
@@ -589,12 +578,10 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect)
#define vcpu_has_serialize() (ctxt->cpuid->feat.serialize)
#define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk)
-#define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16)
#define vcpu_has_sha512() (ctxt->cpuid->feat.sha512)
#define vcpu_has_sm3() (ctxt->cpuid->feat.sm3)
#define vcpu_has_sm4() (ctxt->cpuid->feat.sm4)
#define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni)
-#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16)
#define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd)
#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs)
#define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns)
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1126,19 +1126,40 @@ static unsigned long *decode_vex_gpr(
return decode_gpr(regs, ~vex_reg & (mode_64bit() ? 0xf : 7));
}
-#define avx512_vlen_check(lig) do { \
- switch ( evex.lr ) \
- { \
- default: \
- generate_exception(X86_EXC_UD); \
- case 2: \
- break; \
- case 0: case 1: \
- if ( !(lig) ) \
- host_and_vcpu_must_have(avx512vl); \
- break; \
- } \
-} while ( false )
+#define visa_check(subfeat) \
+ generate_exception_if(!cp->feat.avx512 ## subfeat && !cp->feat.avx10, \
+ X86_EXC_UD)
+
+static bool _vlen_check(
+ const struct x86_emulate_state *s,
+ const struct cpu_policy *cp,
+ bool lig)
+{
+ if ( s->evex.lr > 2 )
+ return false;
+
+ if ( lig )
+ return true;
+
+ if ( cp->feat.avx10 )
+ switch ( s->evex.lr )
+ {
+ case 0:
+ case 1:
+ if ( cp->avx10.vsz256 )
+ return true;
+ /* fall through */
+ case 2:
+ if ( cp->avx10.vsz512 )
+ return true;
+ break;
+ }
+
+ return s->evex.lr == 2 || cp->feat.avx512vl;
+}
+
+#define avx512_vlen_check(lig) \
+ generate_exception_if(!_vlen_check(state, cp, lig), X86_EXC_UD)
static bool is_branch_step(struct x86_emulate_ctxt *ctxt,
const struct x86_emulate_ops *ops)
@@ -1370,7 +1391,9 @@ x86_emulate(
/* KMOV{W,Q} %k<n>, (%rax) */
stb[0] = 0xc4;
stb[1] = 0xe1;
- stb[2] = cpu_has_avx512bw ? 0xf8 : 0x78;
+ stb[2] = cp->feat.avx512bw || cp->feat.avx10
+ ? 0xf8 /* L0.NP.W1 - kmovq */
+ : 0x78 /* L0.NP.W0 - kmovw */;
stb[3] = 0x91;
stb[4] = evex.opmsk << 3;
insn_bytes = 5;
@@ -3395,7 +3418,7 @@ x86_emulate(
(ea.type != OP_REG && evex.brs &&
(evex.pfx & VEX_PREFIX_SCALAR_MASK))),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK);
simd_zmm:
@@ -3451,7 +3474,7 @@ x86_emulate(
generate_exception_if((evex.lr || evex.opmsk || evex.brs ||
evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK)),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( (d & DstMask) != DstMem )
d &= ~TwoOp;
op_bytes = 8;
@@ -3478,7 +3501,7 @@ x86_emulate(
generate_exception_if((evex.brs ||
evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK)),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
avx512_vlen_check(false);
d |= TwoOp;
op_bytes = !(evex.pfx & VEX_PREFIX_DOUBLE_MASK) || evex.lr
@@ -3515,7 +3538,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x64): /* vpblendm{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x65): /* vblendmp{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
avx512f_no_sae:
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
avx512_vlen_check(false);
goto simd_zmm;
@@ -3595,13 +3618,13 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(5, 0x2a): /* vcvtsi2sh r/m,xmm,xmm */
case X86EMUL_OPC_EVEX_F3(5, 0x7b): /* vcvtusi2sh r/m,xmm,xmm */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
/* fall through */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2a): /* vcvtsi2s{s,d} r/m,xmm,xmm */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x7b): /* vcvtusi2s{s,d} r/m,xmm,xmm */
generate_exception_if(evex.opmsk || (ea.type != OP_REG && evex.brs),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
get_fpu(X86EMUL_FPU_zmm);
@@ -3711,7 +3734,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(5, 0x2d): /* vcvtsh2si xmm/mem,reg */
case X86EMUL_OPC_EVEX_F3(5, 0x78): /* vcvttsh2usi xmm/mem,reg */
case X86EMUL_OPC_EVEX_F3(5, 0x79): /* vcvtsh2usi xmm/mem,reg */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
/* fall through */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2c): /* vcvtts{s,d}2si xmm/mem,reg */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2d): /* vcvts{s,d}2si xmm/mem,reg */
@@ -3721,7 +3744,7 @@ x86_emulate(
evex.opmsk ||
(ea.type != OP_REG && evex.brs)),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
get_fpu(X86EMUL_FPU_zmm);
@@ -3787,7 +3810,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX(5, 0x2e): /* vucomish xmm/m16,xmm */
case X86EMUL_OPC_EVEX(5, 0x2f): /* vcomish xmm/m16,xmm */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
/* fall through */
CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */
@@ -3796,7 +3819,7 @@ x86_emulate(
(ea.type != OP_REG && evex.brs) ||
evex.w != evex.pfx),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
get_fpu(X86EMUL_FPU_zmm);
@@ -3940,7 +3963,7 @@ x86_emulate(
case X86EMUL_OPC_VEX(0x0f, 0x4a): /* kadd{w,q} k,k,k */
if ( !vex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
/* fall through */
case X86EMUL_OPC_VEX(0x0f, 0x41): /* kand{w,q} k,k,k */
case X86EMUL_OPC_VEX_66(0x0f, 0x41): /* kand{b,d} k,k,k */
@@ -3956,11 +3979,12 @@ x86_emulate(
generate_exception_if(!vex.l, X86_EXC_UD);
opmask_basic:
if ( vex.w )
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
else if ( vex.pfx )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
+ else
+ visa_check(f);
opmask_common:
- host_and_vcpu_must_have(avx512f);
generate_exception_if(!vex.r || (mode_64bit() && !(vex.reg & 8)) ||
ea.type != OP_REG, X86_EXC_UD);
@@ -3983,13 +4007,14 @@ x86_emulate(
generate_exception_if(vex.l || vex.reg != 0xf, X86_EXC_UD);
goto opmask_basic;
- case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{w,d}{d,q} k,k,k */
+ case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{wd,dq} k,k,k */
generate_exception_if(!vex.l, X86_EXC_UD);
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
goto opmask_common;
case X86EMUL_OPC_VEX_66(0x0f, 0x4b): /* kunpckbw k,k,k */
generate_exception_if(!vex.l || vex.w, X86_EXC_UD);
+ visa_check(f);
goto opmask_common;
#endif /* X86EMUL_NO_SIMD */
@@ -4057,7 +4082,7 @@ x86_emulate(
generate_exception_if((evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK) ||
(ea.type != OP_MEM && evex.brs)),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
avx512_vlen_check(false);
goto simd_zmm;
@@ -4096,12 +4121,12 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F2(0x0f, 0x7a): /* vcvtudq2ps [xyz]mm/mem,[xyz]mm{k} */
/* vcvtuqq2ps [xyz]mm/mem,{x,y}mm{k} */
if ( evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
else
{
case X86EMUL_OPC_EVEX(0x0f, 0x78): /* vcvttp{s,d}2udq [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX(0x0f, 0x79): /* vcvtp{s,d}2udq [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
}
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
@@ -4318,7 +4343,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x0b): /* vpmulhrsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x1c): /* vpabsb [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x1d): /* vpabsw [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = 1 << (b & 1);
goto avx512f_no_sae;
@@ -4350,7 +4375,7 @@ x86_emulate(
generate_exception_if(b != 0x27 && evex.w != (b & 1), X86_EXC_UD);
goto avx512f_no_sae;
}
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = 1 << (ext == ext_0f ? b & 1 : evex.w);
avx512_vlen_check(false);
@@ -4423,7 +4448,7 @@ x86_emulate(
dst.bytes = 2;
/* fall through */
case X86EMUL_OPC_EVEX_66(5, 0x6e): /* vmovw r/m16,xmm */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f, 0x6e): /* vmov{d,q} r/m,xmm */
@@ -4431,7 +4456,7 @@ x86_emulate(
generate_exception_if((evex.lr || evex.opmsk || evex.brs ||
evex.reg != 0xf || !evex.RX),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
get_fpu(X86EMUL_FPU_zmm);
opc = init_evex(stub);
@@ -4489,7 +4514,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F2(0x0f, 0x6f): /* vmovdqu{8,16} [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_F2(0x0f, 0x7f): /* vmovdqu{8,16} [xyz]mm,[xyz]mm/mem{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
elem_bytes = 1 << evex.w;
goto vmovdqa;
@@ -4582,7 +4607,7 @@ x86_emulate(
generate_exception_if(evex.w, X86_EXC_UD);
else
{
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
}
d = (d & ~SrcMask) | SrcMem | TwoOp;
@@ -4830,7 +4855,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(0x0f, 0xe6): /* vcvtdq2pd {x,y}mm/mem,[xyz]mm{k} */
/* vcvtqq2pd [xyz]mm/mem,[xyz]mm{k} */
if ( evex.pfx != vex_f3 )
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
else if ( evex.w )
{
case X86EMUL_OPC_EVEX_66(0x0f, 0x78): /* vcvttps2uqq {x,y}mm/mem,[xyz]mm{k} */
@@ -4841,11 +4866,11 @@ x86_emulate(
/* vcvttpd2qq [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f, 0x7b): /* vcvtps2qq {x,y}mm/mem,[xyz]mm{k} */
/* vcvtpd2qq [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
}
else
{
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
}
if ( ea.type != OP_REG || !evex.brs )
@@ -4883,7 +4908,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */
generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.brs,
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
d |= TwoOp;
op_bytes = 8;
goto simd_zmm;
@@ -4909,19 +4934,21 @@ x86_emulate(
case X86EMUL_OPC_VEX(0x0f, 0x90): /* kmov{w,q} k/mem,k */
case X86EMUL_OPC_VEX_66(0x0f, 0x90): /* kmov{b,d} k/mem,k */
generate_exception_if(vex.l || !vex.r, X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
if ( vex.w )
{
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
op_bytes = 4 << !vex.pfx;
}
else if ( vex.pfx )
{
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
op_bytes = 1;
}
else
+ {
+ visa_check(f);
op_bytes = 2;
+ }
get_fpu(X86EMUL_FPU_opmask);
@@ -4943,14 +4970,15 @@ x86_emulate(
generate_exception_if(vex.l || !vex.r || vex.reg != 0xf ||
ea.type != OP_REG, X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
if ( vex.pfx == vex_f2 )
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
else
{
generate_exception_if(vex.w, X86_EXC_UD);
if ( vex.pfx )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
+ else
+ visa_check(f);
}
get_fpu(X86EMUL_FPU_opmask);
@@ -4982,10 +5010,9 @@ x86_emulate(
dst = ea;
dst.reg = decode_gpr(&_regs, modrm_reg);
- host_and_vcpu_must_have(avx512f);
if ( vex.pfx == vex_f2 )
{
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
dst.bytes = 4 << (mode_64bit() && vex.w);
}
else
@@ -4993,7 +5020,9 @@ x86_emulate(
generate_exception_if(vex.w, X86_EXC_UD);
dst.bytes = 4;
if ( vex.pfx )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
+ else
+ visa_check(f);
}
get_fpu(X86EMUL_FPU_opmask);
@@ -5015,20 +5044,18 @@ x86_emulate(
ASSERT(!state->simd_size);
break;
- case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */
- if ( !vex.w )
- host_and_vcpu_must_have(avx512dq);
- /* fall through */
case X86EMUL_OPC_VEX(0x0f, 0x98): /* kortest{w,q} k,k */
case X86EMUL_OPC_VEX_66(0x0f, 0x98): /* kortest{b,d} k,k */
+ case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */
case X86EMUL_OPC_VEX_66(0x0f, 0x99): /* ktest{b,d} k,k */
generate_exception_if(vex.l || !vex.r || vex.reg != 0xf ||
ea.type != OP_REG, X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
if ( vex.w )
- host_and_vcpu_must_have(avx512bw);
- else if ( vex.pfx )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(bw);
+ else if ( vex.pfx || (b & 1) )
+ visa_check(dq);
+ else
+ visa_check(f);
get_fpu(X86EMUL_FPU_opmask);
@@ -5366,7 +5393,7 @@ x86_emulate(
(evex.pfx & VEX_PREFIX_SCALAR_MASK)) ||
!evex.r || !evex.R || evex.z),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK);
simd_imm8_zmm:
@@ -5410,9 +5437,9 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x22): /* vpinsr{d,q} $imm8,r/m,xmm,xmm */
generate_exception_if(evex.lr || evex.opmsk || evex.brs, X86_EXC_UD);
if ( b & 2 )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
else
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
if ( !mode_64bit() )
evex.w = 0;
memcpy(mmvalp, &src.val, src.bytes);
@@ -5449,7 +5476,7 @@ x86_emulate(
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x25): /* vpternlog{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
avx512f_imm8_no_sae:
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
avx512_vlen_check(false);
goto simd_imm8_zmm;
@@ -5548,7 +5575,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f, 0xe4): /* vpmulhuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f, 0xea): /* vpminsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f, 0xee): /* vpmaxsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = b & 0x10 ? 1 : 2;
goto avx512f_no_sae;
@@ -5773,7 +5800,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x10): /* vpsrlvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x11): /* vpsravw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x12): /* vpsllvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(!evex.w || evex.brs, X86_EXC_UD);
elem_bytes = 2;
goto avx512f_no_sae;
@@ -5783,7 +5810,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(0x0f38, 0x20): /* vpmovswb [xyz]mm,{x,y}mm/mem{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x30): /* vpmovzxbw {x,y}mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_F3(0x0f38, 0x30): /* vpmovwb [xyz]mm,{x,y}mm/mem{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
if ( evex.pfx != vex_f3 )
{
case X86EMUL_OPC_EVEX_66(0x0f38, 0x21): /* vpmovsxbd xmm/mem,[xyz]mm{k} */
@@ -5831,7 +5858,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x13): /* vcvtph2ps {x,y}mm/mem,[xyz]mm{k} */
generate_exception_if(evex.w || (ea.type != OP_REG && evex.brs), X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( !evex.brs )
avx512_vlen_check(false);
op_bytes = 8 << evex.lr;
@@ -5885,7 +5912,7 @@ x86_emulate(
op_bytes = 8;
generate_exception_if(evex.brs, X86_EXC_UD);
if ( !evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
goto avx512_broadcast;
case X86EMUL_OPC_EVEX_66(0x0f38, 0x1a): /* vbroadcastf32x4 m128,{y,z}mm{k} */
@@ -5895,7 +5922,7 @@ x86_emulate(
generate_exception_if(ea.type != OP_MEM || !evex.lr || evex.brs,
X86_EXC_UD);
if ( evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
goto avx512_broadcast;
case X86EMUL_OPC_VEX_66(0x0f38, 0x20): /* vpmovsxbw xmm/mem,{x,y}mm */
@@ -5920,9 +5947,9 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(0x0f38, 0x28): /* vpmovm2{b,w} k,[xyz]mm */
case X86EMUL_OPC_EVEX_F3(0x0f38, 0x38): /* vpmovm2{d,q} k,[xyz]mm */
if ( b & 0x10 )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
else
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.opmsk || ea.type != OP_REG, X86_EXC_UD);
d |= TwoOp;
op_bytes = 16 << evex.lr;
@@ -5965,7 +5992,7 @@ x86_emulate(
fault_suppression = false;
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x44): /* vplzcnt{d,q} [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512cd);
+ visa_check(cd);
goto avx512f_no_sae;
case X86EMUL_OPC_VEX_66(0x0f38, 0x2c): /* vmaskmovps mem,{x,y}mm,{x,y}mm */
@@ -6041,7 +6068,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0xba): /* vfmsub231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbc): /* vfnmadd231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbe): /* vfnmsub231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
goto simd_zmm;
@@ -6060,7 +6087,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbb): /* vfmsub231s{s,d} xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbd): /* vfnmadd231s{s,d} xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbf): /* vfnmsub231s{s,d} xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
@@ -6074,14 +6101,14 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x3a): /* vpminuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x3c): /* vpmaxsb [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x3e): /* vpmaxuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = b & 2 ?: 1;
goto avx512f_no_sae;
case X86EMUL_OPC_EVEX_66(0x0f38, 0x40): /* vpmull{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
if ( evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
goto avx512f_no_sae;
case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */
@@ -6121,7 +6148,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x51): /* vpdpbusds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x52): /* vpdpwssd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x53): /* vpdpwssds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_vnni);
+ visa_check(_vnni);
generate_exception_if(evex.w, X86_EXC_UD);
goto avx512f_no_sae;
@@ -6133,7 +6160,7 @@ x86_emulate(
d |= TwoOp;
/* fall through */
case X86EMUL_OPC_EVEX_F3(0x0f38, 0x52): /* vdpbf16ps [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_bf16);
+ visa_check(_bf16);
generate_exception_if(evex.w, X86_EXC_UD);
op_bytes = 16 << evex.lr;
goto avx512f_no_sae;
@@ -6150,7 +6177,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x4d): /* vrcp14s{s,d} xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x4f): /* vrsqrt14s{s,d} xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(evex.brs, X86_EXC_UD);
avx512_vlen_check(true);
goto simd_zmm;
@@ -6159,16 +6186,16 @@ x86_emulate(
generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x54): /* vpopcnt{b,w} [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_bitalg);
+ visa_check(_bitalg);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x66): /* vpblendm{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = 1 << evex.w;
goto avx512f_no_sae;
case X86EMUL_OPC_EVEX_66(0x0f38, 0x55): /* vpopcnt{d,q} [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_vpopcntdq);
+ visa_check(_vpopcntdq);
goto avx512f_no_sae;
case X86EMUL_OPC_VEX_66(0x0f38, 0x5a): /* vbroadcasti128 m128,ymm */
@@ -6177,14 +6204,14 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} [xyz]mm,[xyz]mm/mem{k} */
- host_and_vcpu_must_have(avx512_vbmi2);
+ visa_check(_vbmi2);
elem_bytes = 1 << evex.w;
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x88): /* vexpandp{s,d} [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x89): /* vpexpand{d,q} [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x8a): /* vcompressp{s,d} [xyz]mm,[xyz]mm/mem{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x8b): /* vpcompress{d,q} [xyz]mm,[xyz]mm/mem{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(evex.brs, X86_EXC_UD);
avx512_vlen_check(false);
/*
@@ -6218,7 +6245,7 @@ x86_emulate(
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x71): /* vpshldv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x73): /* vpshrdv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_vbmi2);
+ visa_check(_vbmi2);
goto avx512f_no_sae;
case X86EMUL_OPC_VEX (0x0f38, 0xb0): /* vcvtneoph2ps mem,[xy]mm */
@@ -6238,16 +6265,16 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x7d): /* vpermt2{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x8d): /* vperm{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
if ( !evex.w )
- host_and_vcpu_must_have(avx512_vbmi);
+ visa_check(_vbmi);
else
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
fault_suppression = false;
goto avx512f_no_sae;
case X86EMUL_OPC_EVEX_66(0x0f38, 0x78): /* vpbroadcastb xmm/m8,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x79): /* vpbroadcastw xmm/m16,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.w || evex.brs, X86_EXC_UD);
op_bytes = elem_bytes = 1 << (b & 1);
/* See the comment at the avx512_broadcast label. */
@@ -6256,14 +6283,14 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x7a): /* vpbroadcastb r32,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x7b): /* vpbroadcastw r32,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.w, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x7c): /* vpbroadcast{d,q} reg,[xyz]mm{k} */
generate_exception_if((ea.type != OP_REG || evex.brs ||
evex.reg != 0xf || !evex.RX),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
avx512_vlen_check(false);
get_fpu(X86EMUL_FPU_zmm);
@@ -6332,7 +6359,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0x83): /* vpmultishiftqb [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
generate_exception_if(!evex.w, X86_EXC_UD);
- host_and_vcpu_must_have(avx512_vbmi);
+ visa_check(_vbmi);
fault_suppression = false;
goto avx512f_no_sae;
@@ -6490,8 +6517,8 @@ x86_emulate(
evex.reg != 0xf ||
modrm_reg == state->sib_index),
X86_EXC_UD);
+ visa_check(f);
avx512_vlen_check(false);
- host_and_vcpu_must_have(avx512f);
get_fpu(X86EMUL_FPU_zmm);
/* Read destination and index registers. */
@@ -6652,8 +6679,8 @@ x86_emulate(
evex.reg != 0xf ||
modrm_reg == state->sib_index),
X86_EXC_UD);
+ visa_check(f);
avx512_vlen_check(false);
- host_and_vcpu_must_have(avx512f);
get_fpu(X86EMUL_FPU_zmm);
/* Read source and index registers. */
@@ -6769,7 +6796,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0xb4): /* vpmadd52luq [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xb5): /* vpmadd52huq [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_ifma);
+ visa_check(_ifma);
generate_exception_if(!evex.w, X86_EXC_UD);
goto avx512f_no_sae;
@@ -7239,7 +7266,7 @@ x86_emulate(
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x08): /* vrndscaleps $imm8,[xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x09): /* vrndscalepd $imm8,[xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(evex.w != (b & 1), X86_EXC_UD);
avx512_vlen_check(b & 2);
goto simd_imm8_zmm;
@@ -7248,7 +7275,7 @@ x86_emulate(
generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX(0x0f3a, 0x08): /* vrndscaleph $imm8,[xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
avx512_vlen_check(b & 2);
goto simd_imm8_zmm;
@@ -7361,11 +7388,11 @@ x86_emulate(
evex.opmsk || evex.brs),
X86_EXC_UD);
if ( !(b & 2) )
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
else if ( !(b & 1) )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
else
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
get_fpu(X86EMUL_FPU_zmm);
opc = init_evex(stub);
goto pextr;
@@ -7379,7 +7406,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x39): /* vextracti32x4 $imm8,{y,z}mm,xmm/m128{k} */
/* vextracti64x2 $imm8,{y,z}mm,xmm/m128{k} */
if ( evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
generate_exception_if(evex.brs, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x23): /* vshuff32x4 $imm8,{y,z}mm/mem,{y,z}mm,{y,z}mm{k} */
@@ -7399,7 +7426,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x3b): /* vextracti32x8 $imm8,zmm,ymm/m256{k} */
/* vextracti64x4 $imm8,zmm,ymm/m256{k} */
if ( !evex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
generate_exception_if(evex.lr != 2 || evex.brs, X86_EXC_UD);
fault_suppression = false;
goto avx512f_imm8_no_sae;
@@ -7415,7 +7442,7 @@ x86_emulate(
generate_exception_if((evex.w || evex.reg != 0xf || !evex.RX ||
(ea.type != OP_REG && (evex.z || evex.brs))),
X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
avx512_vlen_check(false);
opc = init_evex(stub);
}
@@ -7507,7 +7534,7 @@ x86_emulate(
if ( !(b & 0x20) )
goto avx512f_imm8_no_sae;
avx512bw_imm:
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
generate_exception_if(evex.brs, X86_EXC_UD);
elem_bytes = 1 << evex.w;
avx512_vlen_check(false);
@@ -7546,7 +7573,7 @@ x86_emulate(
goto simd_0f_imm8_avx;
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x21): /* vinsertps $imm8,xmm/m32,xmm,xmm */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(evex.lr || evex.w || evex.opmsk || evex.brs,
X86_EXC_UD);
op_bytes = 4;
@@ -7554,18 +7581,18 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x50): /* vrangep{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x56): /* vreducep{s,d} $imm8,[xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x26): /* vgetmantp{s,d} $imm8,[xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x54): /* vfixupimmp{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
goto simd_imm8_zmm;
case X86EMUL_OPC_EVEX(0x0f3a, 0x26): /* vgetmantph $imm8,[xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX(0x0f3a, 0x56): /* vreduceph $imm8,[xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
@@ -7573,11 +7600,11 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x51): /* vranges{s,d} $imm8,xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x57): /* vreduces{s,d} $imm8,xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x27): /* vgetmants{s,d} $imm8,xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x55): /* vfixupimms{s,d} $imm8,xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512f);
+ visa_check(f);
generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
@@ -7585,7 +7612,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX(0x0f3a, 0x27): /* vgetmantsh $imm8,xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX(0x0f3a, 0x57): /* vreducesh $imm8,xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
@@ -7596,18 +7623,19 @@ x86_emulate(
case X86EMUL_OPC_VEX_66(0x0f3a, 0x30): /* kshiftr{b,w} $imm8,k,k */
case X86EMUL_OPC_VEX_66(0x0f3a, 0x32): /* kshiftl{b,w} $imm8,k,k */
if ( !vex.w )
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
+ else
+ visa_check(f);
opmask_shift_imm:
generate_exception_if(vex.l || !vex.r || vex.reg != 0xf ||
ea.type != OP_REG, X86_EXC_UD);
- host_and_vcpu_must_have(avx512f);
get_fpu(X86EMUL_FPU_opmask);
op_bytes = 1; /* Any non-zero value will do. */
goto simd_0f_imm8;
case X86EMUL_OPC_VEX_66(0x0f3a, 0x31): /* kshiftr{d,q} $imm8,k,k */
case X86EMUL_OPC_VEX_66(0x0f3a, 0x33): /* kshiftl{d,q} $imm8,k,k */
- host_and_vcpu_must_have(avx512bw);
+ visa_check(bw);
goto opmask_shift_imm;
case X86EMUL_OPC_66(0x0f3a, 0x44): /* pclmulqdq $imm8,xmm/m128,xmm */
@@ -7748,7 +7776,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x66): /* vfpclassp{s,d} $imm8,[xyz]mm/mem,k{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x67): /* vfpclasss{s,d} $imm8,xmm/mem,k{k} */
- host_and_vcpu_must_have(avx512dq);
+ visa_check(dq);
generate_exception_if(!evex.r || !evex.R || evex.z, X86_EXC_UD);
if ( !(b & 1) )
goto avx512f_imm8_no_sae;
@@ -7758,7 +7786,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX(0x0f3a, 0x66): /* vfpclassph $imm8,[xyz]mm/mem,k{k} */
case X86EMUL_OPC_EVEX(0x0f3a, 0x67): /* vfpclasssh $imm8,xmm/mem,k{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD);
if ( !(b & 1) )
goto avx512f_imm8_no_sae;
@@ -7773,14 +7801,14 @@ x86_emulate(
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x71): /* vpshld{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x73): /* vpshrd{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_vbmi2);
+ visa_check(_vbmi2);
goto avx512f_imm8_no_sae;
case X86EMUL_OPC_EVEX_F3(0x0f3a, 0xc2): /* vcmpsh $imm8,xmm/mem,xmm,k{k} */
generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX(0x0f3a, 0xc2): /* vcmpph $imm8,[xyz]mm/mem,[xyz]mm,k{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK);
@@ -7856,13 +7884,13 @@ x86_emulate(
CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5d): /* vmin{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5e): /* vdiv{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5f): /* vmax{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
goto avx512f_all_fp;
CASE_SIMD_ALL_FP(_EVEX, 5, 0x5a): /* vcvtp{h,d}2p{h,d} [xyz]mm/mem,[xyz]mm{k} */
/* vcvts{h,d}2s{h,d} xmm/mem,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
if ( vex.pfx & VEX_PREFIX_SCALAR_MASK )
d &= ~TwoOp;
op_bytes = 2 << (((evex.pfx & VEX_PREFIX_SCALAR_MASK) ? 0 : 1 + evex.lr) +
@@ -7873,7 +7901,7 @@ x86_emulate(
/* vcvtqq2ph [xyz]mm/mem,xmm{k} */
case X86EMUL_OPC_EVEX_F2(5, 0x7a): /* vcvtudq2ph [xyz]mm/mem,[xy]mm{k} */
/* vcvtuqq2ph [xyz]mm/mem,xmm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
op_bytes = 16 << evex.lr;
@@ -7883,7 +7911,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_F3(5, 0x5b): /* vcvttph2dq [xy]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX (5, 0x78): /* vcvttph2udq [xy]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX (5, 0x79): /* vcvtph2udq [xy]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
@@ -7894,7 +7922,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(5, 0x79): /* vcvtph2uqq xmm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x7a): /* vcvttph2qq xmm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x7b): /* vcvtph2qq xmm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
@@ -7931,7 +7959,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(6, 0xba): /* vfmsub231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(6, 0xbc): /* vfnmadd231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(6, 0xbe): /* vfnmsub231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
if ( ea.type != OP_REG || !evex.brs )
avx512_vlen_check(false);
@@ -7953,7 +7981,7 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(6, 0xbb): /* vfmsub231sh xmm/m16,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(6, 0xbd): /* vfnmadd231sh xmm/m16,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(6, 0xbf): /* vfnmsub231sh xmm/m16,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w || (ea.type != OP_REG && evex.brs),
X86_EXC_UD);
if ( !evex.brs )
@@ -7962,13 +7990,13 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(6, 0x4c): /* vrcpph [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(6, 0x4e): /* vrsqrtph [xyz]mm/mem,[xyz]mm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w, X86_EXC_UD);
goto avx512f_no_sae;
case X86EMUL_OPC_EVEX_66(6, 0x4d): /* vrcpsh xmm/m16,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(6, 0x4f): /* vrsqrtsh xmm/m16,xmm,xmm{k} */
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w || evex.brs, X86_EXC_UD);
avx512_vlen_check(true);
goto simd_zmm;
@@ -7986,7 +8014,7 @@ x86_emulate(
{
unsigned int src1 = ~evex.reg;
- host_and_vcpu_must_have(avx512_fp16);
+ visa_check(_fp16);
generate_exception_if(evex.w || ((b & 1) && ea.type != OP_REG && evex.brs),
X86_EXC_UD);
if ( mode_64bit() )
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -795,7 +795,7 @@ static void __init noinline xstate_check
if ( cpu_has_mpx )
check_new_xstate(&s, X86_XCR0_BNDCSR | X86_XCR0_BNDREGS);
- if ( cpu_has_avx512f )
+ if ( boot_cpu_has(X86_FEATURE_AVX512F) || boot_cpu_has(X86_FEATURE_AVX10) )
check_new_xstate(&s, X86_XCR0_HI_ZMM | X86_XCR0_ZMM | X86_XCR0_OPMASK);
/*
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -355,7 +355,7 @@ XEN_CPUFEATURE(UTMR, 15*32
XEN_CPUFEATURE(PREFETCHI, 15*32+14) /*A PREFETCHIT{0,1} Instructions */
XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructions */
XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */
-XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector ISA */
+XEN_CPUFEATURE(AVX10, 15*32+19) /*a AVX10 Converged Vector ISA */
/* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */
XEN_CPUFEATURE(RDCL_NO, 16*32+ 0) /*A No Rogue Data Cache Load (Meltdown) */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 03/16] x86emul/test: use simd_check_avx512*() in main()
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
2024-12-11 10:11 ` [PATCH v3 01/16] x86/CPUID: enable AVX10 leaf Jan Beulich
2024-12-11 10:11 ` [PATCH v3 02/16] x86emul: support AVX10.1 Jan Beulich
@ 2024-12-11 10:12 ` Jan Beulich
2024-12-11 10:12 ` [PATCH v3 04/16] x86emul/test: drop cpu_has_avx512vl Jan Beulich
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:12 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
In preparation for having these also cover AVX10, use the helper
functions in preference of open-coded cpu_has_avx512* for those features
that AVX10 includes. Introduce a couple further helper functions where
they weren't previously needed.
Note that this way simd_check_avx512f_sha_vl() gains an AVX512F check
(which is likely benign) and simd_check_avx512bw_gf_vl() gains an
AVX512BW check (which was clearly missing).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Re-base over dropping of Xeon Phi support.
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -167,6 +167,11 @@ static bool simd_check_avx512vbmi_vl(voi
return cpu_has_avx512_vbmi && cpu_has_avx512vl;
}
+static bool simd_check_avx512vbmi2(void)
+{
+ return cpu_has_avx512_vbmi2;
+}
+
static bool simd_check_sse4_sha(void)
{
return cpu_has_sha && cpu_has_sse4_2;
@@ -179,7 +184,7 @@ static bool simd_check_avx_sha(void)
static bool simd_check_avx512f_sha_vl(void)
{
- return cpu_has_sha && cpu_has_avx512vl;
+ return cpu_has_sha && simd_check_avx512f_vl();
}
static bool simd_check_avx2_vaes(void)
@@ -189,13 +194,13 @@ static bool simd_check_avx2_vaes(void)
static bool simd_check_avx512bw_vaes(void)
{
- return cpu_has_aesni && cpu_has_vaes && cpu_has_avx512bw;
+ return cpu_has_aesni && cpu_has_vaes && simd_check_avx512bw();
}
static bool simd_check_avx512bw_vaes_vl(void)
{
return cpu_has_aesni && cpu_has_vaes &&
- cpu_has_avx512bw && cpu_has_avx512vl;
+ simd_check_avx512bw_vl();
}
static bool simd_check_avx2_vpclmulqdq(void)
@@ -205,22 +210,22 @@ static bool simd_check_avx2_vpclmulqdq(v
static bool simd_check_avx512bw_vpclmulqdq(void)
{
- return cpu_has_vpclmulqdq && cpu_has_avx512bw;
+ return cpu_has_vpclmulqdq && simd_check_avx512bw();
}
static bool simd_check_avx512bw_vpclmulqdq_vl(void)
{
- return cpu_has_vpclmulqdq && cpu_has_avx512bw && cpu_has_avx512vl;
+ return cpu_has_vpclmulqdq && simd_check_avx512bw_vl();
}
static bool simd_check_avx512vbmi2_vpclmulqdq(void)
{
- return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq();
+ return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq();
}
static bool simd_check_avx512vbmi2_vpclmulqdq_vl(void)
{
- return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq_vl();
+ return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq_vl();
}
static bool simd_check_sse2_gf(void)
@@ -235,12 +240,17 @@ static bool simd_check_avx2_gf(void)
static bool simd_check_avx512bw_gf(void)
{
- return cpu_has_gfni && cpu_has_avx512bw;
+ return cpu_has_gfni && simd_check_avx512bw();
}
static bool simd_check_avx512bw_gf_vl(void)
{
- return cpu_has_gfni && cpu_has_avx512vl;
+ return cpu_has_gfni && simd_check_avx512bw_vl();
+}
+
+static bool simd_check_avx512vnni(void)
+{
+ return cpu_has_avx512_vnni;
}
static bool simd_check_avx512fp16(void)
@@ -3195,7 +3205,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovq_to_mem);
@@ -3219,7 +3229,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovq_from_mem);
@@ -3342,7 +3352,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovdqu32 %zmm2,(%ecx){%k1}...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vmovdqu32_to_mem);
@@ -3372,7 +3382,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovdqu32 64(%edx),%zmm2{%k2}...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vmovdqu32_from_mem);
@@ -3397,7 +3407,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovdqu16 %zmm3,(%ecx){%k1}...");
- if ( stack_exec && cpu_has_avx512bw )
+ if ( stack_exec && simd_check_avx512bw() )
{
decl_insn(vmovdqu16_to_mem);
@@ -3429,7 +3439,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovdqu16 64(%edx),%zmm3{%k2}...");
- if ( stack_exec && cpu_has_avx512bw )
+ if ( stack_exec && simd_check_avx512bw() )
{
decl_insn(vmovdqu16_from_mem);
@@ -3557,7 +3567,7 @@ int main(int argc, char **argv)
printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}...");
memset(res, 0x88, 128);
memset(res + 20, 0x77, 8);
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vmovsd_masked_to_mem);
@@ -3592,7 +3602,7 @@ int main(int argc, char **argv)
}
printf("%-40s", "Testing vmovaps (%edx),%zmm7{%k3}{z}...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vmovaps_masked_from_mem);
@@ -3775,7 +3785,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovd_to_mem);
@@ -3800,7 +3810,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovd_from_mem);
@@ -3990,7 +4000,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovd_to_reg);
@@ -4016,7 +4026,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovd_from_reg);
@@ -4118,7 +4128,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovq_to_mem2);
@@ -4208,7 +4218,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovq %xmm22,%rbx...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovq_to_reg);
@@ -4401,7 +4411,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovntdqa 64(%ecx),%zmm4...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vmovntdqa);
@@ -4997,7 +5007,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vcvtph2ps 32(%ecx),%zmm7{%k4}...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(evex_vcvtph2ps);
decl_insn(evex_vcvtps2ph);
@@ -5040,7 +5050,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vfixupimmpd $0,8(%edx){1to8},%zmm3,%zmm4...");
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vfixupimmpd);
static const struct {
@@ -5079,7 +5089,7 @@ int main(int argc, char **argv)
printf("%-40s", "Testing vfpclasspsz $0x46,64(%edx),%k2...");
- if ( stack_exec && cpu_has_avx512dq )
+ if ( stack_exec && simd_check_avx512dq() )
{
decl_insn(vfpclassps);
@@ -5111,7 +5121,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vfpclassphz $0x46,128(%ecx),%k3...");
- if ( stack_exec && cpu_has_avx512_fp16 )
+ if ( stack_exec && simd_check_avx512fp16() )
{
decl_insn(vfpclassph);
@@ -5154,7 +5164,7 @@ int main(int argc, char **argv)
* on the mapping boundaries) that elements controlled by clear mask
* bits don't get accessed.
*/
- if ( stack_exec && cpu_has_avx512f )
+ if ( stack_exec && simd_check_avx512f() )
{
decl_insn(vpcompressd);
decl_insn(vpcompressq);
@@ -5256,7 +5266,7 @@ int main(int argc, char **argv)
}
#if __GNUC__ > 7 /* can't check for __AVX512VBMI2__ here */
- if ( stack_exec && cpu_has_avx512_vbmi2 )
+ if ( stack_exec && simd_check_avx512vbmi2() )
{
decl_insn(vpcompressb);
decl_insn(vpcompressw);
@@ -5444,7 +5454,7 @@ int main(int argc, char **argv)
}
printf("%-40s", "Testing vpdpwssd (%ecx),%{y,z}mmA,%{y,z}mmB...");
- if ( stack_exec && cpu_has_avx512_vnni && cpu_has_avx_vnni )
+ if ( stack_exec && simd_check_avx512vnni() && cpu_has_avx_vnni )
{
/* Do the same operation two ways and compare the results. */
decl_insn(vpdpwssd_vex1);
@@ -5499,7 +5509,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovsh 8(%ecx),%xmm5...");
- if ( stack_exec && cpu_has_avx512_fp16 )
+ if ( stack_exec && simd_check_avx512fp16() )
{
decl_insn(vmovsh_from_mem);
decl_insn(vmovw_to_gpr);
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 04/16] x86emul/test: drop cpu_has_avx512vl
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (2 preceding siblings ...)
2024-12-11 10:12 ` [PATCH v3 03/16] x86emul/test: use simd_check_avx512*() in main() Jan Beulich
@ 2024-12-11 10:12 ` Jan Beulich
2024-12-11 10:13 ` [PATCH v3 05/16] x86emul: AVX10.1 testing Jan Beulich
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:12 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
AVX512VL not being a standalone feature anyway, but always needing
to be combined with some other AVX512*, replace uses of
cpu_has_avx512vl by just the feature bit check.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Re-base over dropping of Xeon Phi support.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -998,7 +998,8 @@ static void test_group(const struct test
{
for ( j = 0; j < nr_vl; ++j )
{
- if ( vl[0] == VL_512 && vl[j] != VL_512 && !cpu_has_avx512vl )
+ if ( vl[0] == VL_512 && vl[j] != VL_512 &&
+ !cpu_policy.feat.avx512vl )
continue;
switch ( tests[i].esz )
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -131,7 +131,7 @@ static bool simd_check_avx512f(void)
static bool simd_check_avx512f_vl(void)
{
- return cpu_has_avx512f && cpu_has_avx512vl;
+ return cpu_has_avx512f && cpu_policy.feat.avx512vl;
}
#define simd_check_avx512vl_sg simd_check_avx512f_vl
@@ -143,7 +143,7 @@ static bool simd_check_avx512dq(void)
static bool simd_check_avx512dq_vl(void)
{
- return cpu_has_avx512dq && cpu_has_avx512vl;
+ return cpu_has_avx512dq && cpu_policy.feat.avx512vl;
}
static bool simd_check_avx512bw(void)
@@ -154,7 +154,7 @@ static bool simd_check_avx512bw(void)
static bool simd_check_avx512bw_vl(void)
{
- return cpu_has_avx512bw && cpu_has_avx512vl;
+ return cpu_has_avx512bw && cpu_policy.feat.avx512vl;
}
static bool simd_check_avx512vbmi(void)
@@ -164,7 +164,7 @@ static bool simd_check_avx512vbmi(void)
static bool simd_check_avx512vbmi_vl(void)
{
- return cpu_has_avx512_vbmi && cpu_has_avx512vl;
+ return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl;
}
static bool simd_check_avx512vbmi2(void)
@@ -260,7 +260,7 @@ static bool simd_check_avx512fp16(void)
static bool simd_check_avx512fp16_vl(void)
{
- return cpu_has_avx512_fp16 && cpu_has_avx512vl;
+ return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl;
}
static void simd_set_regs(struct cpu_user_regs *regs)
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -173,8 +173,6 @@ void wrpkru(unsigned int val);
#define cpu_has_sha cpu_policy.feat.sha
#define cpu_has_avx512bw (cpu_policy.feat.avx512bw && \
xcr0_mask(0xe6))
-#define cpu_has_avx512vl (cpu_policy.feat.avx512vl && \
- xcr0_mask(0xe6))
#define cpu_has_avx512_vbmi (cpu_policy.feat.avx512_vbmi && \
xcr0_mask(0xe6))
#define cpu_has_avx512_vbmi2 (cpu_policy.feat.avx512_vbmi2 && \
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 05/16] x86emul: AVX10.1 testing
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (3 preceding siblings ...)
2024-12-11 10:12 ` [PATCH v3 04/16] x86emul/test: drop cpu_has_avx512vl Jan Beulich
@ 2024-12-11 10:13 ` Jan Beulich
2024-12-11 10:13 ` [PATCH v3 06/16] x86emul/test: engage AVX512VL via command line option Jan Beulich
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:13 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Re-use respective AVX512 tests, by suitably adjusting the predicate
functions. This leaves test names ("Testing ... NN-bit code sequence")
somewhat misleading, but I think we can live with that.
Note that the AVX512{BW,DQ} opmask tests cannot be run as-is for the
AVX10/256 case, as they include 512-bit vector <-> opmask insn tests.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
SDE: -gnr / -gnr256
---
TBD: For AVX10.1/256 need to somehow guarantee that the generated blobs
really don't use 512-bit insns (it's uncertain whether passing
-mprefer-vector-width= is enough). Right now according to my
testing on SDE this is all fine. May need to probe for support of
the new -mno-evex512 compiler option.
The AVX512{BW,DQ} opmask tests could of course be cloned (i.e. rebuilt
another time with -mavx512vl passed) accordingly, but the coverage gain
wouldbe pretty marginal.
---
v2: Drop SDE 9.27.0 workaround. Re-base over dropping of Xeon Phi
support.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -999,7 +999,11 @@ static void test_group(const struct test
for ( j = 0; j < nr_vl; ++j )
{
if ( vl[0] == VL_512 && vl[j] != VL_512 &&
- !cpu_policy.feat.avx512vl )
+ !cpu_policy.feat.avx512vl && !cpu_policy.feat.avx10 )
+ continue;
+
+ if ( vl[j] == VL_512 && !cpu_policy.feat.avx512f &&
+ !cpu_policy.avx10.vsz512 )
continue;
switch ( tests[i].esz )
@@ -1050,6 +1054,27 @@ static void test_group(const struct test
}
}
+/* AVX512 (sub)features implied by AVX10. */
+#define avx10_has_avx512f true
+#define avx10_has_avx512bw true
+#define avx10_has_avx512cd true
+#define avx10_has_avx512dq true
+#define avx10_has_avx512_bf16 true
+#define avx10_has_avx512_bitalg true
+#define avx10_has_avx512_fp16 true
+#define avx10_has_avx512_ifma true
+#define avx10_has_avx512_vbmi true
+#define avx10_has_avx512_vbmi2 true
+#define avx10_has_avx512_vnni true
+#define avx10_has_avx512_vpopcntdq true
+
+/* AVX512 sub-features /not/ implied by AVX10. */
+#define avx10_has_avx512er false
+#define avx10_has_avx512pf false
+#define avx10_has_avx512_4fmaps false
+#define avx10_has_avx512_4vnniw false
+#define avx10_has_avx512_vp2intersect false
+
void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt,
const struct x86_emulate_ops *ops)
{
@@ -1057,8 +1082,8 @@ void evex_disp8_test(void *instr, struct
emulops.read = read;
emulops.write = write;
-#define RUN(feat, vl) do { \
- if ( cpu_has_##feat ) \
+#define run(cond, feat, vl) do { \
+ if ( cond ) \
{ \
printf("%-40s", "Testing " #feat "/" #vl " disp8 handling..."); \
test_group(feat ## _ ## vl, ARRAY_SIZE(feat ## _ ## vl), \
@@ -1067,6 +1092,12 @@ void evex_disp8_test(void *instr, struct
} \
} while ( false )
+#define RUN(feat, vl) \
+ run(cpu_has_ ## feat || \
+ (cpu_has_avx10_1 && cpu_policy.avx10.vsz256 && avx10_has_ ## feat && \
+ (ARRAY_SIZE(vl_ ## vl) > 1 || &vl_ ## vl[0] != &vl_512[0])), \
+ feat, vl)
+
RUN(avx512f, all);
RUN(avx512f, 128);
RUN(avx512f, no128);
@@ -1089,10 +1120,15 @@ void evex_disp8_test(void *instr, struct
RUN(avx512_fp16, all);
RUN(avx512_fp16, 128);
- if ( cpu_has_avx512f )
+#undef RUN
+
+ if ( cpu_has_avx512f || cpu_has_avx10_1 )
{
+#define RUN(feat, vl) run(cpu_has_ ## feat, feat, vl)
RUN(gfni, all);
RUN(vaes, all);
RUN(vpclmulqdq, all);
+#undef RUN
}
+#undef run
}
--- a/tools/tests/x86_emulator/testcase.mk
+++ b/tools/tests/x86_emulator/testcase.mk
@@ -4,7 +4,27 @@ include $(XEN_ROOT)/tools/Rules.mk
$(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS))
-CFLAGS += -fno-builtin -g0 $($(TESTCASE)-cflags)
+ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),)
+
+cflags-vsz64 :=
+cflags-vsz32 := -mprefer-vector-width=256
+cflags-vsz16 := -mprefer-vector-width=128
+# Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only)
+cflags-vsz := -mprefer-vector-width=128
+
+ifneq ($(filter -DVEC_SIZE=%,$($(TESTCASE)-cflags)),)
+CFLAGS-VSZ := $(cflags-vsz$(patsubst -DVEC_SIZE=%,%,$(filter -DVEC_SIZE=%,$($(TESTCASE)-cflags))))
+else
+CFLAGS-VSZ := $(cflags-vsz$(patsubst -DVEC_MAX=%,%,$(filter -DVEC_MAX=%,$($(TESTCASE)-cflags))))
+endif
+
+else
+
+CFLAGS-VSZ :=
+
+endif
+
+CFLAGS += -fno-builtin -g0 $($(TESTCASE)-cflags) $(CFLAGS-VSZ)
LDFLAGS_DIRECT += $(shell { $(LD) -v --warn-rwx-segments; } >/dev/null 2>&1 && echo --no-warn-rwx-segments)
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -124,52 +124,61 @@ static bool simd_check_avx_pclmul(void)
static bool simd_check_avx512f(void)
{
- return cpu_has_avx512f;
+ return cpu_has_avx512f || cpu_has_avx10_1_512;
}
-#define simd_check_avx512f_opmask simd_check_avx512f
#define simd_check_avx512f_sg simd_check_avx512f
+static bool simd_check_avx512f_sc(void)
+{
+ return cpu_has_avx512f || cpu_has_avx10_1;
+}
+#define simd_check_avx512f_opmask simd_check_avx512f_sc
+
static bool simd_check_avx512f_vl(void)
{
- return cpu_has_avx512f && cpu_policy.feat.avx512vl;
+ return (cpu_has_avx512f && cpu_policy.feat.avx512vl) ||
+ cpu_has_avx10_1_256;
}
#define simd_check_avx512vl_sg simd_check_avx512f_vl
static bool simd_check_avx512dq(void)
{
- return cpu_has_avx512dq;
+ return cpu_has_avx512dq || cpu_has_avx10_1_512;
}
#define simd_check_avx512dq_opmask simd_check_avx512dq
static bool simd_check_avx512dq_vl(void)
{
- return cpu_has_avx512dq && cpu_policy.feat.avx512vl;
+ return (cpu_has_avx512dq && cpu_policy.feat.avx512vl) ||
+ cpu_has_avx10_1_256;
}
static bool simd_check_avx512bw(void)
{
- return cpu_has_avx512bw;
+ return cpu_has_avx512bw || cpu_has_avx10_1_512;
}
#define simd_check_avx512bw_opmask simd_check_avx512bw
static bool simd_check_avx512bw_vl(void)
{
- return cpu_has_avx512bw && cpu_policy.feat.avx512vl;
+ return (cpu_has_avx512bw && cpu_policy.feat.avx512vl) ||
+ cpu_has_avx10_1_256;
}
static bool simd_check_avx512vbmi(void)
{
- return cpu_has_avx512_vbmi;
+ return cpu_has_avx512_vbmi || cpu_has_avx10_1_512;
}
static bool simd_check_avx512vbmi_vl(void)
{
- return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl;
+ return (cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl) ||
+ cpu_has_avx10_1_256;
}
static bool simd_check_avx512vbmi2(void)
{
- return cpu_has_avx512_vbmi2;
+ return cpu_has_avx512_vbmi2 || cpu_has_avx10_1_512;
}
static bool simd_check_sse4_sha(void)
@@ -250,17 +259,23 @@ static bool simd_check_avx512bw_gf_vl(vo
static bool simd_check_avx512vnni(void)
{
- return cpu_has_avx512_vnni;
+ return cpu_has_avx512_vnni || cpu_has_avx10_1_512;
}
static bool simd_check_avx512fp16(void)
{
- return cpu_has_avx512_fp16;
+ return cpu_has_avx512_fp16 || cpu_has_avx10_1_512;
+}
+
+static bool simd_check_avx512fp16_sc(void)
+{
+ return cpu_has_avx512_fp16 || cpu_has_avx10_1;
}
static bool simd_check_avx512fp16_vl(void)
{
- return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl;
+ return (cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl) ||
+ cpu_has_avx10_1_256;
}
static void simd_set_regs(struct cpu_user_regs *regs)
@@ -433,9 +448,13 @@ static const struct {
SIMD(OPMASK+DQ/w, avx512dq_opmask, 2),
SIMD(OPMASK+BW/d, avx512bw_opmask, 4),
SIMD(OPMASK+BW/q, avx512bw_opmask, 8),
- SIMD(AVX512F f32 scalar, avx512f, f4),
+#define avx512f_sc_x86_32_D_f4 avx512f_x86_32_D_f4
+#define avx512f_sc_x86_64_D_f4 avx512f_x86_64_D_f4
+ SIMD(AVX512F f32 scalar, avx512f_sc, f4),
SIMD(AVX512F f32x16, avx512f, 64f4),
- SIMD(AVX512F f64 scalar, avx512f, f8),
+#define avx512f_sc_x86_32_D_f8 avx512f_x86_32_D_f8
+#define avx512f_sc_x86_64_D_f8 avx512f_x86_64_D_f8
+ SIMD(AVX512F f64 scalar, avx512f_sc, f8),
SIMD(AVX512F f64x8, avx512f, 64f8),
SIMD(AVX512F s32x16, avx512f, 64i4),
SIMD(AVX512F u32x16, avx512f, 64u4),
@@ -523,7 +542,9 @@ static const struct {
AVX512VL(_VBMI+VL u16x8, avx512vbmi, 16u2),
AVX512VL(_VBMI+VL s16x16, avx512vbmi, 32i2),
AVX512VL(_VBMI+VL u16x16, avx512vbmi, 32u2),
- SIMD(AVX512_FP16 f16 scal,avx512fp16, f2),
+#define avx512fp16_sc_x86_32_D_f2 avx512fp16_x86_32_D_f2
+#define avx512fp16_sc_x86_64_D_f2 avx512fp16_x86_64_D_f2
+ SIMD(AVX512_FP16 f16 scal,avx512fp16_sc, f2),
SIMD(AVX512_FP16 f16x32, avx512fp16, 64f2),
AVX512VL(_FP16+VL f16x8, avx512fp16, 16f2),
AVX512VL(_FP16+VL f16x16,avx512fp16, 32f2),
@@ -3205,7 +3226,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovq_to_mem);
@@ -3229,7 +3250,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovq_from_mem);
@@ -3241,11 +3262,22 @@ int main(int argc, char **argv)
rc = x86_emulate(&ctxt, &emulops);
if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_from_mem) )
goto fail;
- asm ( "vmovq %1, %%xmm1\n\t"
- "vpcmpeqq %%zmm0, %%zmm1, %%k0\n"
- "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
- if ( rc != 0xff )
- goto fail;
+ if ( simd_check_avx512f() )
+ {
+ asm ( "vmovq %1, %%xmm1\n\t"
+ "vpcmpeqq %%zmm0, %%zmm1, %%k0\n"
+ "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0x00ff )
+ goto fail;
+ }
+ else
+ {
+ asm ( "vmovq %1, %%xmm1\n\t"
+ "vpcmpeqq %%xmm0, %%xmm1, %%k0\n"
+ "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0x03 )
+ goto fail;
+ }
printf("okay\n");
}
else
@@ -3567,7 +3599,7 @@ int main(int argc, char **argv)
printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}...");
memset(res, 0x88, 128);
memset(res + 20, 0x77, 8);
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(vmovsd_masked_to_mem);
@@ -3785,7 +3817,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovd_to_mem);
@@ -3810,7 +3842,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovd_from_mem);
@@ -3823,11 +3855,22 @@ int main(int argc, char **argv)
rc = x86_emulate(&ctxt, &emulops);
if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovd_from_mem) )
goto fail;
- asm ( "vmovd %1, %%xmm0\n\t"
- "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t"
- "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
- if ( rc != 0xffff )
- goto fail;
+ if ( simd_check_avx512f() )
+ {
+ asm ( "vmovd %1, %%xmm0\n\t"
+ "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t"
+ "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0xffff )
+ goto fail;
+ }
+ else
+ {
+ asm ( "vmovd %1, %%xmm0\n\t"
+ "vpcmpeqd %%xmm4, %%xmm0, %%k0\n\t"
+ "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0x0f )
+ goto fail;
+ }
printf("okay\n");
}
else
@@ -4000,7 +4043,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovd_to_reg);
@@ -4026,7 +4069,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovd_from_reg);
@@ -4040,11 +4083,22 @@ int main(int argc, char **argv)
rc = x86_emulate(&ctxt, &emulops);
if ( (rc != X86EMUL_OKAY) || !check_eip(evex_vmovd_from_reg) )
goto fail;
- asm ( "vmovd %1, %%xmm0\n\t"
- "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t"
- "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
- if ( rc != 0xffff )
- goto fail;
+ if ( simd_check_avx512f() )
+ {
+ asm ( "vmovd %1, %%xmm0\n\t"
+ "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t"
+ "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0xffff )
+ goto fail;
+ }
+ else
+ {
+ asm ( "vmovd %1, %%xmm0\n\t"
+ "vpcmpeqd %%xmm1, %%xmm0, %%k0\n\t"
+ "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) );
+ if ( rc != 0x0f )
+ goto fail;
+ }
printf("okay\n");
}
else
@@ -4128,7 +4182,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovq_to_mem2);
@@ -4218,7 +4272,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovq %xmm22,%rbx...");
- if ( stack_exec && simd_check_avx512f() )
+ if ( stack_exec && simd_check_avx512f_sc() )
{
decl_insn(evex_vmovq_to_reg);
@@ -5509,7 +5563,7 @@ int main(int argc, char **argv)
printf("skipped\n");
printf("%-40s", "Testing vmovsh 8(%ecx),%xmm5...");
- if ( stack_exec && simd_check_avx512fp16() )
+ if ( stack_exec && simd_check_avx512fp16_sc() )
{
decl_insn(vmovsh_from_mem);
decl_insn(vmovw_to_gpr);
@@ -5527,14 +5581,28 @@ int main(int argc, char **argv)
rc = x86_emulate(&ctxt, &emulops);
if ( (rc != X86EMUL_OKAY) || !check_eip(vmovsh_from_mem) )
goto fail;
- asm volatile ( "kmovw %2, %%k1\n\t"
- "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t"
- "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t"
- "kmovw %%k0, %0"
- : "=g" (rc)
- : "m" (res[2]), "r" (1) );
- if ( rc != 0xffff )
- goto fail;
+ if ( simd_check_avx512fp16() )
+ {
+ asm volatile ( "kmovw %2, %%k1\n\t"
+ "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t"
+ "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t"
+ "kmovw %%k0, %0"
+ : "=g" (rc)
+ : "m" (res[2]), "r" (1) );
+ if ( rc != 0xffff )
+ goto fail;
+ }
+ else
+ {
+ asm volatile ( "kmovb %2, %%k1\n\t"
+ "vmovdqu16 %1, %%xmm4%{%%k1%}%{z%}\n\t"
+ "vpcmpeqw %%xmm4, %%xmm5, %%k0\n\t"
+ "kmovb %%k0, %0"
+ : "=g" (rc)
+ : "m" (res[2]), "r" (1) );
+ if ( rc != 0xff )
+ goto fail;
+ }
printf("okay\n");
printf("%-40s", "Testing vmovsh %xmm4,2(%eax){%k3}...");
--- a/tools/tests/x86_emulator/x86-emulate.c
+++ b/tools/tests/x86_emulator/x86-emulate.c
@@ -244,7 +244,7 @@ int emul_test_get_fpu(
break;
case X86EMUL_FPU_opmask:
case X86EMUL_FPU_zmm:
- if ( cpu_has_avx512f )
+ if ( cpu_has_avx512f || cpu_has_avx10_1 )
break;
default:
return X86EMUL_UNHANDLEABLE;
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -207,6 +207,12 @@ void wrpkru(unsigned int val);
xcr0_mask(6))
#define cpu_has_avx_vnni_int16 (cpu_policy.feat.avx_vnni_int16 && \
xcr0_mask(6))
+ /* TBD: Is bit 6 (ZMM_Hi256) really needed here? */
+#define cpu_has_avx10_1 (cpu_policy.feat.avx10 && xcr0_mask(0xe6))
+#define cpu_has_avx10_1_256 (cpu_has_avx10_1 && \
+ (cpu_policy.avx10.vsz256 || \
+ cpu_policy.avx10.vsz512))
+#define cpu_has_avx10_1_512 (cpu_has_avx10_1 && cpu_policy.avx10.vsz512)
#define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1)
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 06/16] x86emul/test: engage AVX512VL via command line option
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (4 preceding siblings ...)
2024-12-11 10:13 ` [PATCH v3 05/16] x86emul: AVX10.1 testing Jan Beulich
@ 2024-12-11 10:13 ` Jan Beulich
2024-12-11 10:14 ` [PATCH v3 07/16] x86emul: support AVX10.2 256-bit embedded rounding / SAE Jan Beulich
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:13 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Now that we have machinery in testcase.mk to set vector length dependent
flags for AVX512 tests, let's avoid using a pragma to enable AVX512VL
insns for the compiler. This way, correct settings are in place from the
very beginning of compilation.
No change to the generated test blobs, and hence no functional change.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/tools/tests/x86_emulator/simd.h
+++ b/tools/tests/x86_emulator/simd.h
@@ -215,10 +215,6 @@ DECL_OCTET(half);
# define __builtin_ia32_shuf_i32x4_512_mask __builtin_ia32_shuf_i32x4_mask
# define __builtin_ia32_shuf_i64x2_512_mask __builtin_ia32_shuf_i64x2_mask
-# if VEC_SIZE > ELEM_SIZE && (defined(VEC_MAX) ? VEC_MAX : VEC_SIZE) < 64
-# pragma GCC target ( "avx512vl" )
-# endif
-
# define REN(insn, old, new) \
asm ( ".macro v" #insn #old " o:vararg \n\t" \
"v" #insn #new " \\o \n\t" \
--- a/tools/tests/x86_emulator/testcase.mk
+++ b/tools/tests/x86_emulator/testcase.mk
@@ -7,8 +7,8 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDD
ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),)
cflags-vsz64 :=
-cflags-vsz32 := -mprefer-vector-width=256
-cflags-vsz16 := -mprefer-vector-width=128
+cflags-vsz32 := -mavx512vl -mprefer-vector-width=256
+cflags-vsz16 := -mavx512vl -mprefer-vector-width=128
# Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only)
cflags-vsz := -mprefer-vector-width=128
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 07/16] x86emul: support AVX10.2 256-bit embedded rounding / SAE
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (5 preceding siblings ...)
2024-12-11 10:13 ` [PATCH v3 06/16] x86emul/test: engage AVX512VL via command line option Jan Beulich
@ 2024-12-11 10:14 ` Jan Beulich
2024-12-11 10:17 ` [PATCH v3 08/16] x86emul: support AVX10.2 scalar compare insns Jan Beulich
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:14 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
AVX10.2 (along with APX) assigns new meaning to the bit that previsouly
distinguished EVEX from the Phi co-processor's MVEX. Therefore
evex_encoded() now needs to key off of something else: Use the opcode
mapping field for this, leveraging that map 0 has no assigned opcodes
(and appears unlikely to gain any).
Place the check of EVEX.U such that it'll cover most insns. EVEX.b is
being checked for individual insns as applicable - whenever that's valid
for (register-only) 512-bit forms, it becomes valid for 256-bit forms as
well when AVX10.2 is permitted for a guest. Scalar insns permitting
embedded rounding / SAE, otoh, have individual EVEX.U checks added (where
applicable with minor adjustments to the logic to avoid - where easily
possible - testing the same bit multiple times).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
To raise the question early: It is entirely unclear to me how we want to
allow control over the AVX10 minor version number from guest configs, as
that's not a boolean field and hence not suitable for simple bit-wise
masking of feature sets.
---
v3: Take care of scalar insns individually.
v2: New.
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -16,7 +16,7 @@
# define ERR_PTR(val) NULL
#endif
-#define evex_encoded() (s->evex.mbs)
+#define evex_encoded() (s->evex.opcx)
struct x86_emulate_state *
x86_decode_insn(
@@ -1198,8 +1198,15 @@ int x86emul_decode(struct x86_emulate_st
s->evex.raw[1] = s->vex.raw[1];
s->evex.raw[2] = insn_fetch_type(uint8_t);
- generate_exception_if(!s->evex.mbs || s->evex.mbz, X86_EXC_UD);
- generate_exception_if(!s->evex.opmsk && s->evex.z, X86_EXC_UD);
+ /*
+ * .opcx is being checked here just to be on the safe
+ * side, especially as long as evex_encoded() uses
+ * this field.
+ */
+ generate_exception_if(s->evex.mbz || !s->evex.opcx,
+ X86_EXC_UD);
+ generate_exception_if(!s->evex.opmsk && s->evex.z,
+ X86_EXC_UD);
if ( !mode_64bit() )
s->evex.R = 1;
@@ -1777,6 +1784,16 @@ int x86emul_decode(struct x86_emulate_st
if ( override_seg != x86_seg_none )
s->ea.mem.seg = override_seg;
+ /*
+ * While this generic check takes care of most insns, scalar ones (with
+ * EVEX.b set) need checking individually (elsewhere).
+ */
+ generate_exception_if((evex_encoded() &&
+ !s->evex.u &&
+ (s->modrm_mod != 3 ||
+ !vcpu_has_avx10(2) || !s->evex.brs)),
+ X86_EXC_UD);
+
/* Fetch the immediate operand, if present. */
switch ( d & SrcMask )
{
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -225,7 +225,7 @@ union evex {
uint8_t x:1; /* X */
uint8_t r:1; /* R */
uint8_t pfx:2; /* pp */
- uint8_t mbs:1;
+ uint8_t u:1; /* U */
uint8_t reg:4; /* vvvv */
uint8_t w:1; /* W */
uint8_t opmsk:3; /* aaa */
@@ -594,6 +594,8 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16)
#define vcpu_has_user_msr() (ctxt->cpuid->feat.user_msr)
+#define vcpu_has_avx10(minor) (ctxt->cpuid->avx10.version >= (minor))
+
#define vcpu_must_have(feat) \
generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD)
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1241,7 +1241,7 @@ int cf_check x86emul_unhandleable_rw(
#define lock_prefix (state->lock_prefix)
#define vex (state->vex)
#define evex (state->evex)
-#define evex_encoded() (evex.mbs)
+#define evex_encoded() (evex.opcx)
#define ea (state->ea)
/* Undo DEBUG wrapper. */
@@ -3415,8 +3415,8 @@ x86_emulate(
CASE_SIMD_ALL_FP(_EVEX, 0x0f, 0x5f): /* vmax{p,s}{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
avx512f_all_fp:
generate_exception_if((evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK) ||
- (ea.type != OP_REG && evex.brs &&
- (evex.pfx & VEX_PREFIX_SCALAR_MASK))),
+ ((evex.pfx & VEX_PREFIX_SCALAR_MASK) &&
+ (ea.type != OP_REG ? evex.brs : !evex.u))),
X86_EXC_UD);
visa_check(f);
if ( ea.type != OP_REG || !evex.brs )
@@ -3622,11 +3622,12 @@ x86_emulate(
/* fall through */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2a): /* vcvtsi2s{s,d} r/m,xmm,xmm */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x7b): /* vcvtusi2s{s,d} r/m,xmm,xmm */
- generate_exception_if(evex.opmsk || (ea.type != OP_REG && evex.brs),
- X86_EXC_UD);
+ generate_exception_if(evex.opmsk, X86_EXC_UD);
visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
get_fpu(X86EMUL_FPU_zmm);
if ( ea.type == OP_MEM )
@@ -3741,12 +3742,13 @@ x86_emulate(
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x78): /* vcvtts{s,d}2usi xmm/mem,reg */
CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x79): /* vcvts{s,d}2usi xmm/mem,reg */
generate_exception_if((evex.reg != 0xf || !evex.RX || !evex.R ||
- evex.opmsk ||
- (ea.type != OP_REG && evex.brs)),
+ evex.opmsk),
X86_EXC_UD);
visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
get_fpu(X86EMUL_FPU_zmm);
opc = init_evex(stub);
goto cvts_2si;
@@ -3816,12 +3818,13 @@ x86_emulate(
CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */
CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2f): /* vcomis{s,d} xmm/mem,xmm */
generate_exception_if((evex.reg != 0xf || !evex.RX || evex.opmsk ||
- (ea.type != OP_REG && evex.brs) ||
evex.w != evex.pfx),
X86_EXC_UD);
visa_check(f);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
get_fpu(X86EMUL_FPU_zmm);
opc = init_evex(stub);
@@ -5389,8 +5392,8 @@ x86_emulate(
CASE_SIMD_ALL_FP(_EVEX, 0x0f, 0xc2): /* vcmp{p,s}{s,d} $imm8,[xyz]mm/mem,[xyz]mm,k{k} */
generate_exception_if((evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK) ||
- (ea.type != OP_REG && evex.brs &&
- (evex.pfx & VEX_PREFIX_SCALAR_MASK)) ||
+ ((evex.pfx & VEX_PREFIX_SCALAR_MASK) &&
+ (ea.type != OP_REG ? evex.brs : !evex.u)) ||
!evex.r || !evex.R || evex.z),
X86_EXC_UD);
visa_check(f);
@@ -6088,9 +6091,10 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbd): /* vfnmadd231s{s,d} xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0xbf): /* vfnmsub231s{s,d} xmm/mem,xmm,xmm{k} */
visa_check(f);
- generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
goto simd_zmm;
case X86EMUL_OPC_66(0x0f38, 0x37): /* pcmpgtq xmm/m128,xmm */
@@ -7262,7 +7266,8 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x0a): /* vrndscaless $imm8,xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x0b): /* vrndscalesd $imm8,xmm/mem,xmm,xmm{k} */
- generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
+ generate_exception_if(ea.type != OP_REG ? evex.brs : !evex.u,
+ X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x08): /* vrndscaleps $imm8,[xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x09): /* vrndscalepd $imm8,[xyz]mm/mem,[xyz]mm{k} */
@@ -7272,7 +7277,8 @@ x86_emulate(
goto simd_imm8_zmm;
case X86EMUL_OPC_EVEX(0x0f3a, 0x0a): /* vrndscalesh $imm8,xmm/mem,xmm,xmm{k} */
- generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
+ generate_exception_if(ea.type != OP_REG ? evex.brs : !evex.u,
+ X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX(0x0f3a, 0x08): /* vrndscaleph $imm8,[xyz]mm/mem,[xyz]mm{k} */
visa_check(_fp16);
@@ -7605,9 +7611,10 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x27): /* vgetmants{s,d} $imm8,xmm/mem,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(0x0f3a, 0x55): /* vfixupimms{s,d} $imm8,xmm/mem,xmm,xmm{k} */
visa_check(f);
- generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
goto simd_imm8_zmm;
case X86EMUL_OPC_EVEX(0x0f3a, 0x27): /* vgetmantsh $imm8,xmm/mem,xmm,xmm{k} */
@@ -7617,7 +7624,7 @@ x86_emulate(
if ( !evex.brs )
avx512_vlen_check(true);
else
- generate_exception_if(ea.type != OP_REG, X86_EXC_UD);
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
goto simd_imm8_zmm;
case X86EMUL_OPC_VEX_66(0x0f3a, 0x30): /* kshiftr{b,w} $imm8,k,k */
@@ -7805,7 +7812,7 @@ x86_emulate(
goto avx512f_imm8_no_sae;
case X86EMUL_OPC_EVEX_F3(0x0f3a, 0xc2): /* vcmpsh $imm8,xmm/mem,xmm,k{k} */
- generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD);
+ generate_exception_if(ea.type != OP_REG ? evex.brs : !evex.u, X86_EXC_UD);
/* fall through */
case X86EMUL_OPC_EVEX(0x0f3a, 0xc2): /* vcmpph $imm8,[xyz]mm/mem,[xyz]mm,k{k} */
visa_check(_fp16);
@@ -7982,10 +7989,11 @@ x86_emulate(
case X86EMUL_OPC_EVEX_66(6, 0xbd): /* vfnmadd231sh xmm/m16,xmm,xmm{k} */
case X86EMUL_OPC_EVEX_66(6, 0xbf): /* vfnmsub231sh xmm/m16,xmm,xmm{k} */
visa_check(_fp16);
- generate_exception_if(evex.w || (ea.type != OP_REG && evex.brs),
- X86_EXC_UD);
+ generate_exception_if(evex.w, X86_EXC_UD);
if ( !evex.brs )
avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
goto simd_zmm;
case X86EMUL_OPC_EVEX_66(6, 0x4c): /* vrcpph [xyz]mm/mem,[xyz]mm{k} */
@@ -8015,7 +8023,9 @@ x86_emulate(
unsigned int src1 = ~evex.reg;
visa_check(_fp16);
- generate_exception_if(evex.w || ((b & 1) && ea.type != OP_REG && evex.brs),
+ generate_exception_if((evex.w ||
+ ((b & 1) &&
+ (ea.type != OP_REG ? evex.brs : !evex.u))),
X86_EXC_UD);
if ( mode_64bit() )
src1 = (src1 & 0xf) | (!evex.RX << 4);
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 08/16] x86emul: support AVX10.2 scalar compare insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (6 preceding siblings ...)
2024-12-11 10:14 ` [PATCH v3 07/16] x86emul: support AVX10.2 256-bit embedded rounding / SAE Jan Beulich
@ 2024-12-11 10:17 ` Jan Beulich
2024-12-11 10:18 ` [PATCH v3 09/16] x86emul: support AVX10.2 partial copy insns Jan Beulich
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:17 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Simply clone code from their V{,U}COMIS{S,D,H} counterparts.
While there drop a redundant EVEX.W check from V{,U}COMISH handling.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
This still follows what spec version 001 says wrt embedded prefixed.
They were swapped to match other insns, yet so far no SDE is available
to run the test harness there with the flipped encoding.
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -81,6 +81,7 @@ enum esz {
ESZ_w,
ESZ_bw,
ESZ_fp16,
+#define ESZ_bf16 ESZ_fp16
};
#ifndef __i386__
@@ -711,6 +712,16 @@ static const struct test vpclmulqdq_all[
INSN(pclmulqdq, 66, 0f3a, 44, vl, q_nb, vl)
};
+static const struct test avx10_2_all[] = {
+ INSN(comsbf16, 66, map5, 2f, el, bf16, el),
+ INSN(comxsd, f3, 0f, 2f, el, q, el),
+ INSN(comxsh, f2, map5, 2f, el, fp16, el),
+ INSN(comxss, f2, 0f, 2f, el, d, el),
+ INSN(ucomxsd, f3, 0f, 2e, el, q, el),
+ INSN(ucomxsh, f2, map5, 2e, el, fp16, el),
+ INSN(ucomxss, f2, 0f, 2e, el, d, el),
+};
+
static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
static const unsigned char vl_128[] = { VL_128 };
static const unsigned char vl_no128[] = { VL_512, VL_256 };
@@ -1130,5 +1141,8 @@ void evex_disp8_test(void *instr, struct
RUN(vpclmulqdq, all);
#undef RUN
}
+
+ run(cpu_has_avx10_2, avx10_2, all);
+
#undef run
}
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1682,8 +1682,12 @@ static const struct evex {
{ { 0x2d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvtsd2si */
{ { 0x2e }, 2, T, R, pfx_no, W0, LIG }, /* vucomiss */
{ { 0x2e }, 2, T, R, pfx_66, W1, LIG }, /* vucomisd */
+ { { 0x2e }, 2, T, R, pfx_f3, W1, LIG }, /* vucomxsd */
+ { { 0x2e }, 2, T, R, pfx_f2, W0, LIG }, /* vucomxss */
{ { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomiss */
{ { 0x2f }, 2, T, R, pfx_66, W1, LIG }, /* vcomisd */
+ { { 0x2f }, 2, T, R, pfx_f3, W1, LIG }, /* vcomxsd */
+ { { 0x2f }, 2, T, R, pfx_f2, W0, LIG }, /* vcomxss */
{ { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtps */
{ { 0x51 }, 2, T, R, pfx_66, W1, Ln }, /* vsqrtpd */
{ { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtss */
@@ -2100,7 +2104,10 @@ static const struct evex {
{ { 0x2c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2si */
{ { 0x2d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsh2si */
{ { 0x2e }, 2, T, R, pfx_no, W0, LIG }, /* vucomish */
+ { { 0x2e }, 2, T, R, pfx_f2, W0, LIG }, /* vucomxsh */
{ { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomish */
+ { { 0x2f }, 2, T, R, pfx_66, W0, LIG }, /* vcomsbf16 */
+ { { 0x2f }, 2, T, R, pfx_f2, W0, LIG }, /* vcomxsh */
{ { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtph */
{ { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtsh */
{ { 0x58 }, 2, T, R, pfx_no, W0, Ln }, /* vaddph */
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -213,6 +213,8 @@ void wrpkru(unsigned int val);
(cpu_policy.avx10.vsz256 || \
cpu_policy.avx10.vsz512))
#define cpu_has_avx10_1_512 (cpu_has_avx10_1 && cpu_policy.avx10.vsz512)
+#define cpu_has_avx10_2 (cpu_policy.avx10.version >= 2 && \
+ xcr0_mask(0xe6))
#define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1)
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1521,9 +1521,8 @@ int x86emul_decode(struct x86_emulate_st
s->fp16 = true;
break;
- case 0x2e: case 0x2f: /* v{,u}comish */
- if ( !s->evex.pfx )
- s->fp16 = true;
+ case 0x2e: case 0x2f: /* v{,u}com{i,x}sh, vcomsbf16 */
+ s->fp16 = true;
s->simd_size = simd_none;
break;
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -304,7 +304,7 @@ struct x86_emulate_state {
bool lock_prefix;
bool not_64bit; /* Instruction not available in 64bit. */
bool fpu_ctrl; /* Instruction is an FPU control one. */
- bool fp16; /* Instruction has half-precision FP source operand. */
+ bool fp16; /* Instruction has half-precision FP or BF16 source. */
opcode_desc_t desc;
union vex vex;
union evex evex;
@@ -596,8 +596,8 @@ amd_like(const struct x86_emulate_ctxt *
#define vcpu_has_avx10(minor) (ctxt->cpuid->avx10.version >= (minor))
-#define vcpu_must_have(feat) \
- generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD)
+#define vcpu_must_have(feat, ...) \
+ generate_exception_if(!vcpu_has_##feat(__VA_ARGS__), X86_EXC_UD)
#ifdef __XEN__
/*
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -3813,7 +3813,6 @@ x86_emulate(
case X86EMUL_OPC_EVEX(5, 0x2e): /* vucomish xmm/m16,xmm */
case X86EMUL_OPC_EVEX(5, 0x2f): /* vcomish xmm/m16,xmm */
visa_check(_fp16);
- generate_exception_if(evex.w, X86_EXC_UD);
/* fall through */
CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */
CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2f): /* vcomis{s,d} xmm/mem,xmm */
@@ -3821,6 +3820,7 @@ x86_emulate(
evex.w != evex.pfx),
X86_EXC_UD);
visa_check(f);
+ vcomi_evex:
if ( !evex.brs )
avx512_vlen_check(true);
else
@@ -3831,6 +3831,17 @@ x86_emulate(
op_bytes = 2 << (!state->fp16 + evex.w);
goto vcomi;
+ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2e): /* vucomxs{s,d} xmm/mem,xmm */
+ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2f): /* vcomxs{s,d} xmm/mem,xmm */
+ case X86EMUL_OPC_EVEX_F2(5, 0x2e): /* vucomxsh xmm/m16,xmm */
+ case X86EMUL_OPC_EVEX_66(5, 0x2f): /* vcomsbf16 xmm/m16,xmm */
+ case X86EMUL_OPC_EVEX_F2(5, 0x2f): /* vcomxsh xmm/m16,xmm */
+ generate_exception_if((evex.reg != 0xf || !evex.RX || evex.opmsk ||
+ evex.w != !(evex.pfx & 1)),
+ X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ goto vcomi_evex;
+
#endif
case X86EMUL_OPC(0x0f, 0x30): /* wrmsr */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 09/16] x86emul: support AVX10.2 partial copy insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (7 preceding siblings ...)
2024-12-11 10:17 ` [PATCH v3 08/16] x86emul: support AVX10.2 scalar compare insns Jan Beulich
@ 2024-12-11 10:18 ` Jan Beulich
2024-12-11 10:18 ` [PATCH v3 10/16] x86emul: support AVX10.2 media insns Jan Beulich
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:18 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Extend existing VMOV{Q,W} logic accordingly.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -722,6 +722,13 @@ static const struct test avx10_2_all[] =
INSN(ucomxss, f2, 0f, 2e, el, d, el),
};
+static const struct test avx10_2_128[] = {
+ INSN(movd, f3, 0f, 7e, el, d, el),
+ INSN(movd, 66, 0f, d6, el, d, el),
+ INSN(movw, f3, map5, 6e, el, fp16, el),
+ INSN(movw, f3, map5, 7e, el, fp16, el),
+};
+
static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
static const unsigned char vl_128[] = { VL_128 };
static const unsigned char vl_no128[] = { VL_512, VL_256 };
@@ -1143,6 +1150,7 @@ void evex_disp8_test(void *instr, struct
}
run(cpu_has_avx10_2, avx10_2, all);
+ run(cpu_has_avx10_2, avx10_2, 128);
#undef run
}
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1782,7 +1782,7 @@ static const struct evex {
{ { 0x7b }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtusi2ss */
{ { 0x7b }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvtusi2sd */
{ { 0x7e }, 2, T, W, pfx_66, Wn, L0 }, /* vmov{d,q} */
- { { 0x7e }, 2, T, R, pfx_f3, W1, L0 }, /* vmovq */
+ { { 0x7e }, 2, T, R, pfx_f3, Wn, L0 }, /* vmov{d,q} */
{ { 0x7f }, 2, T, W, pfx_66, Wn, Ln }, /* vmovdqa{32,64} */
{ { 0x7f }, 2, T, W, pfx_f3, Wn, Ln }, /* vmovdqu{32,64} */
{ { 0x7f }, 2, T, W, pfx_f2, Wn, Ln }, /* vmovdqu{8,16} */
@@ -1799,7 +1799,7 @@ static const struct evex {
{ { 0xd3 }, 2, T, R, pfx_66, W1, Ln }, /* vpsrlq */
{ { 0xd4 }, 2, T, R, pfx_66, W1, Ln }, /* vpaddq */
{ { 0xd5 }, 2, T, R, pfx_66, WIG, Ln }, /* vpmullw */
- { { 0xd6 }, 2, T, W, pfx_66, W1, L0 }, /* vmovq */
+ { { 0xd6 }, 2, T, W, pfx_66, Wn, L0 }, /* vmov{d,q} */
{ { 0xd8 }, 2, T, R, pfx_66, WIG, Ln }, /* vpsubusb */
{ { 0xd9 }, 2, T, R, pfx_66, WIG, Ln }, /* vpsubusw */
{ { 0xda }, 2, T, R, pfx_66, WIG, Ln }, /* vpminub */
@@ -2131,6 +2131,7 @@ static const struct evex {
{ { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */
{ { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */
{ { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */
+ { { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */
{ { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */
{ { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttph2uqq */
{ { 0x78 }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2usi */
@@ -2149,6 +2150,7 @@ static const struct evex {
{ { 0x7d }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtw2ph */
{ { 0x7d }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtuwph */
{ { 0x7e }, 2, T, W, pfx_66, WIG, L0 }, /* vmovw */
+ { { 0x7e }, 2, T, W, pfx_f3, W0, L0 }, /* vmovw */
}, evex_map6[] = {
{ { 0x13 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2psx */
{ { 0x13 }, 2, T, R, pfx_no, W0, LIG }, /* vcvtsh2ss */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -293,7 +293,7 @@ static const struct twobyte_table {
[0xd0] = { DstImplicit|SrcMem|ModRM, simd_other },
[0xd1 ... 0xd3] = { DstImplicit|SrcMem|ModRM, simd_128, 4 },
[0xd4 ... 0xd5] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
- [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other, 3 },
+ [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other, d8s_dq },
[0xd7] = { DstReg|SrcImplicit|ModRM|Mov },
[0xd8 ... 0xdf] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
[0xe0] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl },
@@ -802,7 +802,7 @@ decode_twobyte(struct x86_emulate_state
if ( s->vex.pfx == vex_f3 ) /* movq xmm/m64,xmm */
{
case X86EMUL_OPC_VEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */
- case X86EMUL_OPC_EVEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */
+ case X86EMUL_OPC_EVEX_F3(0, 0x7e): /* vmov{d,q} xmm/mem,xmm */
s->desc = DstImplicit | SrcMem | TwoOp;
s->simd_size = simd_other;
/* Avoid the s->desc clobbering of TwoOp below. */
@@ -1422,7 +1422,7 @@ int x86emul_decode(struct x86_emulate_st
break;
case 0x7e: /* vmovq xmm/m64,xmm needs special casing */
- if ( disp8scale == 2 && s->evex.pfx == vex_f3 )
+ if ( disp8scale == 2 && s->evex.pfx == vex_f3 && s->evex.w )
disp8scale = 3;
break;
@@ -1531,13 +1531,13 @@ int x86emul_decode(struct x86_emulate_st
s->fp16 = true;
break;
- case 0x6e: /* vmovw r/m16, xmm */
+ case 0x6e: /* vmovw r/x/m16, xmm */
d = (d & ~SrcMask) | SrcMem16;
/* fall through */
- case 0x7e: /* vmovw xmm, r/m16 */
+ case 0x7e: /* vmovw xmm, r/x/m16 */
+ s->fp16 = true;
if ( s->evex.pfx == vex_66 )
- s->fp16 = true;
- s->simd_size = simd_none;
+ s->simd_size = simd_none;
break;
case 0x78: case 0x79: /* vcvt{,t}ph2u{d,q}q, vcvt{,t}sh2usi */
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -4918,13 +4918,17 @@ x86_emulate(
op_bytes = 8;
goto simd_0f_int;
- case X86EMUL_OPC_EVEX_F3(0x0f, 0x7e): /* vmovq xmm/m64,xmm */
- case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */
- generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.brs,
- X86_EXC_UD);
- visa_check(f);
+ case X86EMUL_OPC_EVEX_F3(0x0f, 0x7e): /* vmov{d,q} xmm/mem,xmm */
+ case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmov{d,q} xmm,xmm/mem */
+ case X86EMUL_OPC_EVEX_F3(5, 0x6e): /* vmovw xmm/m16,xmm */
+ case X86EMUL_OPC_EVEX_F3(5, 0x7e): /* vmovw xmm,xmm/m16 */
+ generate_exception_if(evex.lr || evex.opmsk || evex.brs, X86_EXC_UD);
+ if ( evex.w )
+ visa_check(f);
+ else
+ vcpu_must_have(avx10, 2);
d |= TwoOp;
- op_bytes = 8;
+ op_bytes = 2 << (!state->fp16 + evex.w);
goto simd_zmm;
#endif /* !X86EMUL_NO_SIMD */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 10/16] x86emul: support AVX10.2 media insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (8 preceding siblings ...)
2024-12-11 10:18 ` [PATCH v3 09/16] x86emul: support AVX10.2 partial copy insns Jan Beulich
@ 2024-12-11 10:18 ` Jan Beulich
2024-12-11 10:19 ` [PATCH v3 11/16] x86emul: support AVX10.2 minmax insns Jan Beulich
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:18 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
These are all very similar to various existing insns.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -717,6 +717,20 @@ static const struct test avx10_2_all[] =
INSN(comxsd, f3, 0f, 2f, el, q, el),
INSN(comxsh, f2, map5, 2f, el, fp16, el),
INSN(comxss, f2, 0f, 2f, el, d, el),
+ INSN(dpphps, , 0f38, 52, vl, d, vl),
+ INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl),
+ INSN(pdpbssd, f2, 0f38, 50, vl, d, vl),
+ INSN(pdpbssds, f2, 0f38, 51, vl, d, vl),
+ INSN(pdpbsud, f3, 0f38, 50, vl, d, vl),
+ INSN(pdpbsuds, f3, 0f38, 51, vl, d, vl),
+ INSN(pdpbuud, , 0f38, 50, vl, d, vl),
+ INSN(pdpbuuds, , 0f38, 51, vl, d, vl),
+ INSN(pdpwsud, f3, 0f38, d2, vl, d, vl),
+ INSN(pdpwsuds, f3, 0f38, d3, vl, d, vl),
+ INSN(pdpwusd, 66, 0f38, d2, vl, d, vl),
+ INSN(pdpwusds, 66, 0f38, d3, vl, d, vl),
+ INSN(pdpwuud, , 0f38, d2, vl, d, vl),
+ INSN(pdpwuuds, , 0f38, d3, vl, d, vl),
INSN(ucomxsd, f3, 0f, 2e, el, q, el),
INSN(ucomxsh, f2, map5, 2e, el, fp16, el),
INSN(ucomxss, f2, 0f, 2e, el, d, el),
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1927,8 +1927,15 @@ static const struct evex {
{ { 0x4d }, 2, T, R, pfx_66, Wn, LIG }, /* vrcp14s{s,d} */
{ { 0x4e }, 2, T, R, pfx_66, Wn, Ln }, /* vrsqrt14p{s,d} */
{ { 0x4f }, 2, T, R, pfx_66, Wn, LIG }, /* vrsqrt14s{s,d} */
+ { { 0x50 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuud */
{ { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */
+ { { 0x50 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsud */
+ { { 0x50 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssd */
+ { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuuds */
{ { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */
+ { { 0x51 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsuds */
+ { { 0x51 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssds */
+ { { 0x52 }, 2, T, R, pfx_no, W0, Ln }, /* vdpphps */
{ { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */
{ { 0x52 }, 2, T, R, pfx_f3, W0, Ln }, /* vdpbf16ps */
{ { 0x52 }, 2, T, R, pfx_f2, W0, L2 }, /* vp4dpwssd */
@@ -2029,6 +2036,12 @@ static const struct evex {
{ { 0xcc }, 2, T, R, pfx_66, Wn, L2 }, /* vrsqrt28p{s,d} */
{ { 0xcd }, 2, T, R, pfx_66, Wn, LIG }, /* vrsqrt28s{s,d} */
{ { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */
+ { { 0xd2 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuud */
+ { { 0xd2 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusd */
+ { { 0xd2 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsud */
+ { { 0xd3 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuuds */
+ { { 0xd3 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusds */
+ { { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */
{ { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */
{ { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */
{ { 0xde }, 2, T, R, pfx_66, WIG, Ln }, /* vaesdec */
@@ -2073,6 +2086,7 @@ static const struct evex {
{ { 0x3e }, 3, T, R, pfx_66, Wn, Ln }, /* vpcmpu{b,w} */
{ { 0x3f }, 3, T, R, pfx_66, Wn, Ln }, /* vpcmp{b,w} */
{ { 0x42 }, 3, T, R, pfx_66, W0, Ln }, /* vdbpsadbw */
+ { { 0x42 }, 3, T, R, pfx_f3, W0, Ln }, /* vmpsadbw */
{ { 0x43 }, 3, T, R, pfx_66, Wn, L1|L2 }, /* vshufi{32x4,64x2} */
{ { 0x44 }, 3, T, R, pfx_66, WIG, Ln }, /* vpclmulqdq */
{ { 0x50 }, 3, T, R, pfx_66, Wn, Ln }, /* vrangep{s,d} */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -433,8 +433,8 @@ static const struct ext0f38_table {
[0xcb] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xcc ... 0xcd] = { .simd_size = simd_other, .two_op = 1, .d8s = d8s_vl },
[0xcf] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
- [0xd2] = { .simd_size = simd_other },
- [0xd3] = { .simd_size = simd_other },
+ [0xd2] = { .simd_size = simd_other, .d8s = d8s_vl },
+ [0xd3] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xd6] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
[0xda] = { .simd_size = simd_other },
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6201,6 +6201,24 @@ x86_emulate(
avx512_vlen_check(true);
goto simd_zmm;
+ case X86EMUL_OPC_EVEX (0x0f38, 0x50): /* vpdpbuud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x50): /* vpdpbsud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f38, 0x50): /* vpdpbssd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (0x0f38, 0x51): /* vpdpbuuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x51): /* vpdpbsuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f38, 0x51): /* vpdpbssds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (0x0f38, 0xd2): /* vpdpwuud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(0x0f38, 0xd2): /* vpdpwusd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0xd2): /* vpdpwsud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (0x0f38, 0xd3): /* vpdpwuuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(0x0f38, 0xd3): /* vpdpwusds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0xd3): /* vpdpwsuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (0x0f38, 0x52): /* vdpphps [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ generate_exception_if(evex.w, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ op_bytes = 16 << evex.lr;
+ goto avx512f_no_sae;
+
case X86EMUL_OPC_EVEX_66(0x0f38, 0x8f): /* vpshufbitqmb [xyz]mm/mem,[xyz]mm,k{k} */
generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD);
/* fall through */
@@ -7660,6 +7678,14 @@ x86_emulate(
visa_check(bw);
goto opmask_shift_imm;
+ case X86EMUL_OPC_EVEX_F3(0x0f3a, 0x42): /* vmpsadbw $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ generate_exception_if(evex.w || evex.brs, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ fault_suppression = false;
+ goto simd_imm8_zmm;
+
case X86EMUL_OPC_66(0x0f3a, 0x44): /* pclmulqdq $imm8,xmm/m128,xmm */
case X86EMUL_OPC_VEX_66(0x0f3a, 0x44): /* vpclmulqdq $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */
host_and_vcpu_must_have(pclmulqdq);
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 11/16] x86emul: support AVX10.2 minmax insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (9 preceding siblings ...)
2024-12-11 10:18 ` [PATCH v3 10/16] x86emul: support AVX10.2 media insns Jan Beulich
@ 2024-12-11 10:19 ` Jan Beulich
2024-12-11 10:19 ` [PATCH v3 12/16] x86emul: support AVX10.2 BFloat16 insns Jan Beulich
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:19 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
While they use new major opcodes, they are still pretty similar to
various existing insns.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Spec rev 002 says VMINMAXNEPBF16, yet that's going to change to
VMINMAXPBF16.
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -718,6 +718,11 @@ static const struct test avx10_2_all[] =
INSN(comxsh, f2, map5, 2f, el, fp16, el),
INSN(comxss, f2, 0f, 2f, el, d, el),
INSN(dpphps, , 0f38, 52, vl, d, vl),
+ INSN(minmax, 66, 0f3a, 52, vl, sd, vl),
+ INSN(minmax, 66, 0f3a, 53, el, sd, el),
+ INSN(minmaxpbf16, f2, 0f3a, 52, vl, bf16, vl),
+ INSN(minmaxph, , 0f3a, 52, vl, fp16, vl),
+ INSN(minmaxsh, , 0f3a, 53, el, fp16, el),
INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl),
INSN(pdpbssd, f2, 0f38, 50, vl, d, vl),
INSN(pdpbssds, f2, 0f38, 51, vl, d, vl),
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2091,6 +2091,11 @@ static const struct evex {
{ { 0x44 }, 3, T, R, pfx_66, WIG, Ln }, /* vpclmulqdq */
{ { 0x50 }, 3, T, R, pfx_66, Wn, Ln }, /* vrangep{s,d} */
{ { 0x51 }, 3, T, R, pfx_66, Wn, LIG }, /* vranges{s,d} */
+ { { 0x52 }, 3, T, R, pfx_no, W0, Ln }, /* vminmaxph */
+ { { 0x52 }, 3, T, R, pfx_66, Wn, Ln }, /* vminmaxp{s,d} */
+ { { 0x52 }, 3, T, R, pfx_f2, W0, Ln }, /* vminmaxpbf16 */
+ { { 0x53 }, 3, T, R, pfx_no, W0, LIG }, /* vminmaxsh */
+ { { 0x53 }, 3, T, R, pfx_66, Wn, LIG }, /* vminmaxs{s,d} */
{ { 0x54 }, 3, T, R, pfx_66, Wn, Ln }, /* vfixupimmp{s,d} */
{ { 0x55 }, 3, T, R, pfx_66, Wn, LIG }, /* vfixumpimms{s,d} */
{ { 0x56 }, 3, T, R, pfx_no, W0, Ln }, /* vreduceph */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -499,6 +499,8 @@ static const struct ext0f3a_table {
[0x4c] = { .simd_size = simd_packed_int, .four_op = 1 },
[0x50] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
[0x51] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
+ [0x52] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
+ [0x53] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
[0x54] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
[0x55] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
[0x56] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl },
@@ -1474,6 +1476,7 @@ int x86emul_decode(struct x86_emulate_st
case 0x0a: /* vrndscalesh */
case 0x26: /* vfpclassph */
case 0x27: /* vfpclasssh */
+ case 0x53: /* vminmaxsh */
case 0x56: /* vgetmantph */
case 0x57: /* vgetmantsh */
case 0x66: /* vreduceph */
@@ -1482,6 +1485,11 @@ int x86emul_decode(struct x86_emulate_st
s->fp16 = true;
break;
+ case 0x52: /* vminmaxp{h,bf16} */
+ if ( !s->evex.pfx || s->evex.pfx == vex_f2 )
+ s->fp16 = true;
+ break;
+
case 0xc2: /* vpcmp{p,s}h */
if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) )
s->fp16 = true;
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7716,6 +7716,21 @@ x86_emulate(
generate_exception_if(vex.w, X86_EXC_UD);
goto simd_0f_int_imm8;
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x52): /* vminmaxpbf16 $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+ op_bytes = 16 << evex.lr;
+ /* fall through */
+ case X86EMUL_OPC_EVEX(0x0f3a, 0x52): /* vminmaxph $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(0x0f3a, 0x53): /* vminmaxsh $imm,xmm/m16,xmm,xmm,xmm{k} */
+ generate_exception_if(vex.w, X86_EXC_UD);
+ /* fall through */
+ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x52): /* vminmaxp{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x53): /* vminmaxs{s,d} $imm8,xmm/mem,xmm,xmm{k} */
+ vcpu_must_have(avx10, 2);
+ if ( ea.type != OP_REG || !evex.brs )
+ avx512_vlen_check(b & 1);
+ goto simd_imm8_zmm;
+
case X86EMUL_OPC_VEX_66(0x0f3a, 0x5c): /* vfmaddsubps {x,y}mm,{x,y}mm/mem,{x,y}mm,{x,y}mm */
/* vfmaddsubps {x,y}mm/mem,{x,y}mm,{x,y}mm,{x,y}mm */
case X86EMUL_OPC_VEX_66(0x0f3a, 0x5d): /* vfmaddsubpd {x,y}mm,{x,y}mm/mem,{x,y}mm,{x,y}mm */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 12/16] x86emul: support AVX10.2 BFloat16 insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (10 preceding siblings ...)
2024-12-11 10:19 ` [PATCH v3 11/16] x86emul: support AVX10.2 minmax insns Jan Beulich
@ 2024-12-11 10:19 ` Jan Beulich
2024-12-11 10:20 ` [PATCH v3 13/16] x86emul: support AVX10.2 saturating convert insns Jan Beulich
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:19 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
These are all very similar to various existing insns. VGETEXPPBF16, not
living in the expected place, benefits from the respective
twobyte_table[] entry already having Mov (aka TwoOp).
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
This still follows what spec version 001 says for VGETEXPPBF16. It moved
to map 6 (and be NP), yet so far no SDE is available to run the test
harness there with the changed encoding.
Spec rev 002 says VSCALEFPBF16, yet that's going to change to
VSCALEFNEPBF16.
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -713,16 +713,37 @@ static const struct test vpclmulqdq_all[
};
static const struct test avx10_2_all[] = {
+ INSN(addnepbf16, 66, map5, 58, vl, bf16, vl),
+ INSN(cmppbf16, f2, 0f3a, c2, vl, bf16, vl),
INSN(comsbf16, 66, map5, 2f, el, bf16, el),
INSN(comxsd, f3, 0f, 2f, el, q, el),
INSN(comxsh, f2, map5, 2f, el, fp16, el),
INSN(comxss, f2, 0f, 2f, el, d, el),
+ INSN(divnepbf16, 66, map5, 5e, vl, bf16, vl),
INSN(dpphps, , 0f38, 52, vl, d, vl),
+ INSN(fmadd132nepbf16, , map6, 98, vl, bf16, vl),
+ INSN(fmadd213nepbf16, , map6, a8, vl, bf16, vl),
+ INSN(fmadd231nepbf16, , map6, b8, vl, bf16, vl),
+ INSN(fmsub132nepbf16, , map6, 9a, vl, bf16, vl),
+ INSN(fmsub213nepbf16, , map6, aa, vl, bf16, vl),
+ INSN(fmsub231nepbf16, , map6, ba, vl, bf16, vl),
+ INSN(fnmadd132nepbf16, , map6, 9c, vl, bf16, vl),
+ INSN(fnmadd213nepbf16, , map6, ac, vl, bf16, vl),
+ INSN(fnmadd231nepbf16, , map6, bc, vl, bf16, vl),
+ INSN(fnmsub132nepbf16, , map6, 9e, vl, bf16, vl),
+ INSN(fnmsub213nepbf16, , map6, ae, vl, bf16, vl),
+ INSN(fnmsub231nepbf16, , map6, be, vl, bf16, vl),
+ INSN(fpclasspbf16, f2, 0f3a, 66, vl, bf16, vl),
+ INSN(getexppbf16, 66, map5, 42, vl, bf16, vl),
+ INSN(getmantpbf16, f2, 0f3a, 26, vl, bf16, vl),
+ INSN(maxpbf16, 66, map5, 5f, vl, bf16, vl),
+ INSN(minpbf16, 66, map5, 5d, vl, bf16, vl),
INSN(minmax, 66, 0f3a, 52, vl, sd, vl),
INSN(minmax, 66, 0f3a, 53, el, sd, el),
INSN(minmaxpbf16, f2, 0f3a, 52, vl, bf16, vl),
INSN(minmaxph, , 0f3a, 52, vl, fp16, vl),
INSN(minmaxsh, , 0f3a, 53, el, fp16, el),
+ INSN(mulnepbf16, 66, map5, 59, vl, bf16, vl),
INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl),
INSN(pdpbssd, f2, 0f38, 50, vl, d, vl),
INSN(pdpbssds, f2, 0f38, 51, vl, d, vl),
@@ -736,6 +757,13 @@ static const struct test avx10_2_all[] =
INSN(pdpwusds, 66, 0f38, d3, vl, d, vl),
INSN(pdpwuud, , 0f38, d2, vl, d, vl),
INSN(pdpwuuds, , 0f38, d3, vl, d, vl),
+ INSN(rcpph, , map6, 4c, vl, bf16, vl),
+ INSN(reducenepbf16, f2, 0f3a, 56, vl, bf16, vl),
+ INSN(rndscalenepbf16, f2, 0f3a, 08, vl, bf16, vl),
+ INSN(rsqrtph, , map6, 4e, vl, bf16, vl),
+ INSN(scalefnepbf16, , map6, 2c, vl, bf16, vl),
+ INSN(sqrtnepbf16, 66, map5, 51, vl, bf16, vl),
+ INSN(subnepbf16, 66, map5, 5c, vl, bf16, vl),
INSN(ucomxsd, f3, 0f, 2e, el, q, el),
INSN(ucomxsh, f2, map5, 2e, el, fp16, el),
INSN(ucomxss, f2, 0f, 2e, el, d, el),
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2054,6 +2054,7 @@ static const struct evex {
{ { 0x05 }, 3, T, R, pfx_66, W1, Ln }, /* vpermilpd */
{ { 0x08 }, 3, T, R, pfx_no, W0, Ln }, /* vrndscaleph */
{ { 0x08 }, 3, T, R, pfx_66, W0, Ln }, /* vrndscaleps */
+ { { 0x08 }, 3, T, R, pfx_f2, W0, Ln }, /* vrndscalenepbf16 */
{ { 0x09 }, 3, T, R, pfx_66, W1, Ln }, /* vrndscalepd */
{ { 0x0a }, 3, T, R, pfx_no, W0, LIG }, /* vrndscalesh */
{ { 0x0a }, 3, T, R, pfx_66, W0, LIG }, /* vrndscaless */
@@ -2077,6 +2078,7 @@ static const struct evex {
{ { 0x25 }, 3, T, R, pfx_66, Wn, Ln }, /* vpternlog{d,q} */
{ { 0x26 }, 3, T, R, pfx_no, W0, Ln }, /* vgetmantph */
{ { 0x26 }, 3, T, R, pfx_66, Wn, Ln }, /* vgetmantp{s,d} */
+ { { 0x26 }, 3, T, R, pfx_f2, W0, Ln }, /* vgetmantpbf16 */
{ { 0x27 }, 3, T, R, pfx_no, W0, LIG }, /* vgetmantsh */
{ { 0x27 }, 3, T, R, pfx_66, Wn, LIG }, /* vgetmants{s,d} */
{ { 0x38 }, 3, T, R, pfx_66, Wn, L1|L2 }, /* vinserti{32x4,64x2} */
@@ -2100,10 +2102,12 @@ static const struct evex {
{ { 0x55 }, 3, T, R, pfx_66, Wn, LIG }, /* vfixumpimms{s,d} */
{ { 0x56 }, 3, T, R, pfx_no, W0, Ln }, /* vreduceph */
{ { 0x56 }, 3, T, R, pfx_66, Wn, Ln }, /* vreducep{s,d} */
+ { { 0x56 }, 3, T, R, pfx_f2, W0, Ln }, /* vreducenepbf16 */
{ { 0x57 }, 3, T, R, pfx_no, W0, LIG }, /* vreducesh */
{ { 0x57 }, 3, T, R, pfx_66, Wn, LIG }, /* vreduces{s,d} */
{ { 0x66 }, 3, T, R, pfx_no, W0, Ln }, /* vfpclassph */
{ { 0x66 }, 3, T, R, pfx_66, Wn, Ln }, /* vfpclassp{s,d} */
+ { { 0x66 }, 3, T, R, pfx_f2, W0, Ln }, /* vfpclasspbf16 */
{ { 0x67 }, 3, T, R, pfx_no, W0, LIG }, /* vfpclasssh */
{ { 0x67 }, 3, T, R, pfx_66, Wn, LIG }, /* vfpclasss{s,d} */
{ { 0x70 }, 3, T, R, pfx_66, W1, Ln }, /* vshldw */
@@ -2112,6 +2116,7 @@ static const struct evex {
{ { 0x73 }, 3, T, R, pfx_66, Wn, Ln }, /* vshrd{d,q} */
{ { 0xc2 }, 3, T, R, pfx_no, W0, Ln }, /* vcmpph */
{ { 0xc2 }, 3, T, R, pfx_f3, W0, LIG }, /* vcmpsh */
+ { { 0xc2 }, 3, T, R, pfx_f2, W0, Ln }, /* vcmppbf16 */
{ { 0xce }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineqb */
{ { 0xcf }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineinvqb */
}, evex_map5[] = {
@@ -2127,11 +2132,15 @@ static const struct evex {
{ { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomish */
{ { 0x2f }, 2, T, R, pfx_66, W0, LIG }, /* vcomsbf16 */
{ { 0x2f }, 2, T, R, pfx_f2, W0, LIG }, /* vcomxsh */
+ { { 0x42 }, 2, T, R, pfx_66, W0, Ln }, /* vgetexppbf16 */
{ { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtph */
+ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vsqrtnepbf16 */
{ { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtsh */
{ { 0x58 }, 2, T, R, pfx_no, W0, Ln }, /* vaddph */
+ { { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vaddnepbf16 */
{ { 0x58 }, 2, T, R, pfx_f3, W0, LIG }, /* vaddsh */
{ { 0x59 }, 2, T, R, pfx_no, W0, Ln }, /* vmulph */
+ { { 0x59 }, 2, T, R, pfx_66, W0, Ln }, /* vmulnepbf16 */
{ { 0x59 }, 2, T, R, pfx_f3, W0, LIG }, /* vmulsh */
{ { 0x5a }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2pd */
{ { 0x5a }, 2, T, R, pfx_66, W1, Ln }, /* vcvtpd2ph */
@@ -2142,12 +2151,16 @@ static const struct evex {
{ { 0x5b }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2dq */
{ { 0x5b }, 2, T, R, pfx_f3, W0, Ln }, /* vcvttph2dq */
{ { 0x5c }, 2, T, R, pfx_no, W0, Ln }, /* vsubph */
+ { { 0x5c }, 2, T, R, pfx_66, W0, Ln }, /* vsubnepbf16 */
{ { 0x5c }, 2, T, R, pfx_f3, W0, LIG }, /* vsubsh */
{ { 0x5d }, 2, T, R, pfx_no, W0, Ln }, /* vminph */
+ { { 0x5d }, 2, T, R, pfx_66, W0, Ln }, /* vminpbf16 */
{ { 0x5d }, 2, T, R, pfx_f3, W0, LIG }, /* vminsh */
{ { 0x5e }, 2, T, R, pfx_no, W0, Ln }, /* vdivph */
+ { { 0x5e }, 2, T, R, pfx_66, W0, Ln }, /* vdivnepbf16 */
{ { 0x5e }, 2, T, R, pfx_f3, W0, LIG }, /* vdivsh */
{ { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */
+ { { 0x5f }, 2, T, R, pfx_66, W0, Ln }, /* vmaxpbf16 */
{ { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */
{ { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */
{ { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */
@@ -2173,12 +2186,15 @@ static const struct evex {
}, evex_map6[] = {
{ { 0x13 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2psx */
{ { 0x13 }, 2, T, R, pfx_no, W0, LIG }, /* vcvtsh2ss */
+ { { 0x2c }, 2, T, R, pfx_no, W0, Ln }, /* vscalefnepbf16 */
{ { 0x2c }, 2, T, R, pfx_66, W0, Ln }, /* vscalefph */
{ { 0x2d }, 2, T, R, pfx_66, W0, LIG }, /* vscalefsh */
{ { 0x42 }, 2, T, R, pfx_66, W0, Ln }, /* vgetexpph */
{ { 0x43 }, 2, T, R, pfx_66, W0, LIG }, /* vgetexpsh */
+ { { 0x4c }, 2, T, R, pfx_no, W0, Ln }, /* vrcppbf16 */
{ { 0x4c }, 2, T, R, pfx_66, W0, Ln }, /* vrcpph */
{ { 0x4d }, 2, T, R, pfx_66, W0, LIG }, /* vrcpsh */
+ { { 0x4e }, 2, T, R, pfx_no, W0, Ln }, /* vrsqrtpbf16 */
{ { 0x4e }, 2, T, R, pfx_66, W0, Ln }, /* vrsqrtph */
{ { 0x4f }, 2, T, R, pfx_66, W0, LIG }, /* vrsqrtsh */
{ { 0x56 }, 2, T, R, pfx_f3, W0, Ln }, /* vfmaddcph */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1472,31 +1472,34 @@ int x86emul_decode(struct x86_emulate_st
{
switch ( b )
{
- case 0x08: /* vrndscaleph */
+ case 0x08: /* vrndscale{ph,nepbf16} */
+ case 0x26: /* vfpclassp{h,bf16} */
+ case 0x52: /* vminmaxp{h,bf16} */
+ case 0x56: /* vgetmantp{h,bf16} */
+ case 0x66: /* vreduce{ph,nepbf16} */
+ if ( !s->evex.pfx || s->evex.pfx == vex_f2 )
+ s->fp16 = true;
+ break;
+
case 0x0a: /* vrndscalesh */
- case 0x26: /* vfpclassph */
case 0x27: /* vfpclasssh */
case 0x53: /* vminmaxsh */
- case 0x56: /* vgetmantph */
case 0x57: /* vgetmantsh */
- case 0x66: /* vreduceph */
case 0x67: /* vreducesh */
if ( !s->evex.pfx )
s->fp16 = true;
break;
- case 0x52: /* vminmaxp{h,bf16} */
- if ( !s->evex.pfx || s->evex.pfx == vex_f2 )
- s->fp16 = true;
- break;
-
- case 0xc2: /* vpcmp{p,s}h */
- if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) )
+ case 0xc2: /* vpcmp{p,s}h, vcmppbf16 */
+ if ( s->evex.pfx != vex_66 )
s->fp16 = true;
break;
}
- disp8scale = decode_disp8scale(ext0f3a_table[b].d8s, s);
+ if ( s->fp16 && s->evex.pfx == vex_f2 && !s->evex.brs )
+ disp8scale = 4 + s->evex.lr;
+ else
+ disp8scale = decode_disp8scale(ext0f3a_table[b].d8s, s);
}
break;
@@ -1504,7 +1507,7 @@ int x86emul_decode(struct x86_emulate_st
switch ( b )
{
default:
- if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) )
+ if ( s->evex.pfx != vex_f2 )
s->fp16 = true;
break;
@@ -1534,6 +1537,11 @@ int x86emul_decode(struct x86_emulate_st
s->simd_size = simd_none;
break;
+ case 0x5a: /* vcvt{p,s}d2{p,s}h, vcvt{p,s}h2{p,s}d */
+ if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) )
+ s->fp16 = true;
+ break;
+
case 0x5b: /* vcvt{d,q}q2ph, vcvt{,t}ph2dq */
if ( s->evex.pfx && s->evex.pfx != vex_f2 )
s->fp16 = true;
@@ -1586,6 +1594,14 @@ int x86emul_decode(struct x86_emulate_st
disp8scale = 1;
break;
+ case 0x42: /* vgetexppbf16 needs special casing */
+ if ( s->evex.pfx == vex_66 )
+ {
+ s->simd_size = simd_packed_fp;
+ disp8scale = s->evex.brs ? 1 : 4 + s->evex.lr;
+ }
+ break;
+
case 0x5a: /* vcvtph2pd needs special casing */
if ( !s->evex.pfx && !s->evex.brs )
disp8scale -= 2;
@@ -1618,7 +1634,7 @@ int x86emul_decode(struct x86_emulate_st
switch ( b )
{
default:
- if ( s->evex.pfx == vex_66 )
+ if ( !(s->evex.pfx & VEX_PREFIX_SCALAR_MASK) )
s->fp16 = true;
break;
@@ -1950,6 +1966,13 @@ int x86emul_decode(struct x86_emulate_st
s->op_bytes = 4 >> s->fp16;
break;
case vex_f2:
+ if ( s->fp16 )
+ {
+ ASSERT(evex_encoded());
+ generate_exception_if(s->evex.w, X86_EXC_UD);
+ s->op_bytes = 0;
+ break;
+ }
generate_exception_if(evex_encoded() && !s->evex.w, X86_EXC_UD);
s->op_bytes = 8;
break;
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -7319,6 +7319,20 @@ x86_emulate(
avx512_vlen_check(b & 2);
goto simd_imm8_zmm;
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x66): /* vfpclasspbf16 $imm8,[xyz]mm/mem,k{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0xc2): /* vcmppbf16 $imm8,[xyz]mm/mem,[xyz]mm,k{k} */
+ generate_exception_if(!evex.r || !evex.R || evex.z, X86_EXC_UD);
+ /* fall through */
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x08): /* vrndscalenepbf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x26): /* vgetmantpbf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x56): /* vreducenepbf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */
+ generate_exception_if(evex.w || (ea.type != OP_MEM && evex.brs),
+ X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ goto simd_imm8_zmm;
+
#endif /* X86EMUL_NO_SIMD */
CASE_SIMD_PACKED_INT(0x0f3a, 0x0f): /* palignr $imm8,{,x}mm/mem,{,x}mm */
@@ -7951,6 +7965,36 @@ x86_emulate(
generate_exception_if(evex.w, X86_EXC_UD);
goto avx512f_all_fp;
+ case X86EMUL_OPC_EVEX_66(5, 0x42): /* vgetexppbf16 [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x51): /* vsqrtnepbf16 [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x58): /* vaddnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x59): /* vmulnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x5c): /* vsubnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x5d): /* vminpbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x5e): /* vdivnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x5f): /* vmaxpbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x2c): /* vscalefnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x4c): /* vrcppbf16 [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x4e): /* vrsqrtpbf16 [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x98): /* vfmadd132nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x9a): /* vfmsub132nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x9c): /* vfnmadd132nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0x9e): /* vfnmsub132nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xa8): /* vfmadd213nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xaa): /* vfmsub213nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xac): /* vfnmadd213nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xae): /* vfnmsub213nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xb8): /* vfmadd231nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xba): /* vfmsub231nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xbc): /* vfnmadd231nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX(6, 0xbe): /* vfnmsub231nepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+ generate_exception_if(evex.w || (ea.type != OP_MEM && evex.brs),
+ X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ goto simd_zmm;
+
CASE_SIMD_ALL_FP(_EVEX, 5, 0x5a): /* vcvtp{h,d}2p{h,d} [xyz]mm/mem,[xyz]mm{k} */
/* vcvts{h,d}2s{h,d} xmm/mem,xmm,xmm{k} */
visa_check(_fp16);
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 13/16] x86emul: support AVX10.2 saturating convert insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (11 preceding siblings ...)
2024-12-11 10:19 ` [PATCH v3 12/16] x86emul: support AVX10.2 BFloat16 insns Jan Beulich
@ 2024-12-11 10:20 ` Jan Beulich
2024-12-11 10:20 ` [PATCH v3 14/16] x86emul: support other AVX10.2 " Jan Beulich
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:20 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
While the to-byte ones are somewhat different from what has been there
(yet then nicely regular from an operands perspective), the others are
pretty similar to various existing insns.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
Spec rev 002 says VCVTTNEBF162I{,U}BS, yet that's going to change to
VCVTTBF162I{,U}BS.
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -719,6 +719,30 @@ static const struct test avx10_2_all[] =
INSN(comxsd, f3, 0f, 2f, el, q, el),
INSN(comxsh, f2, map5, 2f, el, fp16, el),
INSN(comxss, f2, 0f, 2f, el, d, el),
+ INSN(cvtnebf162ibs, f2, map5, 69, vl, bf16, vl),
+ INSN(cvtnebf162iubs, f2, map5, 6b, vl, bf16, vl),
+ INSN(cvtph2ibs, , map5, 69, vl, fp16, vl),
+ INSN(cvtph2iubs, , map5, 6b, vl, fp16, vl),
+ INSN(cvtps2ibs, 66, map5, 69, vl, d, vl),
+ INSN(cvtps2iubs, 66, map5, 6b, vl, d, vl),
+ INSN(cvttbf162ibs, f2, map5, 68, vl, bf16, vl),
+ INSN(cvttbf162iubs, f2, map5, 6a, vl, bf16, vl),
+ INSN(cvttpd2dqs, , map5, 6d, vl, q, vl),
+ INSN(cvttpd2qqs, 66, map5, 6d, vl, q, vl),
+ INSN(cvttpd2udqs, , map5, 6c, vl, q, vl),
+ INSN(cvttpd2uqqs, 66, map5, 6c, vl, q, vl),
+ INSN(cvttph2ibs, , map5, 68, vl, fp16, vl),
+ INSN(cvttph2iubs, , map5, 6a, vl, fp16, vl),
+ INSN(cvttps2dqs, , map5, 6d, vl, d, vl),
+ INSN(cvttps2ibs, 66, map5, 68, vl, d, vl),
+ INSN(cvttps2iubs, 66, map5, 6a, vl, d, vl),
+ INSN(cvttps2qqs, 66, map5, 6d, vl_2, d, vl),
+ INSN(cvttps2udqs, , map5, 6c, vl, d, vl),
+ INSN(cvttps2uqqs, 66, map5, 6c, vl_2, d, vl),
+ INSN(cvttsd2sis, f2, map5, 6d, el, q, el),
+ INSN(cvttsd2usis, f2, map5, 6c, el, q, el),
+ INSN(cvttss2sis, f3, map5, 6d, el, d, el),
+ INSN(cvttss2usis, f3, map5, 6c, el, d, el),
INSN(divnepbf16, 66, map5, 5e, vl, bf16, vl),
INSN(dpphps, , 0f38, 52, vl, d, vl),
INSN(fmadd132nepbf16, , map6, 98, vl, bf16, vl),
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2162,6 +2162,26 @@ static const struct evex {
{ { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */
{ { 0x5f }, 2, T, R, pfx_66, W0, Ln }, /* vmaxpbf16 */
{ { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */
+ { { 0x68 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2ibs */
+ { { 0x68 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttps2ibs */
+ { { 0x68 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvttbf162ibs */
+ { { 0x69 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2ibs */
+ { { 0x69 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2ibs */
+ { { 0x69 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtnebf162ibs */
+ { { 0x6a }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2iubs */
+ { { 0x6a }, 2, T, R, pfx_66, W0, Ln }, /* vcvttps2iubs */
+ { { 0x6a }, 2, T, R, pfx_f2, W0, Ln }, /* vcvttbf162iubs */
+ { { 0x6b }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2iubs */
+ { { 0x6b }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2iubs */
+ { { 0x6b }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtnebf162iubs */
+ { { 0x6c }, 2, T, R, pfx_no, Wn, Ln }, /* vcvttp{s,d}2udqs */
+ { { 0x6c }, 2, T, R, pfx_66, Wn, Ln }, /* vcvttp{s,d}2uqqs */
+ { { 0x6c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttss2usis */
+ { { 0x6c }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2usis */
+ { { 0x6d }, 2, T, R, pfx_no, Wn, Ln }, /* vcvttp{s,d}2dqs */
+ { { 0x6d }, 2, T, R, pfx_66, Wn, Ln }, /* vcvttp{s,d}2qqs */
+ { { 0x6d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttss2sis */
+ { { 0x6d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2sis */
{ { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */
{ { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */
{ { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -1547,6 +1547,19 @@ int x86emul_decode(struct x86_emulate_st
s->fp16 = true;
break;
+ case 0x68: /* vcvtt{ph,ps,bf16}2ibs */
+ case 0x69: /* vcvt{ph,ps,nebf16}2ibs */
+ case 0x6a: /* vcvtt{ph,ps,bf16}2iubs */
+ case 0x6b: /* vcvt{ph,ps,nebf16}2iubs */
+ if ( !s->evex.pfx || s->evex.pfx == vex_f2 )
+ s->fp16 = true;
+ /* fall through */
+ case 0x6c: /* vcvttp{s,d}2u{d,q}qs, vcvtts{s,d}2usis */
+ case 0x6d: /* vcvttp{s,d}2{d,q}qs, vcvtts{s,d}2sis */
+ d |= TwoOp;
+ s->simd_size = simd_other;
+ break;
+
case 0x6e: /* vmovw r/x/m16, xmm */
d = (d & ~SrcMask) | SrcMem16;
/* fall through */
@@ -1612,6 +1625,14 @@ int x86emul_decode(struct x86_emulate_st
--disp8scale;
break;
+ case 0x6c: /* vcvttps2uqqs and vcvts{s,d}2usi need special casing */
+ case 0x6d: /* vcvttps2qqs and vcvts{s,d}2si need special casing */
+ if ( s->evex.pfx == vex_66 && !s->evex.w && !s->evex.brs )
+ --disp8scale;
+ else if ( s->evex.pfx & VEX_PREFIX_SCALAR_MASK )
+ disp8scale = s->evex.pfx & VEX_PREFIX_DOUBLE_MASK ? 3 : 2;
+ break;
+
case 0x7a: case 0x7b: /* vcvt{,t}ph2qq need special casing */
if ( s->evex.pfx == vex_66 && !s->evex.brs )
disp8scale = s->evex.brs ? 1 : 2 + s->evex.lr;
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -8025,6 +8025,55 @@ x86_emulate(
op_bytes = 8 << evex.lr;
goto simd_zmm;
+ case X86EMUL_OPC_EVEX_F2(5, 0x68): /* vcvttbf162ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(5, 0x69): /* vcvtnebf162ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(5, 0x6a): /* vcvttbf162iubs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_F2(5, 0x6b): /* vcvtnebf162iubs [xyz]mm/mem,[xyz]mm{k} */
+ generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+ /* fall through */
+ case X86EMUL_OPC_EVEX (5, 0x68): /* vcvttph2ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x68): /* vcvttps2ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (5, 0x69): /* vcvtph2ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x69): /* vcvtps2ibs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (5, 0x6a): /* vcvttph2iubs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x6a): /* vcvttps2iubs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (5, 0x6b): /* vcvtph2iubs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x6b): /* vcvtps2iubs [xyz]mm/mem,[xyz]mm{k} */
+ generate_exception_if(evex.w, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ if ( ea.type != OP_REG || !evex.brs )
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ goto simd_zmm;
+
+ case X86EMUL_OPC_EVEX (5, 0x6c): /* vcvttps2udqs [xyz]mm/mem,[xyz]mm{k} */
+ /* vcvttpd2udqs [xyz]mm/mem,{x,y}mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x6c): /* vcvttps2uqqs {x,y}mm/mem,[xyz]mm{k} */
+ /* vcvttpd2uqqs [xyz]mm/mem,[xyz]mm{k} */
+ case X86EMUL_OPC_EVEX (5, 0x6d): /* vcvttps2dqs [xyz]mm/mem,[xyz]mm{k} */
+ /* vcvttpd2dqs [xyz]mm/mem,{x,y}mm{k} */
+ case X86EMUL_OPC_EVEX_66(5, 0x6d): /* vcvttps2qqs {x,y}mm/mem,[xyz]mm{k} */
+ /* vcvttpd2qqs [xyz]mm/mem,[xyz]mm{k} */
+ vcpu_must_have(avx10, 2);
+ if ( ea.type != OP_REG || !evex.brs )
+ avx512_vlen_check(false);
+ op_bytes = 8 << ((evex.w || !evex.pfx) + evex.lr);
+ goto simd_zmm;
+
+ CASE_SIMD_SCALAR_FP(_EVEX, 5, 0x6c): /* vcvtts{s,d}2usis xmm/mem,reg */
+ CASE_SIMD_SCALAR_FP(_EVEX, 5, 0x6d): /* vcvtts{s,d}2sis xmm/mem,reg */
+ generate_exception_if((evex.reg != 0xf || !evex.RX || !evex.R ||
+ evex.opmsk),
+ X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ if ( !evex.brs )
+ avx512_vlen_check(true);
+ else
+ generate_exception_if(ea.type != OP_REG || !evex.u, X86_EXC_UD);
+ get_fpu(X86EMUL_FPU_zmm);
+ opc = init_evex(stub);
+ goto cvts_2si;
+
case X86EMUL_OPC_EVEX_66(5, 0x78): /* vcvttph2uqq xmm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x79): /* vcvtph2uqq xmm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x7a): /* vcvttph2qq xmm/mem,[xyz]mm{k} */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 14/16] x86emul: support other AVX10.2 convert insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (12 preceding siblings ...)
2024-12-11 10:20 ` [PATCH v3 13/16] x86emul: support AVX10.2 saturating convert insns Jan Beulich
@ 2024-12-11 10:20 ` Jan Beulich
2024-12-11 10:21 ` [PATCH v3 15/16] x86emul: support SIMD MOVRS Jan Beulich
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:20 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Despite most of them being about conversion to BF8/HF8, they are still
somewhat similar to various existing convert insns.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
SDE: ???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -719,8 +719,22 @@ static const struct test avx10_2_all[] =
INSN(comxsd, f3, 0f, 2f, el, q, el),
INSN(comxsh, f2, map5, 2f, el, fp16, el),
INSN(comxss, f2, 0f, 2f, el, d, el),
+ INSN(cvt2ps2phx, 66, 0f38, 67, vl, d, vl),
+ INSN(cvtbiasph2bf8, , 0f38, 74, vl, fp16, vl),
+ INSN(cvtbiasph2bf8s, , map5, 74, vl, fp16, vl),
+ INSN(cvtbiasph2hf8, , map5, 18, vl, fp16, vl),
+ INSN(cvtbiasph2hf8s, , map5, 1b, vl, fp16, vl),
+ INSN(cvthf82ph, f2, map5, 1e, vl_2, b, vl),
+ INSN(cvtne2ph2bf8, f2, 0f38, 74, vl, fp16, vl),
+ INSN(cvtne2ph2bf8s, f2, map5, 74, vl, fp16, vl),
+ INSN(cvtne2ph2hf8, f2, map5, 18, vl, fp16, vl),
+ INSN(cvtne2ph2hf8s, f2, map5, 1b, vl, fp16, vl),
INSN(cvtnebf162ibs, f2, map5, 69, vl, bf16, vl),
INSN(cvtnebf162iubs, f2, map5, 6b, vl, bf16, vl),
+ INSN(cvtneph2bf8, f3, 0f38, 74, vl, fp16, vl),
+ INSN(cvtneph2bf8s, f3, map5, 74, vl, fp16, vl),
+ INSN(cvtneph2hf8, f3, map5, 18, vl, fp16, vl),
+ INSN(cvtneph2hf8s, f3, map5, 1b, vl, fp16, vl),
INSN(cvtph2ibs, , map5, 69, vl, fp16, vl),
INSN(cvtph2iubs, , map5, 6b, vl, fp16, vl),
INSN(cvtps2ibs, 66, map5, 69, vl, d, vl),
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1952,6 +1952,7 @@ static const struct evex {
{ { 0x64 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{d,q} */
{ { 0x65 }, 2, T, R, pfx_66, Wn, Ln }, /* vblendmp{s,d} */
{ { 0x66 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{b,w} */
+ { { 0x67 }, 2, T, R, pfx_66, W0, Ln }, /* vcvt2ps2phx */
{ { 0x68 }, 2, T, R, pfx_f2, Wn, Ln }, /* vp2intersect{d,q} */
{ { 0x70 }, 2, T, R, pfx_66, W1, Ln }, /* vpshldvw */
{ { 0x71 }, 2, T, R, pfx_66, Wn, Ln }, /* vpshldv{d,q} */
@@ -1959,6 +1960,9 @@ static const struct evex {
{ { 0x72 }, 2, T, R, pfx_f3, W1, Ln }, /* vcvtneps2bf16 */
{ { 0x72 }, 2, T, R, pfx_f2, W1, Ln }, /* vcvtne2ps2bf16 */
{ { 0x73 }, 2, T, R, pfx_66, Wn, Ln }, /* vpshrdv{d,q} */
+ { { 0x74 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2bf8 */
+ { { 0x74 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneph2bf8 */
+ { { 0x74 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtne2ph2bf8 */
{ { 0x75 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2{b,w} */
{ { 0x76 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2{d,q} */
{ { 0x77 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2p{s,d} */
@@ -2122,8 +2126,15 @@ static const struct evex {
}, evex_map5[] = {
{ { 0x10 }, 2, T, R, pfx_f3, W0, LIG }, /* vmovsh */
{ { 0x11 }, 2, T, W, pfx_f3, W0, LIG }, /* vmovsh */
+ { { 0x18 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2hf8 */
+ { { 0x18 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneph2hf8 */
+ { { 0x18 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtne2ph2hf8 */
+ { { 0x1b }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2hf8s */
+ { { 0x1b }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneph2hf8s */
+ { { 0x1b }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtne2ph2hf8s */
{ { 0x1d }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2phx */
{ { 0x1d }, 2, T, R, pfx_no, W0, LIG }, /* vcvtss2sh */
+ { { 0x1e }, 2, T, R, pfx_f2, W0, Ln }, /* cvthf82ph */
{ { 0x2a }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsi2sh */
{ { 0x2c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2si */
{ { 0x2d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsh2si */
@@ -2184,6 +2195,9 @@ static const struct evex {
{ { 0x6d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2sis */
{ { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */
{ { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */
+ { { 0x74 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2bf8s */
+ { { 0x74 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneph2bf8s */
+ { { 0x74 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtne2ph2bf8s */
{ { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */
{ { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttph2uqq */
{ { 0x78 }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2usi */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -378,8 +378,10 @@ static const struct ext0f38_table {
[0x62] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_bw },
[0x63] = { .simd_size = simd_packed_int, .to_mem = 1, .two_op = 1, .d8s = d8s_bw },
[0x64 ... 0x66] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
+ [0x67] = { .simd_size = simd_other, .d8s = d8s_vl },
[0x68] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
[0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
+ [0x74] = { .simd_size = simd_other, .d8s = d8s_vl },
[0x75 ... 0x76] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
[0x77] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
[0x78] = { .simd_size = simd_other, .two_op = 1 },
@@ -1445,6 +1447,15 @@ int x86emul_decode(struct x86_emulate_st
s->simd_size = ext0f38_table[b].simd_size;
if ( evex_encoded() )
{
+ switch ( b )
+ {
+ case 0x74: /* cvt{bias,ne,ne2}ph2bf8 */
+ s->fp16 = true;
+ if ( s->evex.pfx != vex_f2 )
+ d |= TwoOp;
+ break;
+ }
+
/*
* VPMOVUS* are identical to VPMOVS* Disp8-scaling-wise, but
* their attributes don't match those of the vex_66 encoded
@@ -1592,6 +1603,23 @@ int x86emul_decode(struct x86_emulate_st
switch ( b )
{
+ case 0x18: /* vcvt{bias,ne,ne2}ph2hf8 */
+ case 0x1b: /* vcvt{bias,ne,ne2}ph2hf8s */
+ case 0x74: /* vcvt{bias,ne,ne2}ph2bf8s */
+ s->fp16 = true;
+ d = DstReg | SrcMem;
+ if ( s->evex.pfx != vex_f2 )
+ d |= TwoOp;
+ s->simd_size = simd_other;
+ disp8scale = s->evex.brs ? 1 : 4 + s->evex.lr;
+ break;
+
+ case 0x1e: /* vcvthf82ph */
+ d = DstReg | SrcMem | TwoOp;
+ s->simd_size = simd_other;
+ disp8scale = 3 + s->evex.lr;
+ break;
+
case 0x78:
case 0x79:
/* vcvt{,t}ph2u{d,q}q need special casing */
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6269,6 +6269,29 @@ x86_emulate(
}
goto simd_zmm;
+ case X86EMUL_OPC_EVEX (0x0f38, 0x74): /* vcvtbiasph2bf8 [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x74): /* vcvtneph2bf8 [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F2(0x0f38, 0x74): /* vcvtne2ph2bf8 [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX ( 5, 0x18): /* vcvtbiasph2hf8 [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F3( 5, 0x18): /* vcvtneph2hf8 [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F2( 5, 0x18): /* vcvtne2ph2hf8 [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX ( 5, 0x1b): /* vcvtbiasph2hf8s [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F3( 5, 0x1b): /* vcvtneph2hf8s [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F2( 5, 0x1b): /* vcvtne2ph2hf8s [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX ( 5, 0x74): /* vcvtbiasph2bf8s [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F3( 5, 0x74): /* vcvtneph2bf8s [xyz]mm,[xyz]mm/mem{k} */
+ case X86EMUL_OPC_EVEX_F2( 5, 0x74): /* vcvtne2ph2bf8s [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */
+ generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD);
+ /* fall through */
+ case X86EMUL_OPC_EVEX_66(0x0f38, 0x67): /* vcvt2ps2phx [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */
+ generate_exception_if(evex.w, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ if ( ea.type != OP_REG || !evex.brs )
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ fault_suppression = false;
+ goto simd_zmm;
+
case X86EMUL_OPC_EVEX_F2(0x0f38, 0x68): /* vp2intersect{d,q} [xyz]mm/mem,[xyz]mm,k+1 */
host_and_vcpu_must_have(avx512_vp2intersect);
generate_exception_if(evex.opmsk || !evex.r || !evex.R, X86_EXC_UD);
@@ -7965,6 +7988,14 @@ x86_emulate(
generate_exception_if(evex.w, X86_EXC_UD);
goto avx512f_all_fp;
+ case X86EMUL_OPC_EVEX_F2(5, 0x1e): /* vcvthf82ph [xyz]mm,[xyz]mm/mem{k} */
+ generate_exception_if(evex.w || evex.brs, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ if ( ea.type != OP_REG || !evex.brs )
+ avx512_vlen_check(false);
+ op_bytes = 8 << evex.lr;
+ goto simd_zmm;
+
case X86EMUL_OPC_EVEX_66(5, 0x42): /* vgetexppbf16 [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x51): /* vsqrtnepbf16 [xyz]mm/mem,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(5, 0x58): /* vaddnepbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 15/16] x86emul: support SIMD MOVRS
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (13 preceding siblings ...)
2024-12-11 10:20 ` [PATCH v3 14/16] x86emul: support other AVX10.2 " Jan Beulich
@ 2024-12-11 10:21 ` Jan Beulich
2024-12-11 10:22 ` [PATCH v3 16/16] x86emul: support AVX10.2 forms of SM4 insns Jan Beulich
2024-12-11 10:29 ` [PATCH v3 00/16] x86: support AVX10 Jan Beulich
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:21 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
As we ignore cachability aspects of insns, they're treated like simple
VMOVs.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
SDE: -???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -814,6 +814,13 @@ static const struct test avx10_2_128[] =
INSN(movw, f3, map5, 7e, el, fp16, el),
};
+static const struct test movrs_all[] = {
+ INSN(movrsb, f2, map5, 6f, vl, b, vl),
+ INSN(movrsd, f3, map5, 6f, vl, d_nb, vl),
+ INSN(movrsq, f3, map5, 6f, vl, q_nb, vl),
+ INSN(movrsw, f2, map5, 6f, vl, w, vl),
+};
+
static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
static const unsigned char vl_128[] = { VL_128 };
static const unsigned char vl_no128[] = { VL_512, VL_256 };
@@ -1236,6 +1243,10 @@ void evex_disp8_test(void *instr, struct
run(cpu_has_avx10_2, avx10_2, all);
run(cpu_has_avx10_2, avx10_2, 128);
+ if ( cpu_has_avx10_2 )
+ {
+ run(ctxt->addr_size == 64 && cpu_has_movrs, movrs, all);
+ }
#undef run
}
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2195,6 +2195,8 @@ static const struct evex {
{ { 0x6d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2sis */
{ { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */
{ { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */
+ { { 0x6f }, 2, T, R, pfx_f3, Wn, Ln }, /* vmovrs{d,q} */
+ { { 0x6f }, 2, T, R, pfx_f2, Wn, Ln }, /* vmovrs{b,w} */
{ { 0x74 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2bf8s */
{ { 0x74 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtneph2bf8s */
{ { 0x74 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtne2ph2bf8s */
--- a/tools/tests/x86_emulator/x86-emulate.h
+++ b/tools/tests/x86_emulator/x86-emulate.h
@@ -201,6 +201,7 @@ void wrpkru(unsigned int val);
xcr0_mask(0xe6))
#define cpu_has_cmpccxadd cpu_policy.feat.cmpccxadd
#define cpu_has_avx_ifma (cpu_policy.feat.avx_ifma && xcr0_mask(6))
+#define cpu_has_movrs cpu_policy.feat.movrs
#define cpu_has_avx_vnni_int8 (cpu_policy.feat.avx_vnni_int8 && \
xcr0_mask(6))
#define cpu_has_avx_ne_convert (cpu_policy.feat.avx_ne_convert && \
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6298,6 +6298,17 @@ x86_emulate(
op_bytes = 16 << evex.lr;
goto avx512f_no_sae;
+ case X86EMUL_OPC_EVEX_F2(0x0f38, 0x6f): /* vmovrs{b,w} mem,[xyz]mm{k} */
+ elem_bytes = 1 << evex.w;
+ /* fall through */
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x6f): /* vmovrs{d,q} mem,[xyz]mm{k} */
+ generate_exception_if(ea.type != OP_MEM || evex.brs, X86_EXC_UD);
+ vcpu_must_have(avx10, 2);
+ vcpu_must_have(movrs);
+ avx512_vlen_check(false);
+ op_bytes = 16 << evex.lr;
+ goto simd_zmm;
+
case X86EMUL_OPC_EVEX_66(0x0f38, 0x70): /* vpshldvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
case X86EMUL_OPC_EVEX_66(0x0f38, 0x72): /* vpshrdvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
generate_exception_if(!evex.w, X86_EXC_UD);
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 16/16] x86emul: support AVX10.2 forms of SM4 insns
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (14 preceding siblings ...)
2024-12-11 10:21 ` [PATCH v3 15/16] x86emul: support SIMD MOVRS Jan Beulich
@ 2024-12-11 10:22 ` Jan Beulich
2024-12-11 10:29 ` [PATCH v3 00/16] x86: support AVX10 Jan Beulich
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:22 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
Simply clone the VEX-encoded handling to cover the EVEX forms.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
There's a TODO left due to lack of SDE support. Invoking the test would
fail at present, for SDE 9.44.0 advertising both AVX10.2 and SM4, while
not supporting the new EVEX encodings just yet.
---
SDE: -???
---
v3: New.
--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -821,6 +821,11 @@ static const struct test movrs_all[] = {
INSN(movrsw, f2, map5, 6f, vl, w, vl),
};
+static const struct test sm4_all[] = {
+ INSN(sm4key4, f3, 0f38, da, vl, d_nb, vl),
+ INSN(sm4rnds4, f2, 0f38, da, vl, d_nb, vl),
+};
+
static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 };
static const unsigned char vl_128[] = { VL_128 };
static const unsigned char vl_no128[] = { VL_512, VL_256 };
@@ -1246,6 +1251,7 @@ void evex_disp8_test(void *instr, struct
if ( cpu_has_avx10_2 )
{
run(ctxt->addr_size == 64 && cpu_has_movrs, movrs, all);
+ (void)sm4_all;//todo run(cpu_has_sm4, sm4, all);
}
#undef run
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -2046,6 +2046,8 @@ static const struct evex {
{ { 0xd3 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuuds */
{ { 0xd3 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusds */
{ { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */
+ { { 0xda }, 2, T, R, pfx_f3, W0, Ln }, /* vsm4key4 */
+ { { 0xda }, 2, T, R, pfx_f2, W0, Ln }, /* vsm4rnds4 */
{ { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */
{ { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */
{ { 0xde }, 2, T, R, pfx_66, WIG, Ln }, /* vaesdec */
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -439,7 +439,7 @@ static const struct ext0f38_table {
[0xd3] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xd6] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq },
- [0xda] = { .simd_size = simd_other },
+ [0xda] = { .simd_size = simd_other, .d8s = d8s_vl },
[0xdb] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xdc ... 0xdf] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
[0xe0 ... 0xef] = { .to_mem = 1 },
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -6928,6 +6928,14 @@ x86_emulate(
op_bytes = 16 << vex.l;
goto simd_0f_ymm;
+ case X86EMUL_OPC_EVEX_F3(0x0f38, 0xda): /* vsm4key4 [xyz]mm/mem,[xyz]mm,[xyz]mm */
+ case X86EMUL_OPC_EVEX_F2(0x0f38, 0xda): /* vsm4rnds4 [xyz]mm/mem,[xyz]mm,[xyz]mm */
+ vcpu_must_have(avx10, 2);
+ host_and_vcpu_must_have(sm4);
+ generate_exception_if(evex.w || evex.brs || evex.opmsk, X86_EXC_UD);
+ op_bytes = 16 << evex.lr;
+ goto simd_zmm;
+
case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */
case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 00/16] x86: support AVX10
2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
` (15 preceding siblings ...)
2024-12-11 10:22 ` [PATCH v3 16/16] x86emul: support AVX10.2 forms of SM4 insns Jan Beulich
@ 2024-12-11 10:29 ` Jan Beulich
16 siblings, 0 replies; 18+ messages in thread
From: Jan Beulich @ 2024-12-11 10:29 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org; +Cc: Andrew Cooper, Roger Pau Monné
On 11.12.2024 11:09, Jan Beulich wrote:
> AVX10.1 is just a re-branding of certain AVX512 (sub)features, i.e.
> adds no new instructions. Therefore it's mostly relaxation that needs
> doing, plus dealing with the 256-bit-only case that AVX512 itself
> does not allow for. Luckily an unnecessary restriction on the mask
> register insns was taken out again, simplifying the actual emulator
> adjustments quite a bit.
>
> AVX10.2 is adding quite a few new insns, support for which (new in v3)
> is roughly added chapter-wise as the spec has them (perhaps not in the
> order of the chapters there).
>
> While it probably can be rebased ahead, the series in this form
> depends on the previously submitted "[PATCH v5 0/3] x86/CPUID: leaf
> pruning". It also is assumed to go on top of "[PATCH v7 0/7] x86emul:
> misc additions", albeit at most contextual dependencies ought to exit
> there.
>
> I've tried to be very careful in rebasing ahead of other emulator
> patches I've been carrying, but almost all testing I've done is with
> all of those collectively in place.
>
> 01: x86/CPUID: enable AVX10 leaf
> 02: x86emul: support AVX10.1
> 03: x86emul/test: use simd_check_avx512*() in main()
> 04: x86emul/test: drop cpu_has_avx512vl
> 05: x86emul: AVX10.1 testing
> 06: x86emul/test: engage AVX512VL via command line option
> 07: x86emul: support AVX10.2 256-bit embedded rounding / SAE
> 08: x86emul: support AVX10.2 scalar compare insns
> 09: x86emul: support AVX10.2 partial copy insns
> 10: x86emul: support AVX10.2 media insns
> 11: x86emul: support AVX10.2 minmax insns
> 12: x86emul: support AVX10.2 media insns
> 13: x86emul: support AVX10.2 saturating convert insns
> 14: x86emul: support other AVX10.2 convert insns
> 15: x86emul: support SIMD MOVRS
> 16: x86emul: support AVX10.2 forms of SM4 insns
I should probably have mentioned here two further opens:
1) Testing. So far I haven't been able to think of a good approach to test
some (most?) of the new insns, beyond the EVEX Disp8 and predicates
testing that's being taken care of in individual patches.
2) Supposedly there is a way to constrain guests to 256-bit vector size via
a VMCS setting. The spec has no details beyond mentioning this fact.
Jan
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2024-12-11 10:09 [PATCH v3 00/16] x86: support AVX10 Jan Beulich
2024-12-11 10:11 ` [PATCH v3 01/16] x86/CPUID: enable AVX10 leaf Jan Beulich
2024-12-11 10:11 ` [PATCH v3 02/16] x86emul: support AVX10.1 Jan Beulich
2024-12-11 10:12 ` [PATCH v3 03/16] x86emul/test: use simd_check_avx512*() in main() Jan Beulich
2024-12-11 10:12 ` [PATCH v3 04/16] x86emul/test: drop cpu_has_avx512vl Jan Beulich
2024-12-11 10:13 ` [PATCH v3 05/16] x86emul: AVX10.1 testing Jan Beulich
2024-12-11 10:13 ` [PATCH v3 06/16] x86emul/test: engage AVX512VL via command line option Jan Beulich
2024-12-11 10:14 ` [PATCH v3 07/16] x86emul: support AVX10.2 256-bit embedded rounding / SAE Jan Beulich
2024-12-11 10:17 ` [PATCH v3 08/16] x86emul: support AVX10.2 scalar compare insns Jan Beulich
2024-12-11 10:18 ` [PATCH v3 09/16] x86emul: support AVX10.2 partial copy insns Jan Beulich
2024-12-11 10:18 ` [PATCH v3 10/16] x86emul: support AVX10.2 media insns Jan Beulich
2024-12-11 10:19 ` [PATCH v3 11/16] x86emul: support AVX10.2 minmax insns Jan Beulich
2024-12-11 10:19 ` [PATCH v3 12/16] x86emul: support AVX10.2 BFloat16 insns Jan Beulich
2024-12-11 10:20 ` [PATCH v3 13/16] x86emul: support AVX10.2 saturating convert insns Jan Beulich
2024-12-11 10:20 ` [PATCH v3 14/16] x86emul: support other AVX10.2 " Jan Beulich
2024-12-11 10:21 ` [PATCH v3 15/16] x86emul: support SIMD MOVRS Jan Beulich
2024-12-11 10:22 ` [PATCH v3 16/16] x86emul: support AVX10.2 forms of SM4 insns Jan Beulich
2024-12-11 10:29 ` [PATCH v3 00/16] x86: support AVX10 Jan Beulich
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