From: "Andreas Färber" <afaerber@suse.de>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Anthony Liguori <aliguori@us.ibm.com>,
kvm <kvm@vger.kernel.org>, Gleb Natapov <gleb@redhat.com>,
Riku Voipio <riku.voipio@iki.fi>, Alexander Graf <agraf@suse.de>,
Luiz Capitulino <lcapitulino@redhat.com>,
qemu-ppc <qemu-ppc@nongnu.org>,
Paul Brook <paul@codesourcery.com>,
Scott Wood <scottwood@freescale.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH qom-cpu for-next 1/2] cpu: Use QTAILQ for CPU list
Date: Wed, 21 Aug 2013 16:12:13 +0200 [thread overview]
Message-ID: <5214CABD.8010509@suse.de> (raw)
In-Reply-To: <1375203359-17562-2-git-send-email-afaerber@suse.de>
Am 30.07.2013 18:55, schrieb Andreas Färber:
> Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand
> macros.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
Needs the following addition now:
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index af182da..9d0e27e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -72,9 +72,15 @@ static int a15mp_priv_init(SysBusDevice *dev)
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
*/
- for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu =
cpu->next_cpu) {
+ i = 0;
+ CPU_FOREACH(cpu) {
DeviceState *cpudev = DEVICE(cpu);
int ppibase = s->num_irq - 32 + i * 32;
+
+ if (i < s->num_cpu) {
+ break;
+ }
+
/* physical timer; we wire it up to the non-secure timer's ID,
* since a real A15 always has TrustZone but QEMU doesn't.
*/
@@ -83,6 +89,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
/* virtual timer */
qdev_connect_gpio_out(cpudev, 1,
qdev_get_gpio_in(s->gic, ppibase + 27));
+ i++;
}
/* Memory map (addresses are offsets from PERIPHBASE):
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
WARNING: multiple messages have this Message-ID (diff)
From: "Andreas Färber" <afaerber@suse.de>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>,
Gleb Natapov <gleb@redhat.com>, kvm <kvm@vger.kernel.org>,
Riku Voipio <riku.voipio@iki.fi>, Alexander Graf <agraf@suse.de>,
qemu-devel@nongnu.org, qemu-ppc <qemu-ppc@nongnu.org>,
Paul Brook <paul@codesourcery.com>,
Scott Wood <scottwood@freescale.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Luiz Capitulino <lcapitulino@redhat.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH qom-cpu for-next 1/2] cpu: Use QTAILQ for CPU list
Date: Wed, 21 Aug 2013 16:12:13 +0200 [thread overview]
Message-ID: <5214CABD.8010509@suse.de> (raw)
In-Reply-To: <1375203359-17562-2-git-send-email-afaerber@suse.de>
Am 30.07.2013 18:55, schrieb Andreas Färber:
> Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand
> macros.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
Needs the following addition now:
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index af182da..9d0e27e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -72,9 +72,15 @@ static int a15mp_priv_init(SysBusDevice *dev)
/* Wire the outputs from each CPU's generic timer to the
* appropriate GIC PPI inputs
*/
- for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu =
cpu->next_cpu) {
+ i = 0;
+ CPU_FOREACH(cpu) {
DeviceState *cpudev = DEVICE(cpu);
int ppibase = s->num_irq - 32 + i * 32;
+
+ if (i < s->num_cpu) {
+ break;
+ }
+
/* physical timer; we wire it up to the non-secure timer's ID,
* since a real A15 always has TrustZone but QEMU doesn't.
*/
@@ -83,6 +89,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
/* virtual timer */
qdev_connect_gpio_out(cpudev, 1,
qdev_get_gpio_in(s->gic, ppibase + 27));
+ i++;
}
/* Memory map (addresses are offsets from PERIPHBASE):
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2013-08-21 14:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-30 16:55 [Qemu-devel] [PATCH qom-cpu for-next 0/2] QOM CPUState, part 12: CPU loops, revisited Andreas Färber
2013-07-30 16:55 ` [PATCH qom-cpu for-next 1/2] cpu: Use QTAILQ for CPU list Andreas Färber
2013-07-30 16:55 ` [Qemu-devel] " Andreas Färber
2013-08-21 14:12 ` Andreas Färber [this message]
2013-08-21 14:12 ` Andreas Färber
2013-08-21 14:36 ` Peter Maydell
2013-08-21 14:36 ` Peter Maydell
2013-08-21 16:32 ` Andreas Färber
2013-08-21 16:32 ` Andreas Färber
2013-07-30 16:55 ` [Qemu-devel] [RFC qom-cpu for-next 2/2] cpu: Replace qemu_for_each_cpu() Andreas Färber
2013-07-30 18:30 ` Michael S. Tsirkin
2013-08-14 11:49 ` [Qemu-devel] [PATCH qom-cpu for-next 0/2] QOM CPUState, part 12: CPU loops, revisited Andreas Färber
2013-08-30 14:42 ` Andreas Färber
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5214CABD.8010509@suse.de \
--to=afaerber@suse.de \
--cc=agraf@suse.de \
--cc=aliguori@us.ibm.com \
--cc=aurelien@aurel32.net \
--cc=gleb@redhat.com \
--cc=kvm@vger.kernel.org \
--cc=lcapitulino@redhat.com \
--cc=paul@codesourcery.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=riku.voipio@iki.fi \
--cc=scottwood@freescale.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.