From: Claudio Fontana <claudio.fontana@huawei.com>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3 01/29] tcg-aarch64: Set ext based on TCG_OPF_64BIT
Date: Thu, 12 Sep 2013 10:25:16 +0200 [thread overview]
Message-ID: <52317A6C.20400@huawei.com> (raw)
In-Reply-To: <1378144503-15808-2-git-send-email-rth@twiddle.net>
On 02.09.2013 19:54, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/aarch64/tcg-target.c | 28 +++++++---------------------
> 1 file changed, 7 insertions(+), 21 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
> index 55ff700..5b067fe 100644
> --- a/tcg/aarch64/tcg-target.c
> +++ b/tcg/aarch64/tcg-target.c
> @@ -1105,9 +1105,9 @@ static inline void tcg_out_load_pair(TCGContext *s, TCGReg addr,
> static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> const TCGArg *args, const int *const_args)
> {
> - /* ext will be set in the switch below, which will fall through to the
> - common code. It triggers the use of extended regs where appropriate. */
> - int ext = 0;
> + /* 99% of the time, we can signal the use of extension registers
> + by looking to see if the opcode handles 64-bit data. */
> + bool ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
>
> switch (opc) {
> case INDEX_op_exit_tb:
> @@ -1163,7 +1163,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_mov_i64:
> - ext = 1; /* fall through */
> case INDEX_op_mov_i32:
> tcg_out_movr(s, ext, args[0], args[1]);
> break;
> @@ -1176,43 +1175,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_add_i64:
> - ext = 1; /* fall through */
> case INDEX_op_add_i32:
> tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0);
> break;
>
> case INDEX_op_sub_i64:
> - ext = 1; /* fall through */
> case INDEX_op_sub_i32:
> tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2], 0);
> break;
>
> case INDEX_op_and_i64:
> - ext = 1; /* fall through */
> case INDEX_op_and_i32:
> tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2], 0);
> break;
>
> case INDEX_op_or_i64:
> - ext = 1; /* fall through */
> case INDEX_op_or_i32:
> tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2], 0);
> break;
>
> case INDEX_op_xor_i64:
> - ext = 1; /* fall through */
> case INDEX_op_xor_i32:
> tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2], 0);
> break;
>
> case INDEX_op_mul_i64:
> - ext = 1; /* fall through */
> case INDEX_op_mul_i32:
> tcg_out_mul(s, ext, args[0], args[1], args[2]);
> break;
>
> case INDEX_op_shl_i64:
> - ext = 1; /* fall through */
> case INDEX_op_shl_i32:
> if (const_args[2]) { /* LSL / UBFM Wd, Wn, (32 - m) */
> tcg_out_shl(s, ext, args[0], args[1], args[2]);
> @@ -1222,7 +1214,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_shr_i64:
> - ext = 1; /* fall through */
> case INDEX_op_shr_i32:
> if (const_args[2]) { /* LSR / UBFM Wd, Wn, m, 31 */
> tcg_out_shr(s, ext, args[0], args[1], args[2]);
> @@ -1232,7 +1223,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_sar_i64:
> - ext = 1; /* fall through */
> case INDEX_op_sar_i32:
> if (const_args[2]) { /* ASR / SBFM Wd, Wn, m, 31 */
> tcg_out_sar(s, ext, args[0], args[1], args[2]);
> @@ -1242,7 +1232,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_rotr_i64:
> - ext = 1; /* fall through */
> case INDEX_op_rotr_i32:
> if (const_args[2]) { /* ROR / EXTR Wd, Wm, Wm, m */
> tcg_out_rotr(s, ext, args[0], args[1], args[2]);
> @@ -1252,7 +1241,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_rotl_i64:
> - ext = 1; /* fall through */
> case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */
> if (const_args[2]) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */
> tcg_out_rotl(s, ext, args[0], args[1], args[2]);
> @@ -1265,14 +1253,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_brcond_i64:
> - ext = 1; /* fall through */
> case INDEX_op_brcond_i32: /* CMP 0, 1, cond(2), label 3 */
> tcg_out_cmp(s, ext, args[0], args[1], 0);
> tcg_out_goto_label_cond(s, args[2], args[3]);
> break;
>
> case INDEX_op_setcond_i64:
> - ext = 1; /* fall through */
> case INDEX_op_setcond_i32:
> tcg_out_cmp(s, ext, args[1], args[2], 0);
> tcg_out_cset(s, 0, args[0], args[3]);
There's not point to change to 'bool' if you pass '0': either we keep as int, and we pass 0,
or we change to bool, and we pass 'false'.
There are instances of this also in successive patches, I point out only this one, but it should be checked in the whole series.
> @@ -1315,9 +1301,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> tcg_out_qemu_st(s, args, 3);
> break;
>
> - case INDEX_op_bswap64_i64:
> - ext = 1; /* fall through */
> case INDEX_op_bswap32_i64:
> + /* Despite the _i64, this is a 32-bit bswap. */
> + ext = 0;
> + /* FALLTHRU */
> + case INDEX_op_bswap64_i64:
we waste too much y space here, which gives context and is a scarse resource.
What about
case INDEX_op_bswap32_i64: /* Despite the _i64, this is a 32-bit bswap. */
ext = false; /* FALLTHRU */
> case INDEX_op_bswap32_i32:
> tcg_out_rev(s, ext, args[0], args[1]);
> break;
> @@ -1327,12 +1315,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
>
> case INDEX_op_ext8s_i64:
> - ext = 1; /* fall through */
> case INDEX_op_ext8s_i32:
> tcg_out_sxt(s, ext, 0, args[0], args[1]);
> break;
> case INDEX_op_ext16s_i64:
> - ext = 1; /* fall through */
> case INDEX_op_ext16s_i32:
> tcg_out_sxt(s, ext, 1, args[0], args[1]);
> break;
>
C.
next prev parent reply other threads:[~2013-09-12 8:25 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-02 17:54 [Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 01/29] tcg-aarch64: Set ext based on TCG_OPF_64BIT Richard Henderson
2013-09-12 8:25 ` Claudio Fontana [this message]
2013-09-12 8:58 ` Peter Maydell
2013-09-12 9:01 ` Claudio Fontana
2013-09-12 13:21 ` Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 02/29] tcg-aarch64: Change all ext variables to bool Richard Henderson
2013-09-12 8:29 ` Claudio Fontana
2013-09-12 13:45 ` Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 03/29] tcg-aarch64: Don't handle mov/movi in tcg_out_op Richard Henderson
2013-09-12 8:30 ` Claudio Fontana
2013-09-12 14:02 ` Richard Henderson
2013-09-12 14:31 ` Claudio Fontana
2013-09-12 14:35 ` Peter Maydell
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 04/29] tcg-aarch64: Hoist common argument loads " Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 05/29] tcg-aarch64: Change enum aarch64_arith_opc to AArch64Insn Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 06/29] tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 07/29] tcg-aarch64: Introduce tcg_fmt_* functions Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 08/29] tcg-aarch64: Introduce tcg_fmt_Rdn_aimm Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 09/29] tcg-aarch64: Implement mov with tcg_fmt_* functions Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 10/29] tcg-aarch64: Handle constant operands to add, sub, and compare Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 11/29] tcg-aarch64: Handle constant operands to and, or, xor Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 12/29] tcg-aarch64: Support andc, orc, eqv, not Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 13/29] tcg-aarch64: Handle zero as first argument to sub Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 14/29] tcg-aarch64: Support movcond Richard Henderson
2013-09-09 15:09 ` Claudio Fontana
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 15/29] tcg-aarch64: Support deposit Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 16/29] tcg-aarch64: Support add2, sub2 Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 17/29] tcg-aarch64: Support muluh, mulsh Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 18/29] tcg-aarch64: Support div, rem Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 19/29] tcg-aarch64: Introduce tcg_fmt_Rd_uimm_s Richard Henderson
2013-09-05 13:32 ` Claudio Fontana
2013-09-05 15:41 ` Richard Henderson
2013-09-06 9:06 ` Claudio Fontana
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 20/29] tcg-aarch64: Improve tcg_out_movi Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 21/29] tcg-aarch64: Avoid add with zero in tlb load Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 22/29] tcg-aarch64: Use adrp in tcg_out_movi Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 23/29] tcg-aarch64: Pass return address to load/store helpers directly Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 24/29] tcg-aarch64: Use tcg_out_call for qemu_ld/st Richard Henderson
2013-09-02 17:54 ` [Qemu-devel] [PATCH v3 25/29] tcg-aarch64: Use symbolic names for branches Richard Henderson
2013-09-02 17:55 ` [Qemu-devel] [PATCH v3 26/29] tcg-aarch64: Implement tcg_register_jit Richard Henderson
2013-09-02 17:55 ` [Qemu-devel] [PATCH v3 27/29] tcg-aarch64: Reuse FP and LR in translated code Richard Henderson
2013-09-02 17:55 ` [Qemu-devel] [PATCH v3 28/29] tcg-aarch64: Introduce tcg_out_ldst_pair Richard Henderson
2013-09-02 17:55 ` [Qemu-devel] [PATCH v3 29/29] tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check Richard Henderson
2013-09-03 7:37 ` [Qemu-devel] [PATCH v3 00/29] tcg-aarch64 improvements Richard W.M. Jones
2013-09-03 7:42 ` Laurent Desnogues
2013-09-03 8:00 ` Peter Maydell
2013-09-09 8:13 ` Claudio Fontana
2013-09-09 14:08 ` Richard Henderson
2013-09-09 15:02 ` Claudio Fontana
2013-09-09 15:04 ` Peter Maydell
2013-09-09 15:07 ` Richard Henderson
2013-09-10 8:27 ` Claudio Fontana
2013-09-10 8:45 ` Peter Maydell
2013-09-12 8:03 ` Claudio Fontana
2013-09-12 8:55 ` Peter Maydell
2013-09-10 13:16 ` Richard Henderson
2013-09-12 8:11 ` Claudio Fontana
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