Re: [DISCUSSION] Hexagon code inside kernel

[cotulla@yandex.ua]

> šYou're comparing arm performance with QDSP6 by writing pessimal QDSP6
> šcode that does single-byte moves and keeps half the execution units
> šidle. You're going to get some extremely useful numbers out of that,
> šaren't you? (Even their uClibc port had an assembly optimized
> šmemmove().)
Well, is it simular to usual C/C++ code task and results of compilation?
Until you will do a manual assembler optimization.

> šIs your arm code also doing single byte moves, with the requisite
> šbit-shifting and masking that doing that on arm entails (since last I
> šchecked arm hasn't actually _got_ instructions that handle bytes,
> šalthough maybe it went into thumb2 or v7 or v8 when I wasn't
> šlooking...)?
ARM has LDRB and STRB instructions long time ago (ever in ARMv4)

Okay, seems this is really bad test.


> šSpecifically, the v2 hardware (in the snapdragon chipset in the Nexus
> šOne) has 6 register profiles (for the 6 pipeline stages, acting as
> š6-way SMP) but performance peaked at "make -j 3" which ran very
> šslightly faster than "make -j 4", and then -j 5 and -j 6 were each
> šnoticeably slower (due to TLB thrashing).
Intersting to know that. 
I want to get SSH access to got console and interaction with system.


> šI believe that v3 had already taped out by then (late 2010, but it had
> šfewer pipeline stages and thus register profiles anyway), and then v4
> šwas going to increase the TLB entries. What actually shipped was after
> šmy time, dunno the details.
v3 should be rather close to v2, but v4 seems to have few new features.
At the current moment all v2 source code works on v3.


-Cotulla