From: cotulla@yandex.ua
To: linux-hexagon@vger.kernel.org
Subject: Re: [DISCUSSION] Hexagon code inside kernel
Date: Wed, 27 Feb 2013 00:25:50 +0400 [thread overview]
Message-ID: <9881361910350@web24g.yandex.ru> (raw)
In-Reply-To: <CAHrUA35uwyu5mX3MPxC7AV6qWZ_R6DdBJLp=s78m-1hd3S2RCg@mail.gmail.com>
>
> šOne of the worst design errors in that code is that base addresses
> šwere made into compile-time constants, and then, to add serious injury
> što insult, a lot of complicated macros were written to obtain various
> šrelative offsets. šThe problem being that the hexagon uses exactly the
> šsame offsets, but just different base addresses -- and they're
> šrun-time configurable, e.g. by bootloader or by device tree. šDevice
> štree support for hexagon was planned, not sure about ARM.
>
for me it's normal to have hardcoded base addresses. it's not so bad.
I am talking about more general problems like useless code or code without enough data checks in my opinion.
Hexagon has same addresses for most shared devices except the private ones - like timers and second level interrupt controller.
For example, I am using exactly same base address for USB and it works.
> šI had started work on this, but I don't remember that I ever got it
> šclean enough to submit upstream. šThat plus the fact that interrupt
> šrouting was different: šhexagon has both second and third-level
> šinterrupt controllers, with ethernet being on a third-level
> šcontroller. šI'd gotten much/most of the 2nd-level code done, and some
> šof the 3rd-level code done, and I think its in the mainline kernel
> šnow, although I remember planning to do some more simplification and
> šcleanup.
Hm it seems dependent from SoC.
In QDS8250B there are two second level interrupt controllers (SIRC)
In common it can handle (32 - 2) + 2 * 32 interrupts.
I already got SIRC to work and receive USB interrupts without problems.
> šYes, that sounds right. šSorry, forgot about that.
> šHmm. Either that or volatile needs to be added to the upstream
> šdrivers: this is an issue for a variety of arches, not just hexagon.
> šCertainly powerpc treats treats uncached and i/o access in a very
> šdifferent way than memory access, and if you don't do it right, life
> šwill be painful.
Probably. It's just a thing which should be extremely careful looked during low level development for Hexagon - I am already few times was "catched" by that rule :-P
-Cotulla
next prev parent reply other threads:[~2013-02-26 20:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-15 14:28 [DISCUSSION] Hexagon code inside kernel cotulla
[not found] ` <CAHrUA364XES66kXhr0Gg1dh_MQBAS0+R8Q4x+EY3dgz6s=QRww@mail.gmail.com>
2013-02-15 22:33 ` Linas Vepstas
2013-02-16 1:35 ` cotulla
2013-02-16 2:34 ` Linas Vepstas
2013-02-16 12:39 ` cotulla
2013-02-16 17:33 ` Linas Vepstas
2013-02-16 19:21 ` cotulla
2013-02-19 4:36 ` rkuo
2013-02-19 14:29 ` Linas Vepstas
2013-02-20 1:07 ` cotulla
2013-02-20 1:17 ` cotulla
2013-02-23 4:24 ` Rob Landley
2013-02-24 12:00 ` cotulla
2013-02-24 16:32 ` Linas Vepstas
2013-02-24 17:29 ` cotulla
2013-02-24 21:03 ` Linas Vepstas
2013-02-25 17:26 ` Rob Landley
2013-02-26 18:54 ` cotulla
2013-02-27 0:58 ` Rob Landley
2013-02-27 12:39 ` cotulla
2013-02-24 12:23 ` cotulla
2013-02-26 6:55 ` Rob Landley
2013-02-26 19:30 ` cotulla
2013-02-26 19:32 ` cotulla
2013-02-26 19:59 ` Linas Vepstas
2013-02-26 20:25 ` cotulla [this message]
2013-02-26 20:57 ` Linas Vepstas
2013-02-27 1:06 ` Rob Landley
2013-02-27 1:30 ` Linas Vepstas
2013-02-27 3:03 ` Rob Landley
2013-02-27 12:35 ` cotulla
-- strict thread matches above, loose matches on Subject: below --
2013-02-24 0:24 Linas Vepstas
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