From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
To: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Mike Turquette
<mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Hiroshi Doyu <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v3 00/19] Introduce common infra for tegra clocks
Date: Tue, 15 Oct 2013 11:48:57 -0600 [thread overview]
Message-ID: <525D8009.5040907@wwwdotorg.org> (raw)
In-Reply-To: <1381848794-11761-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 10/15/2013 08:52 AM, Peter De Schrijver wrote:
> This patchset introduces common infrastructure for clocks which exist in
> several Tegra SoCs. We also also move Tegra20, Tegra30 and Tegra114 to
> this new infrastructure.
I took my local branch based on next-20131014, and applied the following:
* Joseph's "ARM: tegra: add clock properties for devices of Tegra124".
* The patches from your "pull request for tegra clocks" of today (I just
cherry-picked the commits rather than merging the pull request).
* Your patch series "Introduce common infra for tegra clocks" of today.
* Your patch series "Tegra124 clock support" of today.
The resultant branch is at:
git://github.com:swarren/linux-tegra.git linux-next_common
When building, I see a number of section mismatches:
> WARNING: drivers/clk/tegra/built-in.o(.text+0x534): Section mismatch in reference from the function _tegra_clk_register_periph() to the function .init.text:get_reg_bank()
> The function _tegra_clk_register_periph() references
> the function __init get_reg_bank().
> This is often because _tegra_clk_register_periph lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
>
> WARNING: drivers/clk/tegra/built-in.o(.text+0x9ec): Section mismatch in reference from the function tegra_clk_register_periph_gate() to the function .init.text:get_reg_bank()
> The function tegra_clk_register_periph_gate() references
> the function __init get_reg_bank().
> This is often because tegra_clk_register_periph_gate lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
There are more, but they refer to references from the same two
functions. You may need to add CONFIG_DEBUG_SECTION_MISMATCH=y to
.config to see these; I can't remember if that's included in
tegra_defconfig.
Testing on Venice2 (Tegra124): I see the following WARN during boot,
which I think is new relative to the internal branch you gave me yesterday:
> [ 0.295386] ------------[ cut here ]------------
> [ 0.300450] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:187 tegra_init_from_table+0x78/0x158()
> [ 0.310362] Modules linked in:
> [ 0.313740] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.323397] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.332753] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.341559] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.351283] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.361768] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c1c>] (tegra_init_from_table+0x78/0x158)
> [ 0.372440] [<c07b4c1c>] (tegra_init_from_table+0x78/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.384138] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.394903] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.404535] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.414551] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.424944] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.434764] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.443850] ---[ end trace 98c2207379d4cf99 ]---
Testing on Cardhu (Tegra30): I see the following new WARNs during boot:
> [ 0.495006] tegra_init_from_table: Failed to set rate 600000000 of disp1
> [ 0.501960] ------------[ cut here ]------------
> [ 0.506792] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.516233] Modules linked in:
> [ 0.519446] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.528653] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.537575] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.545963] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.555231] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.565213] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.575373] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.586514] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.596770] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.605951] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.615486] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.625389] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.634748] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.643406] ---[ end trace 3b692d0aca5bdcbf ]---
> [ 0.648221] tegra_init_from_table: Failed to set rate 600000000 of disp2
> [ 0.655170] ------------[ cut here ]------------
> [ 0.659985] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.669424] Modules linked in:
> [ 0.672641] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.682801] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.691716] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.700089] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.709356] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.719337] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.729496] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.740633] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.750880] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.760058] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.769593] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.779485] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.788843] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.797483] ---[ end trace 3b692d0aca5bdcc0 ]---
Testing on Dalmore (Tegra114) and Harmony (Tegra20) seemed OK.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 00/19] Introduce common infra for tegra clocks
Date: Tue, 15 Oct 2013 11:48:57 -0600 [thread overview]
Message-ID: <525D8009.5040907@wwwdotorg.org> (raw)
In-Reply-To: <1381848794-11761-1-git-send-email-pdeschrijver@nvidia.com>
On 10/15/2013 08:52 AM, Peter De Schrijver wrote:
> This patchset introduces common infrastructure for clocks which exist in
> several Tegra SoCs. We also also move Tegra20, Tegra30 and Tegra114 to
> this new infrastructure.
I took my local branch based on next-20131014, and applied the following:
* Joseph's "ARM: tegra: add clock properties for devices of Tegra124".
* The patches from your "pull request for tegra clocks" of today (I just
cherry-picked the commits rather than merging the pull request).
* Your patch series "Introduce common infra for tegra clocks" of today.
* Your patch series "Tegra124 clock support" of today.
The resultant branch is at:
git://github.com:swarren/linux-tegra.git linux-next_common
When building, I see a number of section mismatches:
> WARNING: drivers/clk/tegra/built-in.o(.text+0x534): Section mismatch in reference from the function _tegra_clk_register_periph() to the function .init.text:get_reg_bank()
> The function _tegra_clk_register_periph() references
> the function __init get_reg_bank().
> This is often because _tegra_clk_register_periph lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
>
> WARNING: drivers/clk/tegra/built-in.o(.text+0x9ec): Section mismatch in reference from the function tegra_clk_register_periph_gate() to the function .init.text:get_reg_bank()
> The function tegra_clk_register_periph_gate() references
> the function __init get_reg_bank().
> This is often because tegra_clk_register_periph_gate lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
There are more, but they refer to references from the same two
functions. You may need to add CONFIG_DEBUG_SECTION_MISMATCH=y to
.config to see these; I can't remember if that's included in
tegra_defconfig.
Testing on Venice2 (Tegra124): I see the following WARN during boot,
which I think is new relative to the internal branch you gave me yesterday:
> [ 0.295386] ------------[ cut here ]------------
> [ 0.300450] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:187 tegra_init_from_table+0x78/0x158()
> [ 0.310362] Modules linked in:
> [ 0.313740] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.323397] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.332753] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.341559] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.351283] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.361768] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c1c>] (tegra_init_from_table+0x78/0x158)
> [ 0.372440] [<c07b4c1c>] (tegra_init_from_table+0x78/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.384138] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.394903] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.404535] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.414551] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.424944] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.434764] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.443850] ---[ end trace 98c2207379d4cf99 ]---
Testing on Cardhu (Tegra30): I see the following new WARNs during boot:
> [ 0.495006] tegra_init_from_table: Failed to set rate 600000000 of disp1
> [ 0.501960] ------------[ cut here ]------------
> [ 0.506792] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.516233] Modules linked in:
> [ 0.519446] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.528653] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.537575] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.545963] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.555231] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.565213] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.575373] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.586514] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.596770] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.605951] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.615486] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.625389] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.634748] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.643406] ---[ end trace 3b692d0aca5bdcbf ]---
> [ 0.648221] tegra_init_from_table: Failed to set rate 600000000 of disp2
> [ 0.655170] ------------[ cut here ]------------
> [ 0.659985] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.669424] Modules linked in:
> [ 0.672641] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.682801] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.691716] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.700089] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.709356] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.719337] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.729496] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.740633] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.750880] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.760058] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.769593] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.779485] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.788843] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.797483] ---[ end trace 3b692d0aca5bdcc0 ]---
Testing on Dalmore (Tegra114) and Harmony (Tegra20) seemed OK.
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Warren <swarren@wwwdotorg.org>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Thierry Reding <thierry.reding@gmail.com>,
Rob Herring <rob.herring@calxeda.com>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Hiroshi Doyu <hdoyu@nvidia.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-tegra@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 00/19] Introduce common infra for tegra clocks
Date: Tue, 15 Oct 2013 11:48:57 -0600 [thread overview]
Message-ID: <525D8009.5040907@wwwdotorg.org> (raw)
In-Reply-To: <1381848794-11761-1-git-send-email-pdeschrijver@nvidia.com>
On 10/15/2013 08:52 AM, Peter De Schrijver wrote:
> This patchset introduces common infrastructure for clocks which exist in
> several Tegra SoCs. We also also move Tegra20, Tegra30 and Tegra114 to
> this new infrastructure.
I took my local branch based on next-20131014, and applied the following:
* Joseph's "ARM: tegra: add clock properties for devices of Tegra124".
* The patches from your "pull request for tegra clocks" of today (I just
cherry-picked the commits rather than merging the pull request).
* Your patch series "Introduce common infra for tegra clocks" of today.
* Your patch series "Tegra124 clock support" of today.
The resultant branch is at:
git://github.com:swarren/linux-tegra.git linux-next_common
When building, I see a number of section mismatches:
> WARNING: drivers/clk/tegra/built-in.o(.text+0x534): Section mismatch in reference from the function _tegra_clk_register_periph() to the function .init.text:get_reg_bank()
> The function _tegra_clk_register_periph() references
> the function __init get_reg_bank().
> This is often because _tegra_clk_register_periph lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
>
> WARNING: drivers/clk/tegra/built-in.o(.text+0x9ec): Section mismatch in reference from the function tegra_clk_register_periph_gate() to the function .init.text:get_reg_bank()
> The function tegra_clk_register_periph_gate() references
> the function __init get_reg_bank().
> This is often because tegra_clk_register_periph_gate lacks a __init
> annotation or the annotation of get_reg_bank is wrong.
There are more, but they refer to references from the same two
functions. You may need to add CONFIG_DEBUG_SECTION_MISMATCH=y to
.config to see these; I can't remember if that's included in
tegra_defconfig.
Testing on Venice2 (Tegra124): I see the following WARN during boot,
which I think is new relative to the internal branch you gave me yesterday:
> [ 0.295386] ------------[ cut here ]------------
> [ 0.300450] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:187 tegra_init_from_table+0x78/0x158()
> [ 0.310362] Modules linked in:
> [ 0.313740] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.323397] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.332753] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.341559] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.351283] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.361768] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c1c>] (tegra_init_from_table+0x78/0x158)
> [ 0.372440] [<c07b4c1c>] (tegra_init_from_table+0x78/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.384138] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.394903] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.404535] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.414551] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.424944] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.434764] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.443850] ---[ end trace 98c2207379d4cf99 ]---
Testing on Cardhu (Tegra30): I see the following new WARNs during boot:
> [ 0.495006] tegra_init_from_table: Failed to set rate 600000000 of disp1
> [ 0.501960] ------------[ cut here ]------------
> [ 0.506792] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.516233] Modules linked in:
> [ 0.519446] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.528653] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.537575] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.545963] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.555231] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.565213] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.575373] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.586514] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.596770] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.605951] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.615486] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.625389] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.634748] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.643406] ---[ end trace 3b692d0aca5bdcbf ]---
> [ 0.648221] tegra_init_from_table: Failed to set rate 600000000 of disp2
> [ 0.655170] ------------[ cut here ]------------
> [ 0.659985] WARNING: CPU: 0 PID: 1 at drivers/clk/tegra/clk.c:196 tegra_init_from_table+0xc0/0x158()
> [ 0.669424] Modules linked in:
> [ 0.672641] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.12.0-rc5-next-20131014-05418-g30b9d55 #48
> [ 0.682801] [<c0016644>] (unwind_backtrace+0x0/0x138) from [<c001225c>] (show_stack+0x10/0x14)
> [ 0.691716] [<c001225c>] (show_stack+0x10/0x14) from [<c0572274>] (dump_stack+0x80/0xc0)
> [ 0.700089] [<c0572274>] (dump_stack+0x80/0xc0) from [<c0025d54>] (warn_slowpath_common+0x64/0x88)
> [ 0.709356] [<c0025d54>] (warn_slowpath_common+0x64/0x88) from [<c0025d94>] (warn_slowpath_null+0x1c/0x24)
> [ 0.719337] [<c0025d94>] (warn_slowpath_null+0x1c/0x24) from [<c07b4c64>] (tegra_init_from_table+0xc0/0x158)
> [ 0.729496] [<c07b4c64>] (tegra_init_from_table+0xc0/0x158) from [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20)
> [ 0.740633] [<c07b4e10>] (tegra_clocks_apply_init_table+0x18/0x20) from [<c079f9cc>] (tegra_dt_init+0xc/0xd8)
> [ 0.750880] [<c079f9cc>] (tegra_dt_init+0xc/0xd8) from [<c079a580>] (customize_machine+0x1c/0x40)
> [ 0.760058] [<c079a580>] (customize_machine+0x1c/0x40) from [<c00089e0>] (do_one_initcall+0xec/0x19c)
> [ 0.769593] [<c00089e0>] (do_one_initcall+0xec/0x19c) from [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8)
> [ 0.779485] [<c0798ba8>] (kernel_init_freeable+0xfc/0x1c8) from [<c056d5a8>] (kernel_init+0x8/0xe4)
> [ 0.788843] [<c056d5a8>] (kernel_init+0x8/0xe4) from [<c000f0f8>] (ret_from_fork+0x14/0x3c)
> [ 0.797483] ---[ end trace 3b692d0aca5bdcc0 ]---
Testing on Dalmore (Tegra114) and Harmony (Tegra20) seemed OK.
next prev parent reply other threads:[~2013-10-15 17:48 UTC|newest]
Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-15 14:52 [PATCH v3 00/19] Introduce common infra for tegra clocks Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 01/19] ARM: tegra30: add missing CLK IDs Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 02/19] clk: tegra: simplify periph clock data Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-3-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 18:46 ` Stephen Warren
2013-10-15 18:46 ` Stephen Warren
2013-10-15 18:46 ` Stephen Warren
[not found] ` <525D8D7D.10301-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 15:06 ` Peter De Schrijver
2013-10-16 15:06 ` Peter De Schrijver
2013-10-16 15:06 ` Peter De Schrijver
2013-10-16 17:06 ` Stephen Warren
2013-10-16 17:06 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 03/19] clk: tegra: common periph_clk_enb_refcnt and clks Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-4-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 18:52 ` Stephen Warren
2013-10-15 18:52 ` Stephen Warren
2013-10-15 18:52 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 05/19] clk: tegra: move some PLLC and PLLXC init to clk-pll.c Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-6-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 18:59 ` Stephen Warren
2013-10-15 18:59 ` Stephen Warren
2013-10-15 18:59 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 06/19] clk: tegra: move fields to tegra_clk_pll_params Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 07/19] clk: tegra: add header for common tegra clock IDs Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 08/19] clk: tegra: add common infra for DT clocks Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-9-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:01 ` Stephen Warren
2013-10-15 19:01 ` Stephen Warren
2013-10-15 19:01 ` Stephen Warren
[not found] ` <525D9117.9050009-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 14:34 ` Peter De Schrijver
2013-10-16 14:34 ` Peter De Schrijver
2013-10-16 14:34 ` Peter De Schrijver
[not found] ` <20131016143448.GK5643-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-10-16 17:02 ` Stephen Warren
2013-10-16 17:02 ` Stephen Warren
2013-10-16 17:02 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 09/19] clk: tegra: add clkdev registration infra Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 19:08 ` Stephen Warren
2013-10-15 19:08 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 10/19] clk: tegra: move audio clk to common file Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-11-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:13 ` Stephen Warren
2013-10-15 19:13 ` Stephen Warren
2013-10-15 19:13 ` Stephen Warren
[not found] ` <525D93E8.1010903-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 7:35 ` Peter De Schrijver
2013-10-16 7:35 ` Peter De Schrijver
2013-10-16 7:35 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 11/19] clk: tegra: move periph clocks " Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-12-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:19 ` Stephen Warren
2013-10-15 19:19 ` Stephen Warren
2013-10-15 19:19 ` Stephen Warren
2013-10-15 14:52 ` [PATCH v3 12/19] clk: tegra: move PMC, fixed clocks to common files Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 13/19] clk: tegra: introduce common gen4 super clock Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-14-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:37 ` Stephen Warren
2013-10-15 19:37 ` Stephen Warren
2013-10-15 19:37 ` Stephen Warren
[not found] ` <525D9973.2070501-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 7:38 ` Peter De Schrijver
2013-10-16 7:38 ` Peter De Schrijver
2013-10-16 7:38 ` Peter De Schrijver
2013-10-15 14:52 ` [PATCH v3 14/19] clk: tegra30: replace enum by binding header Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
[not found] ` <1381848794-11761-15-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:41 ` Stephen Warren
2013-10-15 19:41 ` Stephen Warren
2013-10-15 19:41 ` Stephen Warren
[not found] ` <525D9A85.40102-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 14:46 ` Peter De Schrijver
2013-10-16 14:46 ` Peter De Schrijver
2013-10-16 14:46 ` Peter De Schrijver
[not found] ` <20131016144618.GL5643-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-10-16 17:02 ` Stephen Warren
2013-10-16 17:02 ` Stephen Warren
2013-10-16 17:02 ` Stephen Warren
2013-10-15 14:53 ` [PATCH v3 16/19] clk: tegra20: move tegra20 to common clkdev Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` [PATCH v3 17/19] clk: tegra30: move tegra30 " Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` [PATCH v3 18/19] clk: tegra20: move to common periph clk Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` [PATCH v3 19/19] clk: tegra30: move to common tegra clk infra Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
[not found] ` <1381848794-11761-20-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 19:43 ` Stephen Warren
2013-10-15 19:43 ` Stephen Warren
2013-10-15 19:43 ` Stephen Warren
[not found] ` <1381848794-11761-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2013-10-15 14:52 ` [PATCH v3 04/19] clk: tegra: Add TEGRA_PERIPH_NO_DIV flag Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:52 ` Peter De Schrijver
2013-10-15 14:53 ` [PATCH v3 15/19] clk: tegra20: replace enum by binding header Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 14:53 ` Peter De Schrijver
2013-10-15 17:48 ` Stephen Warren [this message]
2013-10-15 17:48 ` [PATCH v3 00/19] Introduce common infra for tegra clocks Stephen Warren
2013-10-15 17:48 ` Stephen Warren
[not found] ` <525D8009.5040907-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2013-10-16 9:06 ` Peter De Schrijver
2013-10-16 9:06 ` Peter De Schrijver
2013-10-16 9:06 ` Peter De Schrijver
[not found] ` <20131016090643.GI5643-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2013-10-16 17:14 ` Stephen Warren
2013-10-16 17:14 ` Stephen Warren
2013-10-16 17:14 ` Stephen Warren
2013-10-17 7:52 ` Peter De Schrijver
2013-10-17 7:52 ` Peter De Schrijver
2013-10-15 19:43 ` Stephen Warren
2013-10-15 19:43 ` Stephen Warren
2013-10-15 19:43 ` Stephen Warren
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