* [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
@ 2013-10-18 20:41 Alex Deucher
2013-10-18 20:41 ` [PATCH 2/2] drm/radeon/audio: write audio/video latency info for DCE6/8 Alex Deucher
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Alex Deucher @ 2013-10-18 20:41 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Needed by the hda driver to properly set up synchronization
on the audio side.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 5fbe486..abdc893 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
}
+static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
+ struct drm_display_mode *mode)
+{
+ struct radeon_device *rdev = encoder->dev->dev_private;
+ struct drm_connector *connector;
+ struct radeon_connector *radeon_connector = NULL;
+ u32 tmp = 0;
+
+ list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
+ if (connector->encoder == encoder) {
+ radeon_connector = to_radeon_connector(connector);
+ break;
+ }
+ }
+
+ if (!radeon_connector) {
+ DRM_ERROR("Couldn't find encoder's connector\n");
+ return;
+ }
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (connector->latency_present[1])
+ tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
+ AUDIO_LIPSYNC(connector->audio_latency[1]);
+ else
+ tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+ } else {
+ if (connector->latency_present[0])
+ tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
+ AUDIO_LIPSYNC(connector->audio_latency[0]);
+ else
+ tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+ }
+ WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
+}
+
static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
{
struct radeon_device *rdev = encoder->dev->dev_private;
@@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
dce6_afmt_write_sad_regs(encoder);
} else {
evergreen_hdmi_write_sad_regs(encoder);
+ dce4_afmt_write_latency_fields(encoder, mode);
}
err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index fa81893..11e002a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -750,6 +750,44 @@
* bit6 = 192 kHz
*/
+#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
+# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
+# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
+/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
+ * 0 = use stream header
+ * 1-7 = channel count - 1
+ */
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
+# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
+# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
+/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
+ * 0 = invalid
+ * x = legal delay value
+ * 255 = sync not supported
+ */
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
+# define HBR_CAPABLE (1 << 0) /* enabled by default */
+
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
+# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
+# define DISPLAY_TYPE_NONE 0
+# define DISPLAY_TYPE_HDMI 1
+# define DISPLAY_TYPE_DP 2
+# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
+# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
+# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
+# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
+# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
+# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
+# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
+# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
+# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
+# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
+# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
+# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
+
#define AZ_HOT_PLUG_CONTROL 0x5e78
# define AZ_FORCE_CODEC_WAKE (1 << 0)
# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/radeon/audio: write audio/video latency info for DCE6/8
2013-10-18 20:41 [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Alex Deucher
@ 2013-10-18 20:41 ` Alex Deucher
2013-10-19 0:03 ` [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Anssi Hannula
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2013-10-18 20:41 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Needed by the hda driver to properly set up synchronization
on the audio side.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/radeon/dce6_afmt.c | 43 +++++++++++++++++++++++++++++++
drivers/gpu/drm/radeon/evergreen_hdmi.c | 3 +++
drivers/gpu/drm/radeon/sid.h | 45 +++++++++++++++++++++++++++++++++
3 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
index 85a69d2..5929056 100644
--- a/drivers/gpu/drm/radeon/dce6_afmt.c
+++ b/drivers/gpu/drm/radeon/dce6_afmt.c
@@ -102,6 +102,49 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder)
AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
}
+void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
+ struct drm_display_mode *mode)
+{
+ struct radeon_device *rdev = encoder->dev->dev_private;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+ struct drm_connector *connector;
+ struct radeon_connector *radeon_connector = NULL;
+ u32 tmp = 0, offset;
+
+ if (!dig->afmt->pin)
+ return;
+
+ offset = dig->afmt->pin->offset;
+
+ list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
+ if (connector->encoder == encoder) {
+ radeon_connector = to_radeon_connector(connector);
+ break;
+ }
+ }
+
+ if (!radeon_connector) {
+ DRM_ERROR("Couldn't find encoder's connector\n");
+ return;
+ }
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (connector->latency_present[1])
+ tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
+ AUDIO_LIPSYNC(connector->audio_latency[1]);
+ else
+ tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+ } else {
+ if (connector->latency_present[0])
+ tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
+ AUDIO_LIPSYNC(connector->audio_latency[0]);
+ else
+ tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+ }
+ WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
+}
+
void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
{
struct radeon_device *rdev = encoder->dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index abdc893..6787365 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -35,6 +35,8 @@
extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
+extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
+ struct drm_display_mode *mode);
/*
* update the N and CTS parameters for a given pixel clock rate
@@ -361,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
if (ASIC_IS_DCE6(rdev)) {
dce6_afmt_select_pin(encoder);
dce6_afmt_write_sad_regs(encoder);
+ dce6_afmt_write_latency_fields(encoder, mode);
} else {
evergreen_hdmi_write_sad_regs(encoder);
dce4_afmt_write_latency_fields(encoder, mode);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 52d2ab6..307ffdf 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -683,6 +683,51 @@
* bit5 = 176.4 kHz
* bit6 = 192 kHz
*/
+
+#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
+# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
+# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
+/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
+ * 0 = invalid
+ * x = legal delay value
+ * 255 = sync not supported
+ */
+#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
+# define HBR_CAPABLE (1 << 0) /* enabled by default */
+
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
+# define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
+# define PRODUCT_ID(x) (((x) & 0xffff) << 16)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
+# define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
+# define PORT_ID0(x) (((x) & 0xffffffff) << 0)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
+# define PORT_ID1(x) (((x) & 0xffffffff) << 0)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
+# define DESCRIPTION0(x) (((x) & 0xff) << 0)
+# define DESCRIPTION1(x) (((x) & 0xff) << 8)
+# define DESCRIPTION2(x) (((x) & 0xff) << 16)
+# define DESCRIPTION3(x) (((x) & 0xff) << 24)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
+# define DESCRIPTION4(x) (((x) & 0xff) << 0)
+# define DESCRIPTION5(x) (((x) & 0xff) << 8)
+# define DESCRIPTION6(x) (((x) & 0xff) << 16)
+# define DESCRIPTION7(x) (((x) & 0xff) << 24)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
+# define DESCRIPTION8(x) (((x) & 0xff) << 0)
+# define DESCRIPTION9(x) (((x) & 0xff) << 8)
+# define DESCRIPTION10(x) (((x) & 0xff) << 16)
+# define DESCRIPTION11(x) (((x) & 0xff) << 24)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
+# define DESCRIPTION12(x) (((x) & 0xff) << 0)
+# define DESCRIPTION13(x) (((x) & 0xff) << 8)
+# define DESCRIPTION14(x) (((x) & 0xff) << 16)
+# define DESCRIPTION15(x) (((x) & 0xff) << 24)
+#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
+# define DESCRIPTION16(x) (((x) & 0xff) << 0)
+# define DESCRIPTION17(x) (((x) & 0xff) << 8)
+
#define AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL 0x54
# define AUDIO_ENABLED (1 << 31)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
2013-10-18 20:41 [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Alex Deucher
2013-10-18 20:41 ` [PATCH 2/2] drm/radeon/audio: write audio/video latency info for DCE6/8 Alex Deucher
@ 2013-10-19 0:03 ` Anssi Hannula
2013-10-19 8:52 ` Christian König
2013-11-08 11:24 ` Anssi Hannula
3 siblings, 0 replies; 7+ messages in thread
From: Anssi Hannula @ 2013-10-19 0:03 UTC (permalink / raw)
To: Alex Deucher; +Cc: dri-devel
18.10.2013 23:41, Alex Deucher kirjoitti:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
For the record, the ALSA hda driver does not actually do anything with
these values yet (and my work-in-progress doesn't change that), except
show them in ELD information.
This might change in the future of course :)
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
> WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
> }
>
> +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
> + struct drm_display_mode *mode)
> +{
> + struct radeon_device *rdev = encoder->dev->dev_private;
> + struct drm_connector *connector;
> + struct radeon_connector *radeon_connector = NULL;
> + u32 tmp = 0;
> +
> + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
> + if (connector->encoder == encoder) {
> + radeon_connector = to_radeon_connector(connector);
> + break;
> + }
> + }
> +
> + if (!radeon_connector) {
> + DRM_ERROR("Couldn't find encoder's connector\n");
> + return;
> + }
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (connector->latency_present[1])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
> + AUDIO_LIPSYNC(connector->audio_latency[1]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + } else {
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> +}
> +
> static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
> {
> struct radeon_device *rdev = encoder->dev->dev_private;
> @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
> dce6_afmt_write_sad_regs(encoder);
> } else {
> evergreen_hdmi_write_sad_regs(encoder);
> + dce4_afmt_write_latency_fields(encoder, mode);
> }
>
> err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
> index fa81893..11e002a 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -750,6 +750,44 @@
> * bit6 = 192 kHz
> */
>
> +#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
> +# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
> +# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
> +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
> + * 0 = use stream header
> + * 1-7 = channel count - 1
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
> +# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0 = invalid
> + * x = legal delay value
> + * 255 = sync not supported
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
> +# define HBR_CAPABLE (1 << 0) /* enabled by default */
> +
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
> +# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
> +# define DISPLAY_TYPE_NONE 0
> +# define DISPLAY_TYPE_HDMI 1
> +# define DISPLAY_TYPE_DP 2
> +# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
> +# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
> +# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
> +# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
> +# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
> +# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
> +# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
> +# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
> +# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
> +# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
> +# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
> +# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
> +
> #define AZ_HOT_PLUG_CONTROL 0x5e78
> # define AZ_FORCE_CODEC_WAKE (1 << 0)
> # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
>
--
Anssi Hannula
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
2013-10-18 20:41 [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Alex Deucher
2013-10-18 20:41 ` [PATCH 2/2] drm/radeon/audio: write audio/video latency info for DCE6/8 Alex Deucher
2013-10-19 0:03 ` [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Anssi Hannula
@ 2013-10-19 8:52 ` Christian König
2013-11-08 11:24 ` Anssi Hannula
3 siblings, 0 replies; 7+ messages in thread
From: Christian König @ 2013-10-19 8:52 UTC (permalink / raw)
To: Alex Deucher, dri-devel; +Cc: Alex Deucher
Am 18.10.2013 22:41, schrieb Alex Deucher:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For both: Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
> WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
> }
>
> +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
> + struct drm_display_mode *mode)
> +{
> + struct radeon_device *rdev = encoder->dev->dev_private;
> + struct drm_connector *connector;
> + struct radeon_connector *radeon_connector = NULL;
> + u32 tmp = 0;
> +
> + list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
> + if (connector->encoder == encoder) {
> + radeon_connector = to_radeon_connector(connector);
> + break;
> + }
> + }
> +
> + if (!radeon_connector) {
> + DRM_ERROR("Couldn't find encoder's connector\n");
> + return;
> + }
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (connector->latency_present[1])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
> + AUDIO_LIPSYNC(connector->audio_latency[1]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + } else {
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> +}
> +
> static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
> {
> struct radeon_device *rdev = encoder->dev->dev_private;
> @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
> dce6_afmt_write_sad_regs(encoder);
> } else {
> evergreen_hdmi_write_sad_regs(encoder);
> + dce4_afmt_write_latency_fields(encoder, mode);
> }
>
> err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
> index fa81893..11e002a 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -750,6 +750,44 @@
> * bit6 = 192 kHz
> */
>
> +#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
> +# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
> +# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
> +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
> + * 0 = use stream header
> + * 1-7 = channel count - 1
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
> +# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0 = invalid
> + * x = legal delay value
> + * 255 = sync not supported
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
> +# define HBR_CAPABLE (1 << 0) /* enabled by default */
> +
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
> +# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
> +# define DISPLAY_TYPE_NONE 0
> +# define DISPLAY_TYPE_HDMI 1
> +# define DISPLAY_TYPE_DP 2
> +# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
> +# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
> +# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
> +# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
> +# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
> +# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
> +# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
> +# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
> +# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
> +# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
> +# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
> +# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
> +
> #define AZ_HOT_PLUG_CONTROL 0x5e78
> # define AZ_FORCE_CODEC_WAKE (1 << 0)
> # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
2013-10-18 20:41 [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Alex Deucher
` (2 preceding siblings ...)
2013-10-19 8:52 ` Christian König
@ 2013-11-08 11:24 ` Anssi Hannula
2013-11-11 15:55 ` Alex Deucher
3 siblings, 1 reply; 7+ messages in thread
From: Anssi Hannula @ 2013-11-08 11:24 UTC (permalink / raw)
To: Alex Deucher, dri-devel; +Cc: Alex Deucher
18.10.2013 23:41, Alex Deucher kirjoitti:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
[...]
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
[...]
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
> +# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0 = invalid
> + * x = legal delay value
> + * 255 = sync not supported
> + */
Hmm, AMD_HDA_verbs_v2.pdf says that:
0 = unknown latency
HDMI spec 1.4 says that:
0 = not valid or unknown latency
1..251 = valid delay value
255 = video not supported / audio not supported
Are you sure you shouldn't use 0 instead for unknown (no latency_present)?
Not sure this matters much, though, since the only consumer here is ALSA
which we can write however we wish (and it is missing handling for 255
since it was missing from AMD_HDA_verbs_v2.pdf, but I'll add it in any
case since it is mentioned in HDMI specs).
[...]
--
Anssi Hannula
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
2013-11-08 11:24 ` Anssi Hannula
@ 2013-11-11 15:55 ` Alex Deucher
2013-11-11 22:10 ` Anssi Hannula
0 siblings, 1 reply; 7+ messages in thread
From: Alex Deucher @ 2013-11-11 15:55 UTC (permalink / raw)
To: Anssi Hannula; +Cc: Alex Deucher, Maling list - DRI developers
On Fri, Nov 8, 2013 at 6:24 AM, Anssi Hannula <anssi.hannula@iki.fi> wrote:
> 18.10.2013 23:41, Alex Deucher kirjoitti:
>> Needed by the hda driver to properly set up synchronization
>> on the audio side.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>> drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
>> 2 files changed, 75 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> index 5fbe486..abdc893 100644
>> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> [...]
>> + if (connector->latency_present[0])
>> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
>> + AUDIO_LIPSYNC(connector->audio_latency[0]);
>> + else
>> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
>> + }
>> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> [...]
>> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
>> +# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
>> +# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
>> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
>> + * 0 = invalid
>> + * x = legal delay value
>> + * 255 = sync not supported
>> + */
>
> Hmm, AMD_HDA_verbs_v2.pdf says that:
> 0 = unknown latency
>
> HDMI spec 1.4 says that:
> 0 = not valid or unknown latency
> 1..251 = valid delay value
> 255 = video not supported / audio not supported
>
> Are you sure you shouldn't use 0 instead for unknown (no latency_present)?
I'm not sure. The comment in the code above is what the register spec
says which seems to match the HDMI spec. I can dig around a bit more
internally.
Alex
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5
2013-11-11 15:55 ` Alex Deucher
@ 2013-11-11 22:10 ` Anssi Hannula
0 siblings, 0 replies; 7+ messages in thread
From: Anssi Hannula @ 2013-11-11 22:10 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, Maling list - DRI developers
11.11.2013 17:55, Alex Deucher kirjoitti:
> On Fri, Nov 8, 2013 at 6:24 AM, Anssi Hannula <anssi.hannula@iki.fi> wrote:
>> 18.10.2013 23:41, Alex Deucher kirjoitti:
>>> Needed by the hda driver to properly set up synchronization
>>> on the audio side.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>> drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
>>> drivers/gpu/drm/radeon/evergreend.h | 38 +++++++++++++++++++++++++++++++++
>>> 2 files changed, 75 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> index 5fbe486..abdc893 100644
>>> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> [...]
>>> + if (connector->latency_present[0])
>>> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
>>> + AUDIO_LIPSYNC(connector->audio_latency[0]);
>>> + else
>>> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
>>> + }
>>> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
>> [...]
>>> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
>>> +# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
>>> +# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
>>> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
>>> + * 0 = invalid
>>> + * x = legal delay value
>>> + * 255 = sync not supported
>>> + */
>>
>> Hmm, AMD_HDA_verbs_v2.pdf says that:
>> 0 = unknown latency
>>
>> HDMI spec 1.4 says that:
>> 0 = not valid or unknown latency
>> 1..251 = valid delay value
>> 255 = video not supported / audio not supported
>>
>> Are you sure you shouldn't use 0 instead for unknown (no latency_present)?
>
> I'm not sure. The comment in the code above is what the register spec
> says which seems to match the HDMI spec. I can dig around a bit more
> internally.
OK, though don't waste too much time on that, ALSA has to handle 0 and
255 the same in any case (a patch has just been pushed to sound git to
handle 255). :)
--
Anssi Hannula
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-11-11 22:10 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-10-18 20:41 [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Alex Deucher
2013-10-18 20:41 ` [PATCH 2/2] drm/radeon/audio: write audio/video latency info for DCE6/8 Alex Deucher
2013-10-19 0:03 ` [PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5 Anssi Hannula
2013-10-19 8:52 ` Christian König
2013-11-08 11:24 ` Anssi Hannula
2013-11-11 15:55 ` Alex Deucher
2013-11-11 22:10 ` Anssi Hannula
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