Re: [Qemu-devel] [PATCH 09/13] target-openrisc: Add CPU which neglects Carry and Overflow Flag

[Richard Henderson <rth@twiddle.net>]

On 10/29/2013 12:04 PM, Sebastian Macke wrote:
> The carry and overflag and the instructions l.addc and l.addic
> are never used in the toolchain. Linux and gcc compiled software
> don't need them.

Really?  That's quite surprising.

> To speed up the emulation a cpu was added which
> neglects the flags for l.addi, l.add, l.sub and
> generates an illegal instruction error for l.addic and l.addc

I'm somewhat shocked that l.addc is never used.  To me that points
to a missed opportunity in the compiler.

It would be much better to simply improve handling of these bits.
In a previous patch set you broke out SR[F] to its own variable;
I suggest that you do the same for SR[CY] and SR[OV].

If you can implement add et al without branches, the TCG optimizer
will be able to do a good job eliminating shadowed computation.

A good example to follow here is the ARM implementation.  Have a
look at the gen_add_CC and gen_sub_CC functions especially.  Note
that the overflow bit is stored in bit 31 of cpu_VF and the other
bits of cpu_VF are ignored.


r~