From: Richard Henderson <rth@twiddle.net>
To: Claudio Fontana <claudio.fontana@linaro.org>,
Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Michael Matz <matz@suse.de>,
Alex Bennee <alex.bennee@linaro.org>,
Alexander Graf <agraf@suse.de>,
patches@linaro.org
Subject: Re: [Qemu-devel] [RFC] target-arm: provide skeleton for a64 insn decoding
Date: Tue, 12 Nov 2013 05:25:11 +1000 [thread overview]
Message-ID: <52812F17.4010400@twiddle.net> (raw)
In-Reply-To: <1384182837-5925-1-git-send-email-claudio.fontana@linaro.org>
On 11/12/2013 01:13 AM, Claudio Fontana wrote:
> +/* C3.2 Branches, exception generating and system instructions */
> +static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
> +{
> + switch (extract32(insn, 25, 7)) {
> + case 0x0a: case 0x4a: /* Unconditional branch (immediate) */
> + disas_uncond_b_imm(s, insn);
> + break;
Bit 25 is "-" for unconditional branch, so this entry should be
0x0a, 0x0b, 0x4a, 0x4b
All of the other decodings look good.
r~
next prev parent reply other threads:[~2013-11-11 19:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-11 15:13 [Qemu-devel] [RFC] target-arm: provide skeleton for a64 insn decoding Claudio Fontana
2013-11-11 19:25 ` Richard Henderson [this message]
2013-11-12 10:59 ` Alex Bennée
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