[U-Boot] [PATCH V2 00/14] ARM: AM43xx: Update support for AM4372 SoC

[U-Boot] [PATCH V2 00/14] ARM: AM43xx: Update support for AM4372 SoC

[Lokesh Vutla]

This Patch series updates support for AM4372 EPOS and GP EVM boards.
AM4372 is a low cost Cortex-A9 based application processor targeted at existing
ARM9/ARM11 base of customers that need more processing capabilities.
Currently there are two boards with AM4372 SoC: EPOS and GP EVM.
Except for few differences like oscillator clock and SDRAM both EPOS and GP EVM
boards are similar.
EPOS EVM:
	OSC clk	: 25MHz
	DDR	: LPDDR2 @ 266MHz (MT42L256M32D2LG-25 WT:A)
GP EVM:
	OSC clk	: 24MHz
	DDR	: DDR3 @ 400MHz(MT41K512M8RH)

This patch series is applied on top of Mainline U-Boot Tree and two
patches mentioned below:
git://git.denx.de/u-boot.git master
   http://patchwork.ozlabs.org/patch/288175/

Testing:
-> Boot tested on AM4372 EPOS and GP EVMs, Beaglebone Black.
-> verified MAKEALL -s am33xx.
-> Ran checkpatch on all patches.

Changes Since V1:
As per Vaibhav's and Tom's Comments:
-> Updated the mux data not to use DSPULLUDEN.
-> Reused the emif4d file for configuring emif4d5 registers.
-> Updated the code with comments.
-> Rebased on top of Current U-Boot mainline.

Lokesh Vutla (12):
  ARM: AM43xx: Update the base addresses of modules
  ARM: AM43xx: Adapt to ti_armv7_common.h config file
  ARM: AM43xx: Add L2 Support
  ARM: AM43xx: Add extra ENV settings
  ARM: AM43xx: Select clk source for Timer2
  ARM: AM43xx: Update Current Booting devices list
  ARM: AM43xx: mux: Update mux data
  ARM: AM43xx: clocks: Update DPLL details for EPOS EVM
  ARM: AM43xx: clocks: Add DPLL data for GP EVM
  ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
  ARM: AM43xx: GP_EVM: Add support for DDR3
  ARM: AM43xx: Add Maintainer

Sekhar Nori (2):
  ARM: AM43XX: board: add support for reading onboard EEPROM
  ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

 arch/arm/cpu/armv7/am33xx/clock.c                  |   12 +-
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c           |   15 ++
 arch/arm/cpu/armv7/am33xx/clock_am43xx.c           |   12 +-
 arch/arm/cpu/armv7/am33xx/ddr.c                    |  149 ++++++++++-
 arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +-
 arch/arm/cpu/armv7/omap-common/emif-common.c       |   14 -
 arch/arm/include/asm/arch-am33xx/clock.h           |    7 +-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
 arch/arm/include/asm/arch-am33xx/cpu.h             |   22 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   41 ++-
 arch/arm/include/asm/arch-am33xx/hardware.h        |    7 -
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    2 +
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    3 +
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    2 +
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |    2 +
 arch/arm/include/asm/arch-am33xx/mux_am43xx.h      |   45 ++++
 arch/arm/include/asm/arch-am33xx/omap.h            |    2 +
 arch/arm/include/asm/arch-am33xx/spl.h             |   12 +-
 arch/arm/include/asm/emif.h                        |   26 ++
 board/isee/igep0033/board.c                        |   10 +-
 board/phytec/pcm051/board.c                        |   12 +-
 board/siemens/dxr2/board.c                         |   10 +-
 board/siemens/pxm2/board.c                         |   10 +-
 board/siemens/rut/board.c                          |   10 +-
 board/ti/am335x/board.c                            |   40 ++-
 board/ti/am43xx/board.c                            |  271 +++++++++++++++++++-
 board/ti/am43xx/board.h                            |   33 +++
 board/ti/am43xx/mux.c                              |   35 ++-
 board/ti/ti814x/evm.c                              |    4 +-
 board/ti/ti816x/evm.c                              |   12 +-
 boards.cfg                                         |    2 +-
 include/configs/am43xx_evm.h                       |  204 +++++++--------
 32 files changed, 874 insertions(+), 180 deletions(-)

-- 
1.7.9.5

[U-Boot] [PATCH V2 01/14] ARM: AM43xx: Update the base addresses of modules

[Lokesh Vutla]

PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/cpu.h             |   17 +++++++++++------
 arch/arm/include/asm/arch-am33xx/hardware.h        |    7 -------
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |    2 ++
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    2 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h |    2 ++
 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h |    2 ++
 6 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 05752ce..19b8469 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -237,6 +237,14 @@ struct cm_perpll {
 	unsigned int cpswclkstctrl;	/* offset 0x144 */
 	unsigned int lcdcclkstctrl;	/* offset 0x148 */
 };
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+	unsigned int resv1[2];
+	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int resv2[10];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+};
 #else
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
@@ -392,15 +400,12 @@ struct cm_perpll {
 	unsigned int resv40[7];
 	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
 };
-#endif /* CONFIG_AM43XX */
 
-/* Encapsulating Display pll registers */
 struct cm_dpll {
-	unsigned int resv1[2];
-	unsigned int clktimer2clk;	/* offset 0x08 */
-	unsigned int resv2[10];
-	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+	unsigned int resv1;
+	unsigned int clktimer2clk;	/* offset 0x04 */
 };
+#endif /* CONFIG_AM43XX */
 
 /* Control Module RTC registers */
 struct cm_rtc {
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index ee5fce0..dd950e5 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -48,13 +48,6 @@
 #define EMIF4_0_CFG_BASE		0x4C000000
 #define EMIF4_1_CFG_BASE		0x4D000000
 
-/* PLL related registers */
-#define CM_DPLL				0x44E00500
-#define CM_DEVICE			0x44E00700
-#define CM_RTC				0x44E00800
-#define CM_CEFUSE			0x44E00A00
-#define PRM_DEVICE			0x44E00F00
-
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index e4231c8..c67a080 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -30,6 +30,8 @@
 #define PRCM_BASE			0x44E00000
 #define CM_PER				0x44E00000
 #define CM_WKUP				0x44E00400
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
 
 #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
 #define PRM_RSTST			(PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 3b665e6..64f9c99 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -30,6 +30,8 @@
 #define PRCM_BASE			0x44DF0000
 #define	CM_WKUP				0x44DF2800
 #define	CM_PER				0x44DF8800
+#define CM_DPLL				0x44DF4200
+#define CM_RTC				0x44df8500
 
 #define PRM_RSTCTRL			(PRCM_BASE + 0x4000)
 #define PRM_RSTST			(PRM_RSTCTRL + 4)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index 4509a23..9080b6f 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -27,6 +27,8 @@
 #define PRCM_BASE			0x48180000
 #define CM_PER				0x44E00000
 #define CM_WKUP				0x44E00400
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
 
 #define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
 #define PRM_RSTST			(PRM_RSTCTRL + 8)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
index 3c68064..0f6a016 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -34,6 +34,8 @@
 
 /* PRCM Base Address */
 #define PRCM_BASE		0x48180000
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
 
 #define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
 #define PRM_RSTST		(PRM_RSTCTRL + 8)
-- 
1.7.9.5

[U-Boot] [PATCH V2 01/14] ARM: AM43xx: Update the base addresses of modules

[Vaibhav Bedia]

Hi Lokesh,

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]
> +#define CM_DPLL                                0x44DF4200
> +#define CM_RTC                         0x44df8500
>

nit: CM_RTC address should be in caps for the sake of consistency

>  #define PRM_RSTCTRL                    (PRCM_BASE + 0x4000)
>  #define PRM_RSTST                      (PRM_RSTCTRL + 4)
> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> index 4509a23..9080b6f 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
> @@ -27,6 +27,8 @@
>  #define PRCM_BASE                      0x48180000
>  #define CM_PER                         0x44E00000
>  #define CM_WKUP                                0x44E00400
> +#define CM_DPLL                                0x44E00500
> +#define CM_RTC                         0x44E00800
>

Looking at these address i strongly suspect the CM_XXX ones are wrong
for the TI81xx
family. Does this really match with the TRM?

Regards,
Vaibhav

[U-Boot] [PATCH V2 01/14] ARM: AM43xx: Update the base addresses of modules

[Lokesh Vutla]

On Friday 22 November 2013 01:50 AM, Vaibhav Bedia wrote:
> Hi Lokesh,
> 
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
>> +#define CM_DPLL                                0x44DF4200
>> +#define CM_RTC                         0x44df8500
>>
> 
> nit: CM_RTC address should be in caps for the sake of consistency
OK ll change it.
> 
>>  #define PRM_RSTCTRL                    (PRCM_BASE + 0x4000)
>>  #define PRM_RSTST                      (PRM_RSTCTRL + 4)
>> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
>> index 4509a23..9080b6f 100644
>> --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
>> +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
>> @@ -27,6 +27,8 @@
>>  #define PRCM_BASE                      0x48180000
>>  #define CM_PER                         0x44E00000
>>  #define CM_WKUP                                0x44E00400
>> +#define CM_DPLL                                0x44E00500
>> +#define CM_RTC                         0x44E00800
>>
> 
> Looking at these address i strongly suspect the CM_XXX ones are wrong
> for the TI81xx
> family. Does this really match with the TRM?
Yes, you are correct. TI814x code doesn't use these defines at all.
Ill drop these.

Thanks
Lokesh
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 02/14] ARM: AM43xx: Adapt to ti_armv7_common.h config file

[Lokesh Vutla]

Use ti_armv7_common.h config file to inclde the common
configs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 board/ti/am43xx/board.c      |    2 +-
 include/configs/am43xx_evm.h |  129 +++++++++---------------------------------
 2 files changed, 28 insertions(+), 103 deletions(-)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 51b2576..dcd8cbb 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -44,7 +44,7 @@ void sdram_init(void)
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
 }
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index d9b6c16..4815357 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -10,127 +10,52 @@
 #define __CONFIG_AM43XX_EVM_H
 
 #define CONFIG_AM43XX
-#define CONFIG_OMAP
-#define CONFIG_OMAP_COMMON
 
-#include <asm/arch/omap.h>
-
-#define CONFIG_DMA_COHERENT
-#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
-
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"U-Boot# "
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_VERSION_VARIABLE
-
-/* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
-/* Clock Defines */
-#define V_OSCK				24000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK)
-
-#define CONFIG_CMD_ECHO
-
-/* max number of command args */
-#define CONFIG_SYS_MAXARGS		64
-
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE		512
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
-					+ sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
- /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
-#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE       32
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
-						GENERATED_GBL_DATA_SIZE)
-/* Platform/Board specific defs */
-#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
-
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+#include <asm/arch/omap.h>
 
 /* NS16550 Configuration */
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		(48000000)
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_CLK		48000000
 
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
-4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
-
-/* CPU */
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_ENV_OVERWRITE		1
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-
-#define CONFIG_ENV_IS_NOWHERE
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE		0x40300350
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_YMODEM_SUPPORT
 
 /*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80100000 should not be used for any
- * other needs.
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
  */
-#define CONFIG_SYS_TEXT_BASE		0x80800000
-
-#ifndef	CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE		0x402F0400
-#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
-#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
 
-#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
 
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_YMODEM_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SYS_SPL_MALLOC_START	0x80a08000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
 
-/* Unsupported features */
-#undef CONFIG_USE_IRQ
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_CMD_USB
 #define CONFIG_USB_HOST
-- 
1.7.9.5

[U-Boot] [PATCH V2 03/14] ARM: AM43xx: Add L2 Support

[Lokesh Vutla]

AM4372 uses PL310 L2 Cache. Enable the configs for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 include/configs/am43xx_evm.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 4815357..b0269a7 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -30,6 +30,11 @@
 #define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_YMODEM_SUPPORT
 
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Since SPL did pll and ddr initialization for us,
  * we don't need to do it twice.
-- 
1.7.9.5

[U-Boot] [PATCH V2 04/14] ARM: AM43xx: Add extra ENV settings

[Lokesh Vutla]

Add Extra env settings.
This is derived from am335x Extra ENV settings.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 include/configs/am43xx_evm.h |   63 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index b0269a7..6693321 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -72,4 +72,67 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_AM437X_USB2PHY2_HOST
 
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from mmc${mmcdev} ...; " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;"
+
+#endif
 #endif	/* __CONFIG_AM43XX_EVM_H */
-- 
1.7.9.5

[U-Boot] [PATCH V2 05/14] ARM: AM43XX: board: add support for reading onboard EEPROM

[Lokesh Vutla]

From: Sekhar Nori <nsekhar@ti.com>

Add support for reading onboard EEPROM to enable
board detection.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/omap.h |    2 ++
 board/ti/am43xx/board.c                 |   46 +++++++++++++++++++++++++++++++
 board/ti/am43xx/board.h                 |   32 +++++++++++++++++++++
 include/configs/am43xx_evm.h            |    7 +++++
 4 files changed, 87 insertions(+)

diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 2250721..10f05c9 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -27,5 +27,7 @@
 #define NON_SECURE_SRAM_START	0x402F0400
 #define NON_SECURE_SRAM_END	0x40340000
 #define SRAM_SCRATCH_SPACE_ADDR	0x4033C000
+#define AM4372_BOARD_NAME_START	SRAM_SCRATCH_SPACE_ADDR
+#define AM4372_BOARD_NAME_END	SRAM_SCRATCH_SPACE_ADDR + 0xC
 #endif
 #endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index dcd8cbb..4fc1a40 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -9,6 +9,8 @@
  */
 
 #include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
 #include <spl.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
@@ -17,6 +19,50 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		printf("Could not probe the EEPROM at 0x%x\n",
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+		     sizeof(struct am43xx_board_id))) {
+		printf("Could not read the EEPROM\n");
+		return -EIO;
+	}
+
+	if (header->magic != 0xEE3355AA) {
+		/*
+		 * read the eeprom using i2c again,
+		 * but use only a 1 byte address
+		 */
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+			     sizeof(struct am43xx_board_id))) {
+			printf("Could not read the EEPROM at 0x%x\n",
+			       CONFIG_SYS_I2C_EEPROM_ADDR);
+			return -EIO;
+		}
+
+		if (header->magic != 0xEE3355AA) {
+			printf("Incorrect magic number (0x%x) in EEPROM\n",
+			       header->magic);
+			return -EINVAL;
+		}
+	}
+
+	strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
+	am43xx_board_name[sizeof(header->name)] = 0;
+
+	return 0;
+}
+
 #ifdef CONFIG_SPL_BUILD
 
 const struct dpll_params dpll_ddr = {
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 8ca098b..9268895 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -12,6 +12,38 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+#include <asm/arch/omap.h>
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR	3
+#define HDR_ETH_ALEN		6
+#define HDR_NAME_LEN		8
+
+struct am43xx_board_id {
+	unsigned int  magic;
+	char name[HDR_NAME_LEN];
+	char version[4];
+	char serial[12];
+	char config[32];
+	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+	return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+}
+
 void enable_uart0_pin_mux(void);
 void enable_board_pin_mux(void);
 #endif
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 6693321..7810c59 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -25,6 +25,13 @@
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		48000000
 
+/* I2C Configuration */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
 /* SPL defines. */
 #define CONFIG_SPL_TEXT_BASE		0x40300350
 #define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
-- 
1.7.9.5

[U-Boot] [PATCH V2 05/14] ARM: AM43XX: board: add support for reading onboard EEPROM

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]
>  #define NON_SECURE_SRAM_START  0x402F0400
>  #define NON_SECURE_SRAM_END    0x40340000
>  #define SRAM_SCRATCH_SPACE_ADDR        0x4033C000
> +#define AM4372_BOARD_NAME_START        SRAM_SCRATCH_SPACE_ADDR
> +#define AM4372_BOARD_NAME_END  SRAM_SCRATCH_SPACE_ADDR + 0xC

Why do you need to keep the struct address hardcoded like this?

[...]
> +static inline int board_is_eposevm(void)
> +{
> +       return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
> +}
> +
> +static inline int board_is_gpevm(void)
> +{
> +       return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
> +}
> +

Looks like you got the EEPROM content updated ;)

Regards,
Vaibhav

[U-Boot] [PATCH V2 05/14] ARM: AM43XX: board: add support for reading onboard EEPROM

[Lokesh Vutla]

On Friday 22 November 2013 01:56 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
>>  #define NON_SECURE_SRAM_START  0x402F0400
>>  #define NON_SECURE_SRAM_END    0x40340000
>>  #define SRAM_SCRATCH_SPACE_ADDR        0x4033C000
>> +#define AM4372_BOARD_NAME_START        SRAM_SCRATCH_SPACE_ADDR
>> +#define AM4372_BOARD_NAME_END  SRAM_SCRATCH_SPACE_ADDR + 0xC
> 
> Why do you need to keep the struct address hardcoded like this?
FYI, this is not struct address. This is the place where where I am storing board name.
This helps in detecting the board.
It ll be good to understand the code properly and comment.
> 
> [...]
>> +static inline int board_is_eposevm(void)
>> +{
>> +       return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
>> +}
>> +
>> +static inline int board_is_gpevm(void)
>> +{
>> +       return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
>> +}
>> +
> 
> Looks like you got the EEPROM content updated ;)
There is nothing updated. This is what I have used previously.
Please recollect your comments properly.

Thanks and regards,
Lokesh
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 05/14] ARM: AM43XX: board: add support for reading onboard EEPROM

[Vaibhav Bedia]

On Sun, Nov 24, 2013 at 11:46 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 01:56 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> [...]
>>>  #define NON_SECURE_SRAM_START  0x402F0400
>>>  #define NON_SECURE_SRAM_END    0x40340000
>>>  #define SRAM_SCRATCH_SPACE_ADDR        0x4033C000
>>> +#define AM4372_BOARD_NAME_START        SRAM_SCRATCH_SPACE_ADDR
>>> +#define AM4372_BOARD_NAME_END  SRAM_SCRATCH_SPACE_ADDR + 0xC
>>
>> Why do you need to keep the struct address hardcoded like this?
> FYI, this is not struct address. This is the place where where I am storing board name.
> This helps in detecting the board.
> It ll be good to understand the code properly and comment.

My bad. Should have looked closer.

>>
>> [...]
>>> +static inline int board_is_eposevm(void)
>>> +{
>>> +       return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
>>> +}
>>> +
>>> +static inline int board_is_gpevm(void)
>>> +{
>>> +       return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
>>> +}
>>> +
>>
>> Looks like you got the EEPROM content updated ;)
> There is nothing updated. This is what I have used previously.
> Please recollect your comments properly.
>

Well it would help if you added in a more detailed changelog for the different
variants of the patches highlighting what's changed and if some comment is
being ignored the reason for the same.

Regards,
Vaibhav

[U-Boot] [PATCH V2 06/14] ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

[Lokesh Vutla]

From: Sekhar Nori <nsekhar@ti.com>

CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 board/ti/am43xx/board.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 4fc1a40..723d0ca 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -98,6 +98,22 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	char safe_string[HDR_NAME_LEN + 1];
+	struct am43xx_board_id header;
+
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	/* Now set variables based on the header. */
+	strncpy(safe_string, (char *)header.name, sizeof(header.name));
+	safe_string[sizeof(header.name)] = 0;
+	setenv("board_name", safe_string);
+
+	strncpy(safe_string, (char *)header.version, sizeof(header.version));
+	safe_string[sizeof(header.version)] = 0;
+	setenv("board_rev", safe_string);
+#endif
 	return 0;
 }
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH V2 06/14] ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> +       char safe_string[HDR_NAME_LEN + 1];
> +       struct am43xx_board_id header;
> +
> +       if (read_eeprom(&header) < 0)
> +               puts("Could not get board ID.\n");

Hmm... didn't the previous patch read the EEPROM?

[U-Boot] [PATCH V2 06/14] ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

[Lokesh Vutla]

On Friday 22 November 2013 01:58 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>> +       char safe_string[HDR_NAME_LEN + 1];
>> +       struct am43xx_board_id header;
>> +
>> +       if (read_eeprom(&header) < 0)
>> +               puts("Could not get board ID.\n");
> 
> Hmm... didn't the previous patch read the EEPROM?
This is as per suggested by Tom. If I populate a common structure it ll bread NOR boot.
I hope you understand what happens in NOR boot.

Thanks 
Lokesh
> 

[U-Boot] [PATCH V2 06/14] ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

[Vaibhav Bedia]

On Sun, Nov 24, 2013 at 11:48 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 01:58 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> [...]
>>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> +       char safe_string[HDR_NAME_LEN + 1];
>>> +       struct am43xx_board_id header;
>>> +
>>> +       if (read_eeprom(&header) < 0)
>>> +               puts("Could not get board ID.\n");
>>
>> Hmm... didn't the previous patch read the EEPROM?
> This is as per suggested by Tom. If I populate a common structure it ll bread NOR boot.
> I hope you understand what happens in NOR boot.
>

Care to explain how this particular snippet relates to NOR boot?

[U-Boot] [PATCH V2 07/14] ARM: AM43xx: Select clk source for Timer2

[Lokesh Vutla]

Selecting the Master osc clk as Timer2 clock source.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index c4890f2..22963b7 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -18,6 +18,7 @@
 
 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x560,
@@ -107,4 +108,7 @@ void enable_basic_clocks(void)
 	};
 
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+	/* Select the Master osc clk as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
 }
-- 
1.7.9.5

[U-Boot] [PATCH V2 07/14] ARM: AM43xx: Select clk source for Timer2

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> Selecting the Master osc clk as Timer2 clock source.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>  arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> index c4890f2..22963b7 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> @@ -18,6 +18,7 @@
>
>  struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
>  struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
> +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
>
>  const struct dpll_regs dpll_mpu_regs = {
>         .cm_clkmode_dpll        = CM_WKUP + 0x560,
> @@ -107,4 +108,7 @@ void enable_basic_clocks(void)
>         };
>
>         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
> +
> +       /* Select the Master osc clk as Timer2 clock source */
> +       writel(0x1, &cmdpll->clktimer2clk);

I really don't see a point of copying whatever AM335x does. You should
have a good reason for not using the other timers :P

[U-Boot] [PATCH V2 07/14] ARM: AM43xx: Select clk source for Timer2

[Lokesh Vutla]

On Friday 22 November 2013 02:01 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> Selecting the Master osc clk as Timer2 clock source.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>>  arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> index c4890f2..22963b7 100644
>> --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> @@ -18,6 +18,7 @@
>>
>>  struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
>>  struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
>> +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
>>
>>  const struct dpll_regs dpll_mpu_regs = {
>>         .cm_clkmode_dpll        = CM_WKUP + 0x560,
>> @@ -107,4 +108,7 @@ void enable_basic_clocks(void)
>>         };
>>
>>         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
>> +
>> +       /* Select the Master osc clk as Timer2 clock source */
>> +       writel(0x1, &cmdpll->clktimer2clk);
> 
> I really don't see a point of copying whatever AM335x does. You should
> have a good reason for not using the other timers :P
Again nothing is copied here, I am reusing the code what ever is present.
I don't have any restrictions to choose any timer here. All OMAPs and AM uses timer 2
and I used it. I have already told you why I can't use timer1.

First please give me a *valid reason* why I should not use timer2, then Ill think of using other timer.
As per my understanding there is nothing wrong to reuse what ever is present.
Please be specific when you are commenting.

Thanks
Lokesh
> 

[U-Boot] [PATCH V2 07/14] ARM: AM43xx: Select clk source for Timer2

[Vaibhav Bedia]

On Sun, Nov 24, 2013 at 11:53 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 02:01 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> Selecting the Master osc clk as Timer2 clock source.
>>>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> ---
>>>  arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    4 ++++
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>>> index c4890f2..22963b7 100644
>>> --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>>> +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>>> @@ -18,6 +18,7 @@
>>>
>>>  struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
>>>  struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
>>> +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
>>>
>>>  const struct dpll_regs dpll_mpu_regs = {
>>>         .cm_clkmode_dpll        = CM_WKUP + 0x560,
>>> @@ -107,4 +108,7 @@ void enable_basic_clocks(void)
>>>         };
>>>
>>>         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
>>> +
>>> +       /* Select the Master osc clk as Timer2 clock source */
>>> +       writel(0x1, &cmdpll->clktimer2clk);
>>
>> I really don't see a point of copying whatever AM335x does. You should
>> have a good reason for not using the other timers :P
> Again nothing is copied here, I am reusing the code what ever is present.
> I don't have any restrictions to choose any timer here. All OMAPs and AM uses timer 2
> and I used it. I have already told you why I can't use timer1.
>

If by that you are referring to your reasoning that there's a base
address that's already
there and hence let's reuse it, then yes you did.

> First please give me a *valid reason* why I should not use timer2, then Ill think of using other timer.
> As per my understanding there is nothing wrong to reuse what ever is present.
> Please be specific when you are commenting.
>

And the reuse without rethink is exactly how over a period of time we
end up with choices in s/w that no one can recollect.... have it your way :)

Regards,
Vaibhav

[U-Boot] [PATCH V2 08/14] ARM: AM43xx: Update Current Booting devices list

[Lokesh Vutla]

Current Booting devices list is different from that of AM33xx.
Updating the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/spl.h |   12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 95de9aa..82116a9 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -13,11 +13,17 @@
 #define BOOT_DEVICE_MMC1	6
 #define BOOT_DEVICE_MMC2	5
 #define BOOT_DEVICE_UART	0x43
-#define BOOT_DEVICE_MMC2_2	0xFF
+#elif defined(CONFIG_AM43XX)
+#define BOOT_DEVICE_NOR		1
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	7
+#define BOOT_DEVICE_MMC2	8
+#define BOOT_DEVICE_SPI		10
+#define BOOT_DEVICE_UART	65
 #else
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
-#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
+#if defined(CONFIG_AM33XX)
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
 #elif defined(CONFIG_TI814X)
@@ -28,8 +34,8 @@
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_USBETH	68
 #define BOOT_DEVICE_CPGMAC	70
-#define BOOT_DEVICE_MMC2_2      0xFF
 #endif
+#define BOOT_DEVICE_MMC2_2      0xFF
 
 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
-- 
1.7.9.5

[U-Boot] [PATCH V2 09/14] ARM: AM43xx: mux: Update mux data

[Lokesh Vutla]

Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/include/asm/arch-am33xx/mux_am43xx.h |   45 +++++++++++++++++++++++++
 board/ti/am43xx/mux.c                         |   22 ++++++++++--
 2 files changed, 65 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index 0206912..98fc2b5 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -137,6 +137,51 @@ struct pad_signals {
 	int mcasp0_fsr;
 	int mcasp0_axr1;
 	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
 };
 
 #endif /* _MUX_AM43XX_H_ */
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 700e9a7..46bad01 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -12,8 +12,24 @@
 #include "board.h"
 
 static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0))},			/* UART0_TXD */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)},  /* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
 	{-1},
 };
 
@@ -24,4 +40,6 @@ void enable_uart0_pin_mux(void)
 
 void enable_board_pin_mux(void)
 {
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
 }
-- 
1.7.9.5

[U-Boot] [PATCH V2 09/14] ARM: AM43xx: mux: Update mux data

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> Updating the mux data for UART, adding data for i2c0 and mmc.
> And also updating pad_signals structure.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>  arch/arm/include/asm/arch-am33xx/mux_am43xx.h |   45 +++++++++++++++++++++++++
>  board/ti/am43xx/mux.c                         |   22 ++++++++++--
>  2 files changed, 65 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
> index 0206912..98fc2b5 100644
> --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
> +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
> @@ -137,6 +137,51 @@ struct pad_signals {
>         int mcasp0_fsr;
>         int mcasp0_axr1;
>         int mcasp0_ahclkx;
> +       int xdma_event_intr0;
> +       int xdma_event_intr1;
> +       int nresetin_out;
> +       int porz;
> +       int nnmi;
> +       int osc0_in;
> +       int osc0_out;
> +       int rsvd1;
> +       int tms;
> +       int tdi;
> +       int tdo;
> +       int tck;
> +       int ntrst;
> +       int emu0;
> +       int emu1;
> +       int osc1_in;
> +       int osc1_out;
> +       int pmic_power_en;
> +       int rtc_porz;
> +       int rsvd2;
> +       int ext_wakeup;
> +       int enz_kaldo_1p8v;
> +       int usb0_dm;
> +       int usb0_dp;
> +       int usb0_ce;
> +       int usb0_id;
> +       int usb0_vbus;
> +       int usb0_drvvbus;
> +       int usb1_dm;
> +       int usb1_dp;
> +       int usb1_ce;
> +       int usb1_id;
> +       int usb1_vbus;
> +       int usb1_drvvbus;
> +       int ddr_resetn;
> +       int ddr_csn0;
> +       int ddr_cke;
> +       int ddr_ck;
> +       int ddr_nck;
> +       int ddr_casn;
> +       int ddr_rasn;
> +       int ddr_wen;
> +       int ddr_ba0;
> +       int ddr_ba1;
> +       int ddr_ba2;
>  };

IIRC not all the pads over here have any IO control. Some are analog pins
and some like JTAG, PORz really shouldn't be meddled with if the h/w does
expose some configuration. Please revisit this change.

>
>  #endif /* _MUX_AM43XX_H_ */
> diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
> index 700e9a7..46bad01 100644
> --- a/board/ti/am43xx/mux.c
> +++ b/board/ti/am43xx/mux.c
> @@ -12,8 +12,24 @@
>  #include "board.h"
>
>  static struct module_pin_mux uart0_pin_mux[] = {
> -       {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)},      /* UART0_RXD */
> -       {OFFSET(uart0_txd), (MODE(0))},                 /* UART0_TXD */
> +       {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
> +       {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
> +       {-1},

SLEWCTRL is typically not changed. You might want to double check this portion
with the h/w folks.

Regards,
Vaibhav

[U-Boot] [PATCH V2 09/14] ARM: AM43xx: mux: Update mux data

[Lokesh Vutla]

On Friday 22 November 2013 02:04 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> Updating the mux data for UART, adding data for i2c0 and mmc.
>> And also updating pad_signals structure.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>>  arch/arm/include/asm/arch-am33xx/mux_am43xx.h |   45 +++++++++++++++++++++++++
>>  board/ti/am43xx/mux.c                         |   22 ++++++++++--
>>  2 files changed, 65 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>> index 0206912..98fc2b5 100644
>> --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>> +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>> @@ -137,6 +137,51 @@ struct pad_signals {
>>         int mcasp0_fsr;
>>         int mcasp0_axr1;
>>         int mcasp0_ahclkx;
>> +       int xdma_event_intr0;
>> +       int xdma_event_intr1;
>> +       int nresetin_out;
>> +       int porz;
>> +       int nnmi;
>> +       int osc0_in;
>> +       int osc0_out;
>> +       int rsvd1;
>> +       int tms;
>> +       int tdi;
>> +       int tdo;
>> +       int tck;
>> +       int ntrst;
>> +       int emu0;
>> +       int emu1;
>> +       int osc1_in;
>> +       int osc1_out;
>> +       int pmic_power_en;
>> +       int rtc_porz;
>> +       int rsvd2;
>> +       int ext_wakeup;
>> +       int enz_kaldo_1p8v;
>> +       int usb0_dm;
>> +       int usb0_dp;
>> +       int usb0_ce;
>> +       int usb0_id;
>> +       int usb0_vbus;
>> +       int usb0_drvvbus;
>> +       int usb1_dm;
>> +       int usb1_dp;
>> +       int usb1_ce;
>> +       int usb1_id;
>> +       int usb1_vbus;
>> +       int usb1_drvvbus;
>> +       int ddr_resetn;
>> +       int ddr_csn0;
>> +       int ddr_cke;
>> +       int ddr_ck;
>> +       int ddr_nck;
>> +       int ddr_casn;
>> +       int ddr_rasn;
>> +       int ddr_wen;
>> +       int ddr_ba0;
>> +       int ddr_ba1;
>> +       int ddr_ba2;
>>  };
> 
> IIRC not all the pads over here have any IO control. Some are analog pins
> and some like JTAG, PORz really shouldn't be meddled with if the h/w does
> expose some configuration. Please revisit this change.
Nothing to be revisited here. I have to use ddr_ba2 for VTT, so I have
populated the structure till this point. 
I don't see any error to update a structure so that I can use the desired pins.
I am not using the pins what ever you have mentioned. I purposefully populated those
because I don't want make them as reserved.
> 
>>
>>  #endif /* _MUX_AM43XX_H_ */
>> diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
>> index 700e9a7..46bad01 100644
>> --- a/board/ti/am43xx/mux.c
>> +++ b/board/ti/am43xx/mux.c
>> @@ -12,8 +12,24 @@
>>  #include "board.h"
>>
>>  static struct module_pin_mux uart0_pin_mux[] = {
>> -       {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)},      /* UART0_RXD */
>> -       {OFFSET(uart0_txd), (MODE(0))},                 /* UART0_TXD */
>> +       {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
>> +       {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
>> +       {-1},
> 
> SLEWCTRL is typically not changed. You might want to double check this portion
> with the h/w folks.
I have checked with h/w folks, they said nothing wrong here.

Thanks
Lokesh
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 09/14] ARM: AM43xx: mux: Update mux data

[Vaibhav Bedia]

On Sun, Nov 24, 2013 at 11:59 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 02:04 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> Updating the mux data for UART, adding data for i2c0 and mmc.
>>> And also updating pad_signals structure.
>>>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> ---
>>>  arch/arm/include/asm/arch-am33xx/mux_am43xx.h |   45 +++++++++++++++++++++++++
>>>  board/ti/am43xx/mux.c                         |   22 ++++++++++--
>>>  2 files changed, 65 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>>> index 0206912..98fc2b5 100644
>>> --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>>> +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
>>> @@ -137,6 +137,51 @@ struct pad_signals {
>>>         int mcasp0_fsr;
>>>         int mcasp0_axr1;
>>>         int mcasp0_ahclkx;
>>> +       int xdma_event_intr0;
>>> +       int xdma_event_intr1;
>>> +       int nresetin_out;
>>> +       int porz;
>>> +       int nnmi;
>>> +       int osc0_in;
>>> +       int osc0_out;
>>> +       int rsvd1;
>>> +       int tms;
>>> +       int tdi;
>>> +       int tdo;
>>> +       int tck;
>>> +       int ntrst;
>>> +       int emu0;
>>> +       int emu1;
>>> +       int osc1_in;
>>> +       int osc1_out;
>>> +       int pmic_power_en;
>>> +       int rtc_porz;
>>> +       int rsvd2;
>>> +       int ext_wakeup;
>>> +       int enz_kaldo_1p8v;
>>> +       int usb0_dm;
>>> +       int usb0_dp;
>>> +       int usb0_ce;
>>> +       int usb0_id;
>>> +       int usb0_vbus;
>>> +       int usb0_drvvbus;
>>> +       int usb1_dm;
>>> +       int usb1_dp;
>>> +       int usb1_ce;
>>> +       int usb1_id;
>>> +       int usb1_vbus;
>>> +       int usb1_drvvbus;
>>> +       int ddr_resetn;
>>> +       int ddr_csn0;
>>> +       int ddr_cke;
>>> +       int ddr_ck;
>>> +       int ddr_nck;
>>> +       int ddr_casn;
>>> +       int ddr_rasn;
>>> +       int ddr_wen;
>>> +       int ddr_ba0;
>>> +       int ddr_ba1;
>>> +       int ddr_ba2;
>>>  };
>>
>> IIRC not all the pads over here have any IO control. Some are analog pins
>> and some like JTAG, PORz really shouldn't be meddled with if the h/w does
>> expose some configuration. Please revisit this change.
> Nothing to be revisited here. I have to use ddr_ba2 for VTT, so I have
> populated the structure till this point.
> I don't see any error to update a structure so that I can use the desired pins.
> I am not using the pins what ever you have mentioned. I purposefully populated those
> because I don't want make them as reserved.

I think i gave a good enough technical reason why that's not a good thing to do.
If you really don't see the shortcomings of that i have nothing more
to add here.

>>
>>>
>>>  #endif /* _MUX_AM43XX_H_ */
>>> diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
>>> index 700e9a7..46bad01 100644
>>> --- a/board/ti/am43xx/mux.c
>>> +++ b/board/ti/am43xx/mux.c
>>> @@ -12,8 +12,24 @@
>>>  #include "board.h"
>>>
>>>  static struct module_pin_mux uart0_pin_mux[] = {
>>> -       {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)},      /* UART0_RXD */
>>> -       {OFFSET(uart0_txd), (MODE(0))},                 /* UART0_TXD */
>>> +       {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
>>> +       {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
>>> +       {-1},
>>
>> SLEWCTRL is typically not changed. You might want to double check this portion
>> with the h/w folks.
> I have checked with h/w folks, they said nothing wrong here.
>
Fine with me.

Regards,
Vaibhav

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Lokesh Vutla]

Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
Following are the DPLL locking frequencies at OPP NOM:
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 266MHz

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/clock.c        |   12 +++++++---
 arch/arm/cpu/armv7/am33xx/clock_am33xx.c |   15 ++++++++++++
 arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    8 +------
 arch/arm/include/asm/arch-am33xx/clock.h |    7 +++---
 board/ti/am43xx/board.c                  |   38 +++++++++++++++++++++++++++---
 board/ti/am43xx/board.h                  |    1 +
 board/ti/am43xx/mux.c                    |    5 ++++
 7 files changed, 69 insertions(+), 17 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 8e5f3c6..0672798 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
 static void setup_dplls(void)
 {
 	const struct dpll_params *params;
-	do_setup_dpll(&dpll_core_regs, &dpll_core);
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
-	do_setup_dpll(&dpll_per_regs, &dpll_per);
+
+	params = get_dpll_core_params();
+	do_setup_dpll(&dpll_core_regs, params);
+
+	params = get_dpll_mpu_params();
+	do_setup_dpll(&dpll_mpu_regs, params);
+
+	params = get_dpll_per_params();
+	do_setup_dpll(&dpll_per_regs, params);
 	writel(0x300, &cmwkup->clkdcoldodpllper);
 
 	params = get_dpll_ddr_params();
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index fabe259..92142c8 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	return &dpll_per;
+}
+
 void setup_clocks_for_console(void)
 {
 	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 22963b7..97c00b4 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
 	.cm_idlest_dpll		= CM_WKUP + 0x5A4,
 	.cm_clksel_dpll		= CM_WKUP + 0x5AC,
 	.cm_div_m2_dpll		= CM_WKUP + 0x5B0,
+	.cm_div_m4_dpll		= CM_WKUP + 0x5B8,
 };
 
-const struct dpll_params dpll_mpu = {
-		-1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-		-1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_per = {
-		-1, -1, -1, -1, -1, -1, -1};
-
 void setup_clocks_for_console(void)
 {
 	/* Do not add any spl_debug prints in this function */
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 519249e..7637457 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
 extern const struct dpll_regs dpll_core_regs;
 extern const struct dpll_regs dpll_per_regs;
 extern const struct dpll_regs dpll_ddr_regs;
-extern const struct dpll_params dpll_mpu;
-extern const struct dpll_params dpll_core;
-extern const struct dpll_params dpll_per;
-extern const struct dpll_params dpll_ddr;
 
 extern struct cm_wkuppll *const cmwkup;
 
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
 const struct dpll_params *get_dpll_ddr_params(void);
 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
 void prcm_init(void);
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 723d0ca..2d1b8f9 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
 
 #ifdef CONFIG_SPL_BUILD
 
-const struct dpll_params dpll_ddr = {
-		-1, -1, -1, -1, -1, -1, -1};
+const struct dpll_params epos_evm_dpll_ddr = {
+		266, 24, 1, -1, 1, -1, -1};
+const struct dpll_params epos_evm_dpll_mpu = {
+		600, 24, 1, -1, -1, -1, -1};
+const struct dpll_params epos_evm_dpll_core = {
+		1000, 24, -1, -1, 10, 8, 4};
+const struct dpll_params epos_evm_dpll_per = {
+		960, 24, 5, -1, -1, -1, -1};
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
-	return &dpll_ddr;
+	if (board_is_eposevm())
+		return &epos_evm_dpll_ddr;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	if (board_is_eposevm())
+		return &epos_evm_dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+	struct am43xx_board_id header;
+
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+	if (read_eeprom(&header) < 0)
+		puts("Could not get board ID.\n");
+
+	if (board_is_eposevm())
+		return &epos_evm_dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+	if (board_is_eposevm())
+		return &epos_evm_dpll_per;
 }
 
 void set_uart_mux_conf(void)
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 9268895..beee770 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -46,4 +46,5 @@ static inline int board_is_gpevm(void)
 
 void enable_uart0_pin_mux(void);
 void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
 #endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 46bad01..a2d72dd 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -43,3 +43,8 @@ void enable_board_pin_mux(void)
 	configure_module_pin_mux(mmc0_pin_mux);
 	configure_module_pin_mux(i2c0_pin_mux);
 }
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
-- 
1.7.9.5

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
> Following are the DPLL locking frequencies at OPP NOM:
> MPU locks at 600MHz
> Core locks at 1000MHz
> Per locks at 960MHz
> DDR locks at 266MHz
>

As mentioned earlier, this hardcoded frequency approach is really not
scalable when you have
more device variants coming in. Just look at the AM335x changes on how
this gets complicated.

> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>  arch/arm/cpu/armv7/am33xx/clock.c        |   12 +++++++---
>  arch/arm/cpu/armv7/am33xx/clock_am33xx.c |   15 ++++++++++++
>  arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    8 +------
>  arch/arm/include/asm/arch-am33xx/clock.h |    7 +++---
>  board/ti/am43xx/board.c                  |   38 +++++++++++++++++++++++++++---
>  board/ti/am43xx/board.h                  |    1 +
>  board/ti/am43xx/mux.c                    |    5 ++++
>  7 files changed, 69 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
> index 8e5f3c6..0672798 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock.c
> @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
>  static void setup_dplls(void)
>  {
>         const struct dpll_params *params;
> -       do_setup_dpll(&dpll_core_regs, &dpll_core);
> -       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
> -       do_setup_dpll(&dpll_per_regs, &dpll_per);
> +
> +       params = get_dpll_core_params();
> +       do_setup_dpll(&dpll_core_regs, params);
> +
> +       params = get_dpll_mpu_params();
> +       do_setup_dpll(&dpll_mpu_regs, params);
> +
> +       params = get_dpll_per_params();
> +       do_setup_dpll(&dpll_per_regs, params);
>         writel(0x300, &cmwkup->clkdcoldodpllper);
>
>         params = get_dpll_ddr_params();
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> index fabe259..92142c8 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
>  const struct dpll_params dpll_per = {
>                 960, OSC-1, 5, -1, -1, -1, -1};
>
> +const struct dpll_params *get_dpll_mpu_params(void)
> +{
> +       return &dpll_mpu;
> +}
> +
> +const struct dpll_params *get_dpll_core_params(void)
> +{
> +       return &dpll_core;
> +}
> +
> +const struct dpll_params *get_dpll_per_params(void)
> +{
> +       return &dpll_per;
> +}
> +
>  void setup_clocks_for_console(void)
>  {
>         clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> index 22963b7..97c00b4 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
> @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
>         .cm_idlest_dpll         = CM_WKUP + 0x5A4,
>         .cm_clksel_dpll         = CM_WKUP + 0x5AC,
>         .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
> +       .cm_div_m4_dpll         = CM_WKUP + 0x5B8,
>  };
>
> -const struct dpll_params dpll_mpu = {
> -               -1, -1, -1, -1, -1, -1, -1};
> -const struct dpll_params dpll_core = {
> -               -1, -1, -1, -1, -1, -1, -1};
> -const struct dpll_params dpll_per = {
> -               -1, -1, -1, -1, -1, -1, -1};
> -
>  void setup_clocks_for_console(void)
>  {
>         /* Do not add any spl_debug prints in this function */
> diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
> index 519249e..7637457 100644
> --- a/arch/arm/include/asm/arch-am33xx/clock.h
> +++ b/arch/arm/include/asm/arch-am33xx/clock.h
> @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
>  extern const struct dpll_regs dpll_core_regs;
>  extern const struct dpll_regs dpll_per_regs;
>  extern const struct dpll_regs dpll_ddr_regs;
> -extern const struct dpll_params dpll_mpu;
> -extern const struct dpll_params dpll_core;
> -extern const struct dpll_params dpll_per;
> -extern const struct dpll_params dpll_ddr;
>
>  extern struct cm_wkuppll *const cmwkup;
>
> +const struct dpll_params *get_dpll_mpu_params(void);
> +const struct dpll_params *get_dpll_core_params(void);
> +const struct dpll_params *get_dpll_per_params(void);
>  const struct dpll_params *get_dpll_ddr_params(void);
>  void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
>  void prcm_init(void);
> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
> index 723d0ca..2d1b8f9 100644
> --- a/board/ti/am43xx/board.c
> +++ b/board/ti/am43xx/board.c
> @@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
>
>  #ifdef CONFIG_SPL_BUILD
>
> -const struct dpll_params dpll_ddr = {
> -               -1, -1, -1, -1, -1, -1, -1};
> +const struct dpll_params epos_evm_dpll_ddr = {
> +               266, 24, 1, -1, 1, -1, -1};
> +const struct dpll_params epos_evm_dpll_mpu = {
> +               600, 24, 1, -1, -1, -1, -1};
> +const struct dpll_params epos_evm_dpll_core = {
> +               1000, 24, -1, -1, 10, 8, 4};
> +const struct dpll_params epos_evm_dpll_per = {
> +               960, 24, 5, -1, -1, -1, -1};
>
>  const struct dpll_params *get_dpll_ddr_params(void)
>  {
> -       return &dpll_ddr;
> +       if (board_is_eposevm())
> +               return &epos_evm_dpll_ddr;
> +}
> +
> +const struct dpll_params *get_dpll_mpu_params(void)
> +{
> +       if (board_is_eposevm())
> +               return &epos_evm_dpll_mpu;
> +}
> +
> +const struct dpll_params *get_dpll_core_params(void)
> +{
> +       struct am43xx_board_id header;
> +
> +       enable_i2c0_pin_mux();
> +       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
> +       if (read_eeprom(&header) < 0)
> +               puts("Could not get board ID.\n");
> +

Reading the EEPROM again? Why don't you just read it once and update some
common structure?

Regards,
Vaibhav

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Lokesh Vutla]

On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>> Following are the DPLL locking frequencies at OPP NOM:
>> MPU locks at 600MHz
>> Core locks at 1000MHz
>> Per locks at 960MHz
>> DDR locks at 266MHz
>>
> 
> As mentioned earlier, this hardcoded frequency approach is really not
> scalable when you have
> more device variants coming in. Just look at the AM335x changes on how
> this gets complicated.
We already had a discussion on this during V1 of this series.
Sekhar and Tom replied to you comments. What is the point in asking the same question again?

Since you are very concerned here. Why are you feeling it so complicated when new variants come?
We can always differentiate the new variant from the old ones and can pass dpll structure accordingly. It is just a matter a one if condition.
It ll be better to look at the current code and see how cleanly it is done.

Thanks
Lokesh

> 
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>>  arch/arm/cpu/armv7/am33xx/clock.c        |   12 +++++++---
>>  arch/arm/cpu/armv7/am33xx/clock_am33xx.c |   15 ++++++++++++
>>  arch/arm/cpu/armv7/am33xx/clock_am43xx.c |    8 +------
>>  arch/arm/include/asm/arch-am33xx/clock.h |    7 +++---
>>  board/ti/am43xx/board.c                  |   38 +++++++++++++++++++++++++++---
>>  board/ti/am43xx/board.h                  |    1 +
>>  board/ti/am43xx/mux.c                    |    5 ++++
>>  7 files changed, 69 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
>> index 8e5f3c6..0672798 100644
>> --- a/arch/arm/cpu/armv7/am33xx/clock.c
>> +++ b/arch/arm/cpu/armv7/am33xx/clock.c
>> @@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
>>  static void setup_dplls(void)
>>  {
>>         const struct dpll_params *params;
>> -       do_setup_dpll(&dpll_core_regs, &dpll_core);
>> -       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
>> -       do_setup_dpll(&dpll_per_regs, &dpll_per);
>> +
>> +       params = get_dpll_core_params();
>> +       do_setup_dpll(&dpll_core_regs, params);
>> +
>> +       params = get_dpll_mpu_params();
>> +       do_setup_dpll(&dpll_mpu_regs, params);
>> +
>> +       params = get_dpll_per_params();
>> +       do_setup_dpll(&dpll_per_regs, params);
>>         writel(0x300, &cmwkup->clkdcoldodpllper);
>>
>>         params = get_dpll_ddr_params();
>> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
>> index fabe259..92142c8 100644
>> --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
>> +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
>> @@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
>>  const struct dpll_params dpll_per = {
>>                 960, OSC-1, 5, -1, -1, -1, -1};
>>
>> +const struct dpll_params *get_dpll_mpu_params(void)
>> +{
>> +       return &dpll_mpu;
>> +}
>> +
>> +const struct dpll_params *get_dpll_core_params(void)
>> +{
>> +       return &dpll_core;
>> +}
>> +
>> +const struct dpll_params *get_dpll_per_params(void)
>> +{
>> +       return &dpll_per;
>> +}
>> +
>>  void setup_clocks_for_console(void)
>>  {
>>         clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
>> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> index 22963b7..97c00b4 100644
>> --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>> @@ -48,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
>>         .cm_idlest_dpll         = CM_WKUP + 0x5A4,
>>         .cm_clksel_dpll         = CM_WKUP + 0x5AC,
>>         .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
>> +       .cm_div_m4_dpll         = CM_WKUP + 0x5B8,
>>  };
>>
>> -const struct dpll_params dpll_mpu = {
>> -               -1, -1, -1, -1, -1, -1, -1};
>> -const struct dpll_params dpll_core = {
>> -               -1, -1, -1, -1, -1, -1, -1};
>> -const struct dpll_params dpll_per = {
>> -               -1, -1, -1, -1, -1, -1, -1};
>> -
>>  void setup_clocks_for_console(void)
>>  {
>>         /* Do not add any spl_debug prints in this function */
>> diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
>> index 519249e..7637457 100644
>> --- a/arch/arm/include/asm/arch-am33xx/clock.h
>> +++ b/arch/arm/include/asm/arch-am33xx/clock.h
>> @@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
>>  extern const struct dpll_regs dpll_core_regs;
>>  extern const struct dpll_regs dpll_per_regs;
>>  extern const struct dpll_regs dpll_ddr_regs;
>> -extern const struct dpll_params dpll_mpu;
>> -extern const struct dpll_params dpll_core;
>> -extern const struct dpll_params dpll_per;
>> -extern const struct dpll_params dpll_ddr;
>>
>>  extern struct cm_wkuppll *const cmwkup;
>>
>> +const struct dpll_params *get_dpll_mpu_params(void);
>> +const struct dpll_params *get_dpll_core_params(void);
>> +const struct dpll_params *get_dpll_per_params(void);
>>  const struct dpll_params *get_dpll_ddr_params(void);
>>  void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
>>  void prcm_init(void);
>> diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
>> index 723d0ca..2d1b8f9 100644
>> --- a/board/ti/am43xx/board.c
>> +++ b/board/ti/am43xx/board.c
>> @@ -65,12 +65,44 @@ static int read_eeprom(struct am43xx_board_id *header)
>>
>>  #ifdef CONFIG_SPL_BUILD
>>
>> -const struct dpll_params dpll_ddr = {
>> -               -1, -1, -1, -1, -1, -1, -1};
>> +const struct dpll_params epos_evm_dpll_ddr = {
>> +               266, 24, 1, -1, 1, -1, -1};
>> +const struct dpll_params epos_evm_dpll_mpu = {
>> +               600, 24, 1, -1, -1, -1, -1};
>> +const struct dpll_params epos_evm_dpll_core = {
>> +               1000, 24, -1, -1, 10, 8, 4};
>> +const struct dpll_params epos_evm_dpll_per = {
>> +               960, 24, 5, -1, -1, -1, -1};
>>
>>  const struct dpll_params *get_dpll_ddr_params(void)
>>  {
>> -       return &dpll_ddr;
>> +       if (board_is_eposevm())
>> +               return &epos_evm_dpll_ddr;
>> +}
>> +
>> +const struct dpll_params *get_dpll_mpu_params(void)
>> +{
>> +       if (board_is_eposevm())
>> +               return &epos_evm_dpll_mpu;
>> +}
>> +
>> +const struct dpll_params *get_dpll_core_params(void)
>> +{
>> +       struct am43xx_board_id header;
>> +
>> +       enable_i2c0_pin_mux();
>> +       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
>> +       if (read_eeprom(&header) < 0)
>> +               puts("Could not get board ID.\n");
>> +
> 
> Reading the EEPROM again? Why don't you just read it once and update some
> common structure?
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Vaibhav Bedia]

On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>>> Following are the DPLL locking frequencies at OPP NOM:
>>> MPU locks at 600MHz
>>> Core locks at 1000MHz
>>> Per locks at 960MHz
>>> DDR locks at 266MHz
>>>
>>
>> As mentioned earlier, this hardcoded frequency approach is really not
>> scalable when you have
>> more device variants coming in. Just look at the AM335x changes on how
>> this gets complicated.
> We already had a discussion on this during V1 of this series.
> Sekhar and Tom replied to you comments. What is the point in asking the same question again?
>

Because i don't recall any conclusion being reached on that thread? Because the
objective of a patch review is to come up with a solution which learns
from the past
and doesn't try to brush the past issues under the carpet under the
assumption that
the shiny new device will never have bugs?

> Since you are very concerned here. Why are you feeling it so complicated when new variants come?
> We can always differentiate the new variant from the old ones and can pass dpll structure accordingly. It is just a matter a one if condition.
> It ll be better to look at the current code and see how cleanly it is done.
>

As the OPP decoder table in the AM335x datasheet will tell you it's
not that simple.
Frankly, i could care less about this change...

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Lokesh Vutla]

On Wednesday 27 November 2013 05:36 AM, Vaibhav Bedia wrote:
> On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>>>> Following are the DPLL locking frequencies at OPP NOM:
>>>> MPU locks at 600MHz
>>>> Core locks at 1000MHz
>>>> Per locks at 960MHz
>>>> DDR locks at 266MHz
>>>>
>>>
>>> As mentioned earlier, this hardcoded frequency approach is really not
>>> scalable when you have
>>> more device variants coming in. Just look at the AM335x changes on how
>>> this gets complicated.
>> We already had a discussion on this during V1 of this series.
>> Sekhar and Tom replied to you comments. What is the point in asking the same question again?
>>
> 
> Because i don't recall any conclusion being reached on that thread? Because the
> objective of a patch review is to come up with a solution which learns
> from the past
> and doesn't try to brush the past issues under the carpet under the
> assumption that
> the shiny new device will never have bugs?
Yes I agree with you point.
But I have replied to this thread saying that 
"Currently these values are not blown in eFuse. Both EPOS and GP evms support 
OPP NOM. So there is no harm in booting at OPP NOM here."
You haven't come back on that. 

> 
>> Since you are very concerned here. Why are you feeling it so complicated when new variants come?
>> We can always differentiate the new variant from the old ones and can pass dpll structure accordingly. It is just a matter a one if condition.
>> It ll be better to look at the current code and see how cleanly it is done.
>>
> 
> As the OPP decoder table in the AM335x datasheet will tell you it's
> not that simple.
I guess your previous comment was about the code complexity when a new variant of the board comes.
Coming to OPP tables:
Frankly, I don't know what happened during AM33xx times. I am just trying to make things simpler and cleaner.
Do you mean here, we need to support  all OPPs in U-Boot?
Are you expecting complete OPP table to get from e-fuse values for AM43xx?

As per my understanding from working on OMAP, U-Boot supports only OPP_NOM( or the safe OPP to boot).

Please correct me if I am wrong.

Thanks and regards,
Lokesh 
> Frankly, i could care less about this change...
> 

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Vaibhav Bedia]

On Wed, Nov 27, 2013 at 1:58 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Wednesday 27 November 2013 05:36 AM, Vaibhav Bedia wrote:
>> On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>>>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>>>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>>>>> Following are the DPLL locking frequencies at OPP NOM:
>>>>> MPU locks at 600MHz
>>>>> Core locks at 1000MHz
>>>>> Per locks at 960MHz
>>>>> DDR locks at 266MHz
>>>>>
>>>>
>>>> As mentioned earlier, this hardcoded frequency approach is really not
>>>> scalable when you have
>>>> more device variants coming in. Just look at the AM335x changes on how
>>>> this gets complicated.
>>> We already had a discussion on this during V1 of this series.
>>> Sekhar and Tom replied to you comments. What is the point in asking the same question again?
>>>
>>
>> Because i don't recall any conclusion being reached on that thread? Because the
>> objective of a patch review is to come up with a solution which learns
>> from the past
>> and doesn't try to brush the past issues under the carpet under the
>> assumption that
>> the shiny new device will never have bugs?
> Yes I agree with you point.
> But I have replied to this thread saying that
> "Currently these values are not blown in eFuse. Both EPOS and GP evms support
> OPP NOM. So there is no harm in booting at OPP NOM here."
> You haven't come back on that.
>

Sorry i somehow missed replying to that.

So here's the thing. Right now you are told that all the devices
support OPP NOM and hence as the U-Boot maintainer for AM437x
you go ahead and use that information. However, few days down the
line you'll have different speed grades coming out of the fab and some
of them are going to have a max OPP that's lower than what OPP_NOM
means. After a few devices blow up and some mails go around the
world your code gets blamed and you hastily come up with a patch
which tries to address the slower devices. The future you then realizes
that you need some mechanism the differentiate the old devices without
the eFuse information and the new which do. You might discover that
there's some board rev check or something like that can be used. But that's
only if you are lucky. I hope you see where this is going.

So what can you do?
A. Go ahead with OPP NOM and be prepared to debug boot failures on
random boards only to discover that the devices are not meant to operate
at OPP_NOM.

B. Find the lowest common denominator for the supported OPPs and use
that in here. This might end up making some folks unhappy but then you
need to make a choice between fast and reliable and i would personally go
for the latter. If folks really care about boot times someone needs to start
putting the right information in the eFuses at the right time.

>>
>>> Since you are very concerned here. Why are you feeling it so complicated when new variants come?
>>> We can always differentiate the new variant from the old ones and can pass dpll structure accordingly. It is just a matter a one if condition.
>>> It ll be better to look at the current code and see how cleanly it is done.
>>>
>>
>> As the OPP decoder table in the AM335x datasheet will tell you it's
>> not that simple.
> I guess your previous comment was about the code complexity when a new variant of the board comes.
> Coming to OPP tables:
> Frankly, I don't know what happened during AM33xx times. I am just trying to make things simpler and cleaner.
> Do you mean here, we need to support  all OPPs in U-Boot?
> Are you expecting complete OPP table to get from e-fuse values for AM43xx?
>
> As per my understanding from working on OMAP, U-Boot supports only OPP_NOM( or the safe OPP to boot).
>
> Please correct me if I am wrong.
>

I hope the verbiage above helps you get an idea of why i am insisting on
a change here.

I am not asking U-Boot to have the complete OPP table. That's for the kernel
+ device-tree to handle. If there's no eFuse data in the devices, hard luck.
We do the only thing we can for reliable boots and that's to use an OPP which
is reliable all the time.

If you still think OPP_NOM is the right choice please go ahead and use it.

Regards,
Vaibhav

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Lokesh Vutla]

On Thursday 28 November 2013 04:18 AM, Vaibhav Bedia wrote:
> On Wed, Nov 27, 2013 at 1:58 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> On Wednesday 27 November 2013 05:36 AM, Vaibhav Bedia wrote:
>>> On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>>> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>>>>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>>>>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>>>>>> Following are the DPLL locking frequencies at OPP NOM:
>>>>>> MPU locks at 600MHz
>>>>>> Core locks at 1000MHz
>>>>>> Per locks at 960MHz
>>>>>> DDR locks at 266MHz
>>>>>>
>>>>>
>>>>> As mentioned earlier, this hardcoded frequency approach is really not
>>>>> scalable when you have
>>>>> more device variants coming in. Just look at the AM335x changes on how
>>>>> this gets complicated.
>>>> We already had a discussion on this during V1 of this series.
>>>> Sekhar and Tom replied to you comments. What is the point in asking the same question again?
>>>>
>>>
>>> Because i don't recall any conclusion being reached on that thread? Because the
>>> objective of a patch review is to come up with a solution which learns
>>> from the past
>>> and doesn't try to brush the past issues under the carpet under the
>>> assumption that
>>> the shiny new device will never have bugs?
>> Yes I agree with you point.
>> But I have replied to this thread saying that
>> "Currently these values are not blown in eFuse. Both EPOS and GP evms support
>> OPP NOM. So there is no harm in booting at OPP NOM here."
>> You haven't come back on that.
>>
> 
> Sorry i somehow missed replying to that.
> 
> So here's the thing. Right now you are told that all the devices
> support OPP NOM and hence as the U-Boot maintainer for AM437x
> you go ahead and use that information. However, few days down the
> line you'll have different speed grades coming out of the fab and some
> of them are going to have a max OPP that's lower than what OPP_NOM
> means. After a few devices blow up and some mails go around the
> world your code gets blamed and you hastily come up with a patch
> which tries to address the slower devices. The future you then realizes
> that you need some mechanism the differentiate the old devices without
> the eFuse information and the new which do. You might discover that
> there's some board rev check or something like that can be used. But that's
> only if you are lucky. I hope you see where this is going.
Thanks for the clear explanation. Now I get the point.
> 
> So what can you do?
> A. Go ahead with OPP NOM and be prepared to debug boot failures on
> random boards only to discover that the devices are not meant to operate
> at OPP_NOM.
> 
> B. Find the lowest common denominator for the supported OPPs and use
> that in here. This might end up making some folks unhappy but then you
> need to make a choice between fast and reliable and i would personally go
> for the latter. If folks really care about boot times someone needs to start
> putting the right information in the eFuses at the right time.
> 
>>>
>>>> Since you are very concerned here. Why are you feeling it so complicated when new variants come?
>>>> We can always differentiate the new variant from the old ones and can pass dpll structure accordingly. It is just a matter a one if condition.
>>>> It ll be better to look at the current code and see how cleanly it is done.
>>>>
>>>
>>> As the OPP decoder table in the AM335x datasheet will tell you it's
>>> not that simple.
>> I guess your previous comment was about the code complexity when a new variant of the board comes.
>> Coming to OPP tables:
>> Frankly, I don't know what happened during AM33xx times. I am just trying to make things simpler and cleaner.
>> Do you mean here, we need to support  all OPPs in U-Boot?
>> Are you expecting complete OPP table to get from e-fuse values for AM43xx?
>>
>> As per my understanding from working on OMAP, U-Boot supports only OPP_NOM( or the safe OPP to boot).
>>
>> Please correct me if I am wrong.
>>
> 
> I hope the verbiage above helps you get an idea of why i am insisting on
> a change here.
> 
> I am not asking U-Boot to have the complete OPP table. That's for the kernel
> + device-tree to handle. If there's no eFuse data in the devices, hard luck.
> We do the only thing we can for reliable boots and that's to use an OPP which
> is reliable all the time.
I agree with you, we need to have EEPROM to have the safe OPP.
Unfortunately we don't have this information.
I am sure people will not accept to boot at lowest OPP.

I read more about it and got inputs from Sekhar. I came to know that there is a DEV_ATTRIBUTE register
which tells about the safest OPP to boot with. Looks like this should be sufficient to get the values.
Ill add this code and update the patch.

Thanks and regards,
Lokesh



> 
> If you still think OPP_NOM is the right choice please go ahead and use it.
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Vaibhav Bedia]

On Sun, Dec 1, 2013 at 10:53 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]
> I read more about it and got inputs from Sekhar. I came to know that there is a DEV_ATTRIBUTE register
> which tells about the safest OPP to boot with. Looks like this should be sufficient to get the values.
> Ill add this code and update the patch.

Hmm i don't know how that field gets populated. Unless it's coming
from the eFuse i really doubt
it would serve the purpose.

[U-Boot] [PATCH V2 10/14] ARM: AM43xx: clocks: Update DPLL details for EPOS EVM

[Sekhar Nori]

On 12/4/2013 8:50 AM, Vaibhav Bedia wrote:
> On Sun, Dec 1, 2013 at 10:53 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
>> I read more about it and got inputs from Sekhar. I came to know that there is a DEV_ATTRIBUTE register
>> which tells about the safest OPP to boot with. Looks like this should be sufficient to get the values.
>> Ill add this code and update the patch.
> 
> Hmm i don't know how that field gets populated. Unless it's coming
> from the eFuse i really doubt
> it would serve the purpose.

Yes, that register is a reflection of efuse settings.

Thanks,
Sekhar

[U-Boot] [PATCH V2 11/14] ARM: AM43xx: clocks: Add DPLL data for GP EVM

[Lokesh Vutla]

Adding DPLLs Multiplier and DIvider values for GP EVM
Following are the DPLL locking frequencies at OPP NOM
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 400MHz

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 board/ti/am43xx/board.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 2d1b8f9..366bec3 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -74,16 +74,29 @@ const struct dpll_params epos_evm_dpll_core = {
 const struct dpll_params epos_evm_dpll_per = {
 		960, 24, 5, -1, -1, -1, -1};
 
+const struct dpll_params gp_evm_dpll_ddr = {
+		400, 23, 1, -1, 1, -1, -1};
+const struct dpll_params gp_evm_dpll_mpu = {
+		600, 23, 1, -1, -1, -1, -1};
+const struct dpll_params gp_evm_dpll_core = {
+		1000, 23, -1, -1, 10, 8, 4};
+const struct dpll_params gp_evm_dpll_per = {
+		960, 23, 5, -1, -1, -1, -1};
+
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr;
+	else
+		return &gp_evm_dpll_ddr;
 }
 
 const struct dpll_params *get_dpll_mpu_params(void)
 {
 	if (board_is_eposevm())
 		return &epos_evm_dpll_mpu;
+	else
+		return &gp_evm_dpll_mpu;
 }
 
 const struct dpll_params *get_dpll_core_params(void)
@@ -97,12 +110,16 @@ const struct dpll_params *get_dpll_core_params(void)
 
 	if (board_is_eposevm())
 		return &epos_evm_dpll_core;
+	else
+		return &gp_evm_dpll_core;
 }
 
 const struct dpll_params *get_dpll_per_params(void)
 {
 	if (board_is_eposevm())
 		return &epos_evm_dpll_per;
+	else
+		return &gp_evm_dpll_per;
 }
 
 void set_uart_mux_conf(void)
-- 
1.7.9.5

[U-Boot] [PATCH V2 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Lokesh Vutla]

AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c                    |  147 +++++++++++++++++++-
 arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +++-
 arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
 arch/arm/include/asm/arch-am33xx/cpu.h             |    5 +
 arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   33 ++++-
 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    1 +
 arch/arm/include/asm/emif.h                        |   12 ++
 board/isee/igep0033/board.c                        |   10 +-
 board/phytec/pcm051/board.c                        |   12 +-
 board/siemens/dxr2/board.c                         |   10 +-
 board/siemens/pxm2/board.c                         |   10 +-
 board/siemens/rut/board.c                          |   10 +-
 board/ti/am335x/board.c                            |   40 +++++-
 board/ti/am43xx/board.c                            |   66 +++++++++
 board/ti/ti814x/evm.c                              |    4 +-
 board/ti/ti816x/evm.c                              |   12 +-
 16 files changed, 373 insertions(+), 27 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fa697c7..fbee51d 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -36,6 +36,74 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
 static struct ddr_cmdtctrl *ioctrl_reg = {
 			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
 
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+	u32 mr;
+
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
+		return mr & 0xff;
+	else
+		return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+	mr_addr |= cs << EMIF_REG_CS_SHIFT;
+	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+	u32 mr_addr;
+
+	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+		;
+	set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+	set_mr(nr, cs, LPDDR2_MR1, 0x43);
+	set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+	set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+	writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+	writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
+	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+	writel(regs->emif_rd_wr_lvl_rmp_win,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+	writel(regs->emif_rd_wr_lvl_rmp_ctl,
+	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+	writel(regs->emif_rd_wr_exec_thresh,
+	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+		     EMIF_REG_INITREF_DIS_MASK);
+
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+
+	configure_mr(nr, 0);
+	configure_mr(nr, 1);
+}
+
 /**
  * Configure SDRAM
  */
@@ -72,15 +140,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
+void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+/*
+ * Configure EXT PHY registers
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	const u32 *ext_phy_ctrl_const_regs;
+	u32 i = 0;
+	u32 size;
+
+	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base =
+			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+	/* Configure external phy control timing registers */
+	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+	}
+
+	/*
+	 * external phy 6-24 registers do not change with
+	 * ddr frequency
+	 */
+	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+	if (!size)
+		return;
+
+	for (i = 0; i < size; i++) {
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+		/* Update shadow registers */
+		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+	}
+}
+
 /**
  * Configure DDR PHY
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
+	/*
+	 * disable initialization and refreshes for now until we
+	 * finish programming EMIF regs.
+	 */
+	setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+		     EMIF_REG_INITREF_DIS_MASK);
+
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
 	writel(regs->emif_ddr_phy_ctlr_1,
 		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
+		ext_phy_settings(regs, nr);
 }
 
 /**
@@ -88,6 +208,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
+	if (!cmd)
+		return;
+
 	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
 	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
@@ -108,6 +231,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 {
 	int i;
 
+	if (!data)
+		return;
+
 	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 		writel(data->datardsratio0,
 			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
@@ -128,11 +254,20 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 	}
 }
 
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 {
-	writel(val, &ioctrl_reg->cm0ioctl);
-	writel(val, &ioctrl_reg->cm1ioctl);
-	writel(val, &ioctrl_reg->cm2ioctl);
-	writel(val, &ioctrl_reg->dt0ioctl);
-	writel(val, &ioctrl_reg->dt1ioctl);
+	if (!ioregs)
+		return;
+
+	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+	writel(ioregs->emif_sdram_config_ext,
+	       &ioctrl_reg->emif_sdram_config_ext);
+#endif
 }
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 59ad25c..d28fceb 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = {
 #ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+				(struct cm_device_inst *)CM_DEVICE_INST;
+#endif
 
 #ifdef CONFIG_TI81XX
 void config_dmm(const struct dmm_lisa_map_regs *regs)
@@ -87,7 +92,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
 }
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr)
 {
@@ -99,7 +104,18 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 
 	config_ddr_data(data, nr);
 #ifdef CONFIG_AM33XX
-	config_io_ctrl(ioctrl);
+	config_io_ctrl(ioregs);
+
+	/* Set CKE to be controlled by EMIF/DDR PHY */
+	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+#ifdef CONFIG_AM43XX
+	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+		;
+	writel(0x0, &ddrctrl->ddrioctrl);
+
+	config_io_ctrl(ioregs);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
@@ -108,6 +124,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 	/* Program EMIF instance */
 	config_ddr_phy(regs, nr);
 	set_sdram_timings(regs, nr);
-	config_sdram(regs, nr);
+	if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+		config_sdram_emif4d5(regs, nr);
+	else
+		config_sdram(regs, nr);
 }
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 02ed595..4c9352a 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -28,6 +28,9 @@
 #define UART_CLK_RUNNING_MASK	0x1
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 
+#define CM_DLL_CTRL_NO_OVERRIDE	0x0
+#define CM_DLL_READYST		0x4
+
 extern void enable_dmm_clocks(void);
 extern const struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 19b8469..18d0458 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -401,6 +401,11 @@ struct cm_perpll {
 	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
 };
 
+struct cm_device_inst {
+	unsigned int cm_clkout1_ctrl;
+	unsigned int cm_dll_ctrl;
+};
+
 struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fe48b5f..c98ab7f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -19,7 +19,11 @@
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL	0x3
+#else
 #define DDR_CKE_CTRL_NORMAL	0x1
+#endif
 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
@@ -126,6 +130,14 @@
 #define K4B2G1646EBIH9_PHY_WR_DATA		0x76
 #define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
 
+#define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
+#define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
+
 /**
  * Configure DMM
  */
@@ -135,6 +147,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs);
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
@@ -291,12 +304,27 @@ struct ddr_cmdtctrl {
 	unsigned int resv2[12];
 	unsigned int dt0ioctl;
 	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int resv3[4];
+	unsigned int emif_sdram_config_ext;
+};
+
+struct ctrl_ioregs {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int emif_sdram_config_ext;
 };
 
 /**
  * Configure DDR io control registers
  */
-void config_io_ctrl(unsigned long val);
+void config_io_ctrl(const struct ctrl_ioregs *ioregs);
 
 struct ddr_ctrl {
 	unsigned int ddrioctrl;
@@ -304,8 +332,9 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr);
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 64f9c99..efb7b0d 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -62,5 +62,6 @@
 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
 #define USBPHYOCPSCP_MODULE_EN	(1 << 2)
+#define CM_DEVICE_INST			0x44df4100
 
 #endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 1b94a99..ce6b229 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -14,11 +14,15 @@
 #define _EMIF_H_
 #include <asm/types.h>
 #include <common.h>
+#include <asm/io.h>
 
 /* Base address */
 #define EMIF1_BASE				0x4c000000
 #define EMIF2_BASE				0x4d000000
 
+#define EMIF_4D					0x4
+#define EMIF_4D5				0x5
+
 /* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
@@ -1139,6 +1143,14 @@ struct lpddr2_mr_regs {
 	s8 mr16;
 };
 
+static inline u32 get_emif_rev(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+		>> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c)	({ if (!(c)) for (;;); })
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 0b8356d..2a1b75f 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -81,9 +81,17 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
-	config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+	config_ddr(400, &ioregs, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 034886a..f8e1951 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -96,10 +96,18 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
-	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+	config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, &ddr3_cmd_ctrl_data,
+		   &ddr3_emif_reg_data, 0);
 }
 #endif
 
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f..df26340 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -147,6 +147,14 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 	.cmd1dldiff = 0,
 	.cmd2dldiff = 0,
 };
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= DXR2_IOCTRL_VAL,
+	.cm1ioctl		= DXR2_IOCTRL_VAL,
+	.cm2ioctl		= DXR2_IOCTRL_VAL,
+	.dt0ioctl		= DXR2_IOCTRL_VAL,
+	.dt1ioctl		= DXR2_IOCTRL_VAL,
+};
 	/* pass values from eeprom */
 	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 	dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -168,7 +176,7 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+	config_ddr(DDR_PLL_FREQ, &ioregs, &dxr2_ddr3_data,
 		   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 2c1841f..16aec28 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -74,7 +74,15 @@ struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
 	.cmd2iclkout = 0,
 };
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= DXR2_IOCTRL_VAL,
+	.cm1ioctl		= DXR2_IOCTRL_VAL,
+	.cm2ioctl		= DXR2_IOCTRL_VAL,
+	.dt0ioctl		= DXR2_IOCTRL_VAL,
+	.dt1ioctl		= DXR2_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
 		   &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
 }
 
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 5de8fc6..317350b 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -79,7 +79,15 @@ struct cmd_control rut_ddr3_cmd_ctrl_data = {
 	.cmd2iclkout = 1,
 };
 
-	config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= RUT_IOCTRL_VAL,
+	.cm1ioctl		= RUT_IOCTRL_VAL,
+	.cm2ioctl		= RUT_IOCTRL_VAL,
+	.dt0ioctl		= RUT_IOCTRL_VAL,
+	.dt1ioctl		= RUT_IOCTRL_VAL,
+};
+
+	config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
 		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
 }
 
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 8edd21b..aff2dba 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -443,6 +443,38 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux(&header);
 }
 
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
 void sdram_init(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
@@ -460,18 +492,18 @@ void sdram_init(void)
 	}
 
 	if (board_is_evm_sk(&header))
-		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_bone_lt(&header))
-		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
+		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
 	else if (board_is_evm_15_or_later(&header))
-		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
-		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
+		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 366bec3..10c6a2b 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -15,6 +15,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/emif.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -83,6 +85,69 @@ const struct dpll_params gp_evm_dpll_core = {
 const struct dpll_params gp_evm_dpll_per = {
 		960, 23, 5, -1, -1, -1, -1};
 
+const struct ctrl_ioregs ioregs_lpddr2 = {
+	.cm0ioctl		= LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= LPDDR2_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+	.sdram_config			= 0x808012BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0xEA86B411,
+	.sdram_tim2			= 0x103A094A,
+	.sdram_tim3			= 0x0F6BA37F,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E084006,
+	.emif_rd_wr_exec_thresh		= 0x00000405,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04010040,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00500050,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00500050
+};
+
+const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+	0x00500050,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x40001000,
+	0x08102040
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+	*regs = ext_phy_ctrl_const_base_lpddr2;
+	*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+
+	return;
+}
+
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	if (board_is_eposevm())
@@ -134,6 +199,7 @@ void set_mux_conf_regs(void)
 
 void sdram_init(void)
 {
+	config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 }
 #endif
 
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index e406326..56ec4b2 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -100,9 +100,9 @@ void sdram_init(void)
 {
 	config_dmm(&evm_lisa_map_regs);
 
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif0_regs, 0);
-	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+	config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif1_regs, 1);
 }
 #endif
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 74d35e9..9e7d503 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -206,13 +206,15 @@ void sdram_init(void)
 	if (CONFIG_TI816X_USE_EMIF0) {
 		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+			   0);
 	}
 
 	if (CONFIG_TI816X_USE_EMIF1) {
 		ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+			   1);
 	}
 #endif
 
@@ -220,10 +222,12 @@ void sdram_init(void)
 	ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
 
 	if (CONFIG_TI816X_USE_EMIF0)
-		config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
+		config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+			   0);
 
 	if (CONFIG_TI816X_USE_EMIF1)
-		config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1);
+		config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+			   1);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
-- 
1.7.9.5

[U-Boot] [PATCH V2 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
> Adding LPDDR2 init sequence and register details for the same.
> Below is the brief description of LPDDR2 init sequence:
> -> Configure VTP
> -> Configure DDR IO settings
> -> Disable initialization and refreshes until EMIF registers are programmed.
> -> Program Timing registers
> -> Program PHY control and Temp alert and ZQ config registers.
> -> Enable initialization and refreshes and configure SDRAM CONFIG register
> -> Wait till initialization is complete and the configure MR registers.
>

This patch does too many things, some of which affects AM335x and needs to be
split up. I lost track of what you were doing as i scrolled down :\

> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>  arch/arm/cpu/armv7/am33xx/ddr.c                    |  147 +++++++++++++++++++-
>  arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +++-
>  arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
>  arch/arm/include/asm/arch-am33xx/cpu.h             |    5 +
>  arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   33 ++++-
>  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    1 +
>  arch/arm/include/asm/emif.h                        |   12 ++
>  board/isee/igep0033/board.c                        |   10 +-
>  board/phytec/pcm051/board.c                        |   12 +-
>  board/siemens/dxr2/board.c                         |   10 +-
>  board/siemens/pxm2/board.c                         |   10 +-
>  board/siemens/rut/board.c                          |   10 +-
>  board/ti/am335x/board.c                            |   40 +++++-
>  board/ti/am43xx/board.c                            |   66 +++++++++
>  board/ti/ti814x/evm.c                              |    4 +-
>  board/ti/ti816x/evm.c                              |   12 +-
>  16 files changed, 373 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
> index fa697c7..fbee51d 100644
> --- a/arch/arm/cpu/armv7/am33xx/ddr.c
> +++ b/arch/arm/cpu/armv7/am33xx/ddr.c
> @@ -36,6 +36,74 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
>  static struct ddr_cmdtctrl *ioctrl_reg = {
>                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
>
> +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
> +{
> +       u32 mr;
> +
> +       mr_addr |= cs << EMIF_REG_CS_SHIFT;
> +       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
> +
> +       mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
> +       debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
> +       if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
> +           ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
> +           ((mr & 0xff000000) >> 24) == (mr & 0xff))
> +               return mr & 0xff;
> +       else
> +               return mr;
> +}
> +
> +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
> +{
> +       mr_addr |= cs << EMIF_REG_CS_SHIFT;
> +       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
> +       writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
> +}
> +
> +static void configure_mr(int nr, u32 cs)
> +{
> +       u32 mr_addr;
> +
> +       while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
> +               ;
> +       set_mr(nr, cs, LPDDR2_MR10, 0x56);
> +
> +       set_mr(nr, cs, LPDDR2_MR1, 0x43);
> +       set_mr(nr, cs, LPDDR2_MR2, 0x2);
> +
> +       mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
> +       set_mr(nr, cs, mr_addr, 0x2);
> +}
> +
> +/*
> + * Configure EMIF4D5 registers and MR registers
> + */
> +void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
> +{
> +       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
> +       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
> +       writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
> +       writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
> +
> +       writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
> +       writel(regs->emif_rd_wr_lvl_rmp_win,
> +              &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
> +       writel(regs->emif_rd_wr_lvl_rmp_ctl,
> +              &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
> +       writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
> +       writel(regs->emif_rd_wr_exec_thresh,
> +              &emif_reg[nr]->emif_rd_wr_exec_thresh);
> +
> +       clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
> +                    EMIF_REG_INITREF_DIS_MASK);
> +
> +       writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
> +       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
> +
> +       configure_mr(nr, 0);
> +       configure_mr(nr, 1);
> +}
> +

Why can't this portion be shared with the other OMAPs? It looks to be
following a recommended sequence and i can't see why that would vary.

It's just too hard to review so many changes in a single patch so i'll stop
here, sorry.

[U-Boot] [PATCH V2 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Lokesh Vutla]

On Friday 22 November 2013 02:16 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>> Adding LPDDR2 init sequence and register details for the same.
>> Below is the brief description of LPDDR2 init sequence:
>> -> Configure VTP
>> -> Configure DDR IO settings
>> -> Disable initialization and refreshes until EMIF registers are programmed.
>> -> Program Timing registers
>> -> Program PHY control and Temp alert and ZQ config registers.
>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>> -> Wait till initialization is complete and the configure MR registers.
>>
> 
> This patch does too many things, some of which affects AM335x and needs to be
> split up. I lost track of what you were doing as i scrolled down :\
It does only two things. Update IO settings and emif configuration.
I wanted to keep these things in a single patch so that if some functionality
breaks down I can burn down to this patch.
> 
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>>  arch/arm/cpu/armv7/am33xx/ddr.c                    |  147 +++++++++++++++++++-
>>  arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +++-
>>  arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
>>  arch/arm/include/asm/arch-am33xx/cpu.h             |    5 +
>>  arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   33 ++++-
>>  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    1 +
>>  arch/arm/include/asm/emif.h                        |   12 ++
>>  board/isee/igep0033/board.c                        |   10 +-
>>  board/phytec/pcm051/board.c                        |   12 +-
>>  board/siemens/dxr2/board.c                         |   10 +-
>>  board/siemens/pxm2/board.c                         |   10 +-
>>  board/siemens/rut/board.c                          |   10 +-
>>  board/ti/am335x/board.c                            |   40 +++++-
>>  board/ti/am43xx/board.c                            |   66 +++++++++
>>  board/ti/ti814x/evm.c                              |    4 +-
>>  board/ti/ti816x/evm.c                              |   12 +-
>>  16 files changed, 373 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
>> index fa697c7..fbee51d 100644
>> --- a/arch/arm/cpu/armv7/am33xx/ddr.c
>> +++ b/arch/arm/cpu/armv7/am33xx/ddr.c
>> @@ -36,6 +36,74 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
>>  static struct ddr_cmdtctrl *ioctrl_reg = {
>>                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
>>
>> +static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
>> +{
>> +       u32 mr;
>> +
>> +       mr_addr |= cs << EMIF_REG_CS_SHIFT;
>> +       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
>> +
>> +       mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
>> +       debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
>> +       if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
>> +           ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
>> +           ((mr & 0xff000000) >> 24) == (mr & 0xff))
>> +               return mr & 0xff;
>> +       else
>> +               return mr;
>> +}
>> +
>> +static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
>> +{
>> +       mr_addr |= cs << EMIF_REG_CS_SHIFT;
>> +       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
>> +       writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
>> +}
>> +
>> +static void configure_mr(int nr, u32 cs)
>> +{
>> +       u32 mr_addr;
>> +
>> +       while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
>> +               ;
>> +       set_mr(nr, cs, LPDDR2_MR10, 0x56);
>> +
>> +       set_mr(nr, cs, LPDDR2_MR1, 0x43);
>> +       set_mr(nr, cs, LPDDR2_MR2, 0x2);
>> +
>> +       mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
>> +       set_mr(nr, cs, mr_addr, 0x2);
>> +}
>> +
>> +/*
>> + * Configure EMIF4D5 registers and MR registers
>> + */
>> +void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
>> +{
>> +       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
>> +       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
>> +       writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
>> +       writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
>> +
>> +       writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
>> +       writel(regs->emif_rd_wr_lvl_rmp_win,
>> +              &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
>> +       writel(regs->emif_rd_wr_lvl_rmp_ctl,
>> +              &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
>> +       writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
>> +       writel(regs->emif_rd_wr_exec_thresh,
>> +              &emif_reg[nr]->emif_rd_wr_exec_thresh);
>> +
>> +       clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
>> +                    EMIF_REG_INITREF_DIS_MASK);
>> +
>> +       writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
>> +       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
>> +
>> +       configure_mr(nr, 0);
>> +       configure_mr(nr, 1);
>> +}
>> +
> 
> Why can't this portion be shared with the other OMAPs? It looks to be
> following a recommended sequence and i can't see why that would vary.
Yes, my ultimate goal is to have a single emif file, but with the current position
of emif file for OMAP's I can't reuse. 
This is in my To do list. I have already discussed this with Tom

Thanks
Lokesh
> 
> It's just too hard to review so many changes in a single patch so i'll stop
> here, sorry.
> 

[U-Boot] [PATCH V2 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Vaibhav Bedia]

On Mon, Nov 25, 2013 at 12:13 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 02:16 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>>> Adding LPDDR2 init sequence and register details for the same.
>>> Below is the brief description of LPDDR2 init sequence:
>>> -> Configure VTP
>>> -> Configure DDR IO settings
>>> -> Disable initialization and refreshes until EMIF registers are programmed.
>>> -> Program Timing registers
>>> -> Program PHY control and Temp alert and ZQ config registers.
>>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>>> -> Wait till initialization is complete and the configure MR registers.
>>>
>>
>> This patch does too many things, some of which affects AM335x and needs to be
>> split up. I lost track of what you were doing as i scrolled down :\
> It does only two things. Update IO settings and emif configuration.
> I wanted to keep these things in a single patch so that if some functionality
> breaks down I can burn down to this patch.

That doesn't mean that you mix up everything in one humungous patch and
try to force your way through.

>>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> ---
>>>  arch/arm/cpu/armv7/am33xx/ddr.c                    |  147 +++++++++++++++++++-
>>>  arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +++-
>>>  arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
>>>  arch/arm/include/asm/arch-am33xx/cpu.h             |    5 +
>>>  arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   33 ++++-
>>>  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    1 +
>>>  arch/arm/include/asm/emif.h                        |   12 ++
>>>  board/isee/igep0033/board.c                        |   10 +-
>>>  board/phytec/pcm051/board.c                        |   12 +-
>>>  board/siemens/dxr2/board.c                         |   10 +-
>>>  board/siemens/pxm2/board.c                         |   10 +-
>>>  board/siemens/rut/board.c                          |   10 +-
>>>  board/ti/am335x/board.c                            |   40 +++++-
>>>  board/ti/am43xx/board.c                            |   66 +++++++++
>>>  board/ti/ti814x/evm.c                              |    4 +-
>>>  board/ti/ti816x/evm.c                              |   12 +-
>>>  16 files changed, 373 insertions(+), 27 deletions(-)

As the diffstat above shows, this patch affects a critical portion of AM335x,
TI81xx and and at the same time adds in support for a new SoC. If that's not
mixing up things i honestly don't know what is.

And if you have some discussions off-list you should at least attempt to capture
the summary of what was agreed to do taken up as TODO for the benefit of
others. If there's a agreed upon patch to improving the code that helps is
overlooking some short term compromises.

[U-Boot] [PATCH V2 12/14] ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

[Lokesh Vutla]

On Wednesday 27 November 2013 05:42 AM, Vaibhav Bedia wrote:
> On Mon, Nov 25, 2013 at 12:13 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> On Friday 22 November 2013 02:16 AM, Vaibhav Bedia wrote:
>>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>>>> Adding LPDDR2 init sequence and register details for the same.
>>>> Below is the brief description of LPDDR2 init sequence:
>>>> -> Configure VTP
>>>> -> Configure DDR IO settings
>>>> -> Disable initialization and refreshes until EMIF registers are programmed.
>>>> -> Program Timing registers
>>>> -> Program PHY control and Temp alert and ZQ config registers.
>>>> -> Enable initialization and refreshes and configure SDRAM CONFIG register
>>>> -> Wait till initialization is complete and the configure MR registers.
>>>>
>>>
>>> This patch does too many things, some of which affects AM335x and needs to be
>>> split up. I lost track of what you were doing as i scrolled down :\
>> It does only two things. Update IO settings and emif configuration.
>> I wanted to keep these things in a single patch so that if some functionality
>> breaks down I can burn down to this patch.
> 
> That doesn't mean that you mix up everything in one humungous patch and
> try to force your way through.
OK, Ill separate out EMIF configuration and io settings and repost.
 
Thanks
Lokesh
> 
>>>
>>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>>> ---
>>>>  arch/arm/cpu/armv7/am33xx/ddr.c                    |  147 +++++++++++++++++++-
>>>>  arch/arm/cpu/armv7/am33xx/emif4.c                  |   25 +++-
>>>>  arch/arm/include/asm/arch-am33xx/clocks_am33xx.h   |    3 +
>>>>  arch/arm/include/asm/arch-am33xx/cpu.h             |    5 +
>>>>  arch/arm/include/asm/arch-am33xx/ddr_defs.h        |   33 ++++-
>>>>  arch/arm/include/asm/arch-am33xx/hardware_am43xx.h |    1 +
>>>>  arch/arm/include/asm/emif.h                        |   12 ++
>>>>  board/isee/igep0033/board.c                        |   10 +-
>>>>  board/phytec/pcm051/board.c                        |   12 +-
>>>>  board/siemens/dxr2/board.c                         |   10 +-
>>>>  board/siemens/pxm2/board.c                         |   10 +-
>>>>  board/siemens/rut/board.c                          |   10 +-
>>>>  board/ti/am335x/board.c                            |   40 +++++-
>>>>  board/ti/am43xx/board.c                            |   66 +++++++++
>>>>  board/ti/ti814x/evm.c                              |    4 +-
>>>>  board/ti/ti816x/evm.c                              |   12 +-
>>>>  16 files changed, 373 insertions(+), 27 deletions(-)
> 
> As the diffstat above shows, this patch affects a critical portion of AM335x,
> TI81xx and and at the same time adds in support for a new SoC. If that's not
> mixing up things i honestly don't know what is.
> 
> And if you have some discussions off-list you should at least attempt to capture
> the summary of what was agreed to do taken up as TODO for the benefit of
> others. If there's a agreed upon patch to improving the code that helps is
> overlooking some short term compromises.
> 

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Lokesh Vutla]

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c              |    6 +-
 arch/arm/cpu/armv7/omap-common/emif-common.c |   14 ----
 arch/arm/include/asm/arch-am33xx/ddr_defs.h  |    8 +++
 arch/arm/include/asm/emif.h                  |   14 ++++
 board/ti/am43xx/board.c                      |   92 +++++++++++++++++++++++++-
 board/ti/am43xx/mux.c                        |    8 +++
 6 files changed, 123 insertions(+), 19 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fbee51d..389fdfc 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -100,8 +100,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 
-	configure_mr(nr, 0);
-	configure_mr(nr, 1);
+	if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+		configure_mr(nr, 0);
+		configure_mr(nr, 1);
+	}
 }
 
 /**
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index b0e1caa..d8a15be 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
 		return 0;
 }
 
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
-	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-	return (readl(&emif->emif_sdram_config) &
-		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 {
 	u32 mr;
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index c98ab7f..646e50f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -138,6 +138,14 @@
 #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
 
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
 /**
  * Configure DMM
  */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index ce6b229..b4a8c9f 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
 		>> EMIF_REG_MAJOR_REVISION_SHIFT;
 }
 
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(void)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+	return (readl(&emif->emif_sdram_config) &
+		EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c)	({ if (!(c)) for (;;); })
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 10c6a2b..e3a94ad 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -16,6 +16,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
 #include <asm/emif.h>
 #include "board.h"
 
@@ -140,10 +141,70 @@ const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 	0x08102040
 };
 
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl		= DDR3_ADDRCTRL_IOCTRL_VALUE,
+	.cm1ioctl		= DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+	.cm2ioctl		= DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+	.dt0ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt1ioctl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt2ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.dt3ioctrl		= DDR3_DATA0_IOCTRL_VALUE,
+	.emif_sdram_config_ext	= 0x0043,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+	.sdram_config			= 0x638413B2,
+	.ref_ctrl			= 0x00000C30,
+	.sdram_tim1			= 0xEAAAD4DB,
+	.sdram_tim2			= 0x266B7FDA,
+	.sdram_tim3			= 0x107F8678,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x50074BE4,
+	.temp_alert_config		= 0x0,
+	.emif_ddr_phy_ctlr_1		= 0x0E084008,
+	.emif_ddr_ext_phy_ctrl_1	= 0x08020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_3	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_4	= 0x00400040,
+	.emif_ddr_ext_phy_ctrl_5	= 0x00400040,
+	.emif_rd_wr_lvl_rmp_win		= 0x0,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x0,
+	.emif_rd_wr_lvl_ctl		= 0x0,
+	.emif_rd_wr_exec_thresh		= 0x00000405
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+	0x00400040,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00350035,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x00340034,
+	0x0,
+	0x0,
+	0x40000000,
+	0x08102040
+};
+
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 {
-	*regs = ext_phy_ctrl_const_base_lpddr2;
-	*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	if (board_is_eposevm()) {
+		*regs = ext_phy_ctrl_const_base_lpddr2;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+	} else if (board_is_gpevm()) {
+		*regs = ext_phy_ctrl_const_base_ddr3;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+	}
 
 	return;
 }
@@ -197,9 +258,34 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
+static void enable_vtt_regulator(void)
+{
+	u32 temp;
+
+	/* enable module */
+	writel(0x0, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
+
+	/*enable output for GPIO0_22*/
+	writel((1 << 22), AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
+	temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+	temp = temp & ~(1 << 22);
+	writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
+}
+
 void sdram_init(void)
 {
-	config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+	/*
+	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+	 * GP EMV has 1GB DDR3 connected to EMIF
+	 * along with VTT regulator.
+	 */
+	if (board_is_eposevm()) {
+		config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+	} else if (board_is_gpevm()) {
+		enable_vtt_regulator();
+		config_ddr(0, &ioregs_ddr3, NULL, NULL,
+			   &ddr3_emif_regs_400Mhz, 0);
+	}
 }
 #endif
 
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index a2d72dd..810b194 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -33,6 +33,11 @@ static struct module_pin_mux i2c0_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux gpio0_22_pin_mux[] = {
+	{OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)},	/* GPIO0_22 */
+	{-1},
+};
+
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
@@ -42,6 +47,9 @@ void enable_board_pin_mux(void)
 {
 	configure_module_pin_mux(mmc0_pin_mux);
 	configure_module_pin_mux(i2c0_pin_mux);
+
+	if (board_is_gpevm())
+		configure_module_pin_mux(gpio0_22_pin_mux);
 }
 
 void enable_i2c0_pin_mux(void)
-- 
1.7.9.5

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Vaibhav Bedia]

On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]

> -/*
> - * Get SDRAM type connected to EMIF.
> - * Assuming similar SDRAM parts are connected to both EMIF's
> - * which is typically the case. So it is sufficient to get
> - * SDRAM type from EMIF1.
> - */
> -u32 emif_sdram_type()
> -{
> -       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
> -
> -       return (readl(&emif->emif_sdram_config) &
> -               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
> -}
> -
>  static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
>  {
>         u32 mr;
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> index c98ab7f..646e50f 100644
> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> @@ -138,6 +138,14 @@
>  #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
>  #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
>
> +#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
> +#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
> +#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
> +#define  DDR3_DATA0_IOCTRL_VALUE   0x84
> +#define  DDR3_DATA1_IOCTRL_VALUE   0x84
> +#define  DDR3_DATA2_IOCTRL_VALUE   0x84
> +#define  DDR3_DATA3_IOCTRL_VALUE   0x84
> +
>  /**
>   * Configure DMM
>   */
> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
> index ce6b229..b4a8c9f 100644
> --- a/arch/arm/include/asm/emif.h
> +++ b/arch/arm/include/asm/emif.h
> @@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
>                 >> EMIF_REG_MAJOR_REVISION_SHIFT;
>  }
>
> +/*
> + * Get SDRAM type connected to EMIF.
> + * Assuming similar SDRAM parts are connected to both EMIF's
> + * which is typically the case. So it is sufficient to get
> + * SDRAM type from EMIF1.
> + */
> +static inline u32 emif_sdram_type(void)
> +{
> +       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
> +
> +       return (readl(&emif->emif_sdram_config) &
> +               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
> +}
> +

This change don't make any sense to me. How are the EMIF register bits
any indication
of what memory time is used especially for DDR2/3?

[...]
>
> +static void enable_vtt_regulator(void)
> +{
> +       u32 temp;
> +
> +       /* enable module */
> +       writel(0x0, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
> +
> +       /*enable output for GPIO0_22*/
> +       writel((1 << 22), AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
> +       temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
> +       temp = temp & ~(1 << 22);
> +       writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
> +}
> +

No magic nos. please. I think you have a #def the pin used for VTT regulator
in the config file - makes it simpler for others who design their own board.

Regards,
Vaibhav

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Lokesh Vutla]

On Friday 22 November 2013 02:22 AM, Vaibhav Bedia wrote:
> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
> 
>> -/*
>> - * Get SDRAM type connected to EMIF.
>> - * Assuming similar SDRAM parts are connected to both EMIF's
>> - * which is typically the case. So it is sufficient to get
>> - * SDRAM type from EMIF1.
>> - */
>> -u32 emif_sdram_type()
>> -{
>> -       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>> -
>> -       return (readl(&emif->emif_sdram_config) &
>> -               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>> -}
>> -
>>  static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
>>  {
>>         u32 mr;
>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> index c98ab7f..646e50f 100644
>> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>> @@ -138,6 +138,14 @@
>>  #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
>>  #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
>>
>> +#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
>> +#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
>> +#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
>> +#define  DDR3_DATA0_IOCTRL_VALUE   0x84
>> +#define  DDR3_DATA1_IOCTRL_VALUE   0x84
>> +#define  DDR3_DATA2_IOCTRL_VALUE   0x84
>> +#define  DDR3_DATA3_IOCTRL_VALUE   0x84
>> +
>>  /**
>>   * Configure DMM
>>   */
>> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
>> index ce6b229..b4a8c9f 100644
>> --- a/arch/arm/include/asm/emif.h
>> +++ b/arch/arm/include/asm/emif.h
>> @@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
>>                 >> EMIF_REG_MAJOR_REVISION_SHIFT;
>>  }
>>
>> +/*
>> + * Get SDRAM type connected to EMIF.
>> + * Assuming similar SDRAM parts are connected to both EMIF's
>> + * which is typically the case. So it is sufficient to get
>> + * SDRAM type from EMIF1.
>> + */
>> +static inline u32 emif_sdram_type(void)
>> +{
>> +       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>> +
>> +       return (readl(&emif->emif_sdram_config) &
>> +               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>> +}
>> +
> 
> This change don't make any sense to me. How are the EMIF register bits
> any indication
> of what memory time is used especially for DDR2/3?
What is not making sense here ?
If you go and read EMIF spec, it is clearly written that on coming out of reset 
HW sequence starts according to the value populated in SDRAM config register.
As far as I am concerned this is the best way to differentiate between Memories.

Can you tell me a better way to differentiate between memories in emif file ?
Definitely  I should not use board_is_foo() functions.

Thanks
Lokesh
> 
> [...]
>>
>> +static void enable_vtt_regulator(void)
>> +{
>> +       u32 temp;
>> +
>> +       /* enable module */
>> +       writel(0x0, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
>> +
>> +       /*enable output for GPIO0_22*/
>> +       writel((1 << 22), AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
>> +       temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
>> +       temp = temp & ~(1 << 22);
>> +       writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
>> +}
>> +
> 
> No magic nos. please. I think you have a #def the pin used for VTT regulator
> in the config file - makes it simpler for others who design their own board.
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Vaibhav Bedia]

On Mon, Nov 25, 2013 at 12:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> On Friday 22 November 2013 02:22 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> [...]
>>
>>> -/*
>>> - * Get SDRAM type connected to EMIF.
>>> - * Assuming similar SDRAM parts are connected to both EMIF's
>>> - * which is typically the case. So it is sufficient to get
>>> - * SDRAM type from EMIF1.
>>> - */
>>> -u32 emif_sdram_type()
>>> -{
>>> -       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>> -
>>> -       return (readl(&emif->emif_sdram_config) &
>>> -               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>>> -}
>>> -
>>>  static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
>>>  {
>>>         u32 mr;
>>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> index c98ab7f..646e50f 100644
>>> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>> @@ -138,6 +138,14 @@
>>>  #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
>>>  #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
>>>
>>> +#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
>>> +#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
>>> +#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
>>> +#define  DDR3_DATA0_IOCTRL_VALUE   0x84
>>> +#define  DDR3_DATA1_IOCTRL_VALUE   0x84
>>> +#define  DDR3_DATA2_IOCTRL_VALUE   0x84
>>> +#define  DDR3_DATA3_IOCTRL_VALUE   0x84
>>> +
>>>  /**
>>>   * Configure DMM
>>>   */
>>> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
>>> index ce6b229..b4a8c9f 100644
>>> --- a/arch/arm/include/asm/emif.h
>>> +++ b/arch/arm/include/asm/emif.h
>>> @@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
>>>                 >> EMIF_REG_MAJOR_REVISION_SHIFT;
>>>  }
>>>
>>> +/*
>>> + * Get SDRAM type connected to EMIF.
>>> + * Assuming similar SDRAM parts are connected to both EMIF's
>>> + * which is typically the case. So it is sufficient to get
>>> + * SDRAM type from EMIF1.
>>> + */
>>> +static inline u32 emif_sdram_type(void)
>>> +{
>>> +       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>> +
>>> +       return (readl(&emif->emif_sdram_config) &
>>> +               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>>> +}
>>> +
>>
>> This change don't make any sense to me. How are the EMIF register bits
>> any indication
>> of what memory time is used especially for DDR2/3?
> What is not making sense here ?
> If you go and read EMIF spec, it is clearly written that on coming out of reset
> HW sequence starts according to the value populated in SDRAM config register.
> As far as I am concerned this is the best way to differentiate between Memories.
>

Take a moment to think about where that register value comes from. Does it
somehow automagically get reconfigured when the chip is put in a board with
LPDDR2 vs DDR2 vs DDR3? While you are at it also look at the JEDEC specs
to figure out is there's some way to probe the DDR2/3 memory types.

> Can you tell me a better way to differentiate between memories in emif file ?
> Definitely  I should not use board_is_foo() functions.
>

AFAIK there is none and hence this way of trying to get the memory type
is broken.

Moreover, my understanding was that one of the prime functions of the EEPROM
board data was to enable differentiation between the memory types.

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Lokesh Vutla]

On Wednesday 27 November 2013 05:47 AM, Vaibhav Bedia wrote:
> On Mon, Nov 25, 2013 at 12:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>> On Friday 22 November 2013 02:22 AM, Vaibhav Bedia wrote:
>>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
>>> [...]
>>>
>>>> -/*
>>>> - * Get SDRAM type connected to EMIF.
>>>> - * Assuming similar SDRAM parts are connected to both EMIF's
>>>> - * which is typically the case. So it is sufficient to get
>>>> - * SDRAM type from EMIF1.
>>>> - */
>>>> -u32 emif_sdram_type()
>>>> -{
>>>> -       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>>> -
>>>> -       return (readl(&emif->emif_sdram_config) &
>>>> -               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>>>> -}
>>>> -
>>>>  static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
>>>>  {
>>>>         u32 mr;
>>>> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>>> index c98ab7f..646e50f 100644
>>>> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>>> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
>>>> @@ -138,6 +138,14 @@
>>>>  #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
>>>>  #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
>>>>
>>>> +#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
>>>> +#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
>>>> +#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
>>>> +#define  DDR3_DATA0_IOCTRL_VALUE   0x84
>>>> +#define  DDR3_DATA1_IOCTRL_VALUE   0x84
>>>> +#define  DDR3_DATA2_IOCTRL_VALUE   0x84
>>>> +#define  DDR3_DATA3_IOCTRL_VALUE   0x84
>>>> +
>>>>  /**
>>>>   * Configure DMM
>>>>   */
>>>> diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
>>>> index ce6b229..b4a8c9f 100644
>>>> --- a/arch/arm/include/asm/emif.h
>>>> +++ b/arch/arm/include/asm/emif.h
>>>> @@ -1151,6 +1151,20 @@ static inline u32 get_emif_rev(u32 base)
>>>>                 >> EMIF_REG_MAJOR_REVISION_SHIFT;
>>>>  }
>>>>
>>>> +/*
>>>> + * Get SDRAM type connected to EMIF.
>>>> + * Assuming similar SDRAM parts are connected to both EMIF's
>>>> + * which is typically the case. So it is sufficient to get
>>>> + * SDRAM type from EMIF1.
>>>> + */
>>>> +static inline u32 emif_sdram_type(void)
>>>> +{
>>>> +       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
>>>> +
>>>> +       return (readl(&emif->emif_sdram_config) &
>>>> +               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
>>>> +}
>>>> +
>>>
>>> This change don't make any sense to me. How are the EMIF register bits
>>> any indication
>>> of what memory time is used especially for DDR2/3?
>> What is not making sense here ?
>> If you go and read EMIF spec, it is clearly written that on coming out of reset
>> HW sequence starts according to the value populated in SDRAM config register.
>> As far as I am concerned this is the best way to differentiate between Memories.
>>
> 
> Take a moment to think about where that register value comes from. Does it
> somehow automagically get reconfigured when the chip is put in a board with
> LPDDR2 vs DDR2 vs DDR3? While you are at it also look at the JEDEC specs
> to figure out is there's some way to probe the DDR2/3 memory types.
Ideally the default value should be exported from e-fuse values.
EMIF does some HW sequence according to the value exported here. This filed tells 
what type of memory it is.

I understand the point what if efuse is not blown. I am using this only after we write into sdarm_config register.
This can confirm that we get a correct value.
 If this is not sufficient we can hardcode the register during startup only ?
One more thing is we can get from MR registers of DDR.
But for DDR3 we cannot access MR registers. That is why I didn't go with this approach.

Currently EEPROM doesn't have any details about DDR.
Please let me know if this approach is not good enough.

Thanks and regards,
Lokesh

> 
>> Can you tell me a better way to differentiate between memories in emif file ?
>> Definitely  I should not use board_is_foo() functions.
>>
> 
> AFAIK there is none and hence this way of trying to get the memory type
> is broken.
> 
> Moreover, my understanding was that one of the prime functions of the EEPROM
> board data was to enable differentiation between the memory types.
> 

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Vaibhav Bedia]

On Wed, Nov 27, 2013 at 4:34 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
[...]
> Ideally the default value should be exported from e-fuse values.
> EMIF does some HW sequence according to the value exported here. This filed tells
> what type of memory it is.
>

No, eFuse is not the right place for this information. If you were to do that
you would be restricting what memory type is supported on a particular
device that gets shipped and that's not a scalable model.

> I understand the point what if efuse is not blown. I am using this only after we write into sdarm_config register.
> This can confirm that we get a correct value.
>  If this is not sufficient we can hardcode the register during startup only ?

I don't see any value in writing some value in the EMIF register at one place
and then using that here. If you already know what register values to program
you already know the memory type.

Another place where the memory type information is needed is when the device
enters low power state and the EMIF contents are lost. Rather than having to
invent one more way of detecting the memory type in resume from low power state
you could work out a persistent storage area (RTC scratchpad maybe? assuming
the RTC is powered up) and use that in all the places. Requires some thought
about the whole sequence but definitely doable IMHO.

> One more thing is we can get from MR registers of DDR.
> But for DDR3 we cannot access MR registers. That is why I didn't go with this approach.
>

So now you know why things just worked on OMAP3 (and OMAP4?) and not
on TI81xx, AM335x and AM437x :)

> Currently EEPROM doesn't have any details about DDR.
> Please let me know if this approach is not good enough.
>

Since there's no speced way of detecting the memory type you should push for
the right information to be made available via the EEPROM and write
generic code.
But hey that's for you to decide :)

Regards,
Vaibhav

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Lokesh Vutla]

On Thursday 28 November 2013 04:33 AM, Vaibhav Bedia wrote:
> On Wed, Nov 27, 2013 at 4:34 AM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
> [...]
>> Ideally the default value should be exported from e-fuse values.
>> EMIF does some HW sequence according to the value exported here. This filed tells
>> what type of memory it is.
>>
> 
> No, eFuse is not the right place for this information. If you were to do that
> you would be restricting what memory type is supported on a particular
> device that gets shipped and that's not a scalable model.
At least this was the case for OMAPs. So it worked well..:)
> 
>> I understand the point what if efuse is not blown. I am using this only after we write into sdarm_config register.
>> This can confirm that we get a correct value.
>>  If this is not sufficient we can hardcode the register during startup only ?
> 
> I don't see any value in writing some value in the EMIF register at one place
> and then using that here. If you already know what register values to program
> you already know the memory type.
Yes, according to the board we are passing the registers that means we know
the memory type. The same information I am getting from registers.
> 
> Another place where the memory type information is needed is when the device
> enters low power state and the EMIF contents are lost. Rather than having to
> invent one more way of detecting the memory type in resume from low power state
> you could work out a persistent storage area (RTC scratchpad maybe? assuming
> the RTC is powered up) and use that in all the places. Requires some thought
> about the whole sequence but definitely doable IMHO.
We should not rely on RTC here. I don't think U-Boot should worry about low power state. You mean to
say about passing this information to kernel?
In the current kernel also memory type is derived according to the SDRAM CONFIG register only.
So I thought this would be good enough.


Thanks and regards,
Lokesh

> 
>> One more thing is we can get from MR registers of DDR.
>> But for DDR3 we cannot access MR registers. That is why I didn't go with this approach.
>>
> 
> So now you know why things just worked on OMAP3 (and OMAP4?) and not
> on TI81xx, AM335x and AM437x :)
> 
>> Currently EEPROM doesn't have any details about DDR.
>> Please let me know if this approach is not good enough.
>>
> 
> Since there's no speced way of detecting the memory type you should push for
> the right information to be made available via the EEPROM and write
> generic code.
> But hey that's for you to decide :)
> 
> Regards,
> Vaibhav
> 

[U-Boot] [PATCH V2 13/14] ARM: AM43xx: GP_EVM: Add support for DDR3

[Vaibhav Bedia]

On Sun, Dec 1, 2013 at 11:21 PM, Lokesh Vutla <lokeshvutla@ti.com> wrote:
][...]
> We should not rely on RTC here. I don't think U-Boot should worry about low power state. You mean to
> say about passing this information to kernel?

No. I am not asking you to pass this to the kernel.

> In the current kernel also memory type is derived according to the SDRAM CONFIG register only.
> So I thought this would be good enough.
>

The only problem with this being that register is also lost when you
go lower than DeepSleep
and would require you to figure out how to get the memory type.

Your call though. I guess i am just trying to over-engineer things ;)

[U-Boot] [PATCH V2 14/14] ARM: AM43xx: Add Maintainer

[Lokesh Vutla]

Adding Maintainer for AM43xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 boards.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/boards.cfg b/boards.cfg
index e742746..7cd19f7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -263,7 +263,7 @@ Active  arm         armv7          am33xx      ti              am335x
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                    am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   -
+Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   Lokesh Vutla <lokeshvutla@ti.com>
 Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <mporter@ti.com>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                           -                                                                                                                                 -
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_mmc                       sama5d3xek:SAMA5D3,SYS_USE_MMC                                                                                                    Bo Shen <voice.shen@atmel.com>
-- 
1.7.9.5