[PATCH v3 00/13] xen: arm initial support for xgene arm64 platform

[PATCH v3 00/13] xen: arm initial support for xgene arm64 platform

[Ian Campbell]

George has release acked all of these. Otherwise mostly minor updates
this time around.

Summary: A == acked, M == modified

A   xen: arm64: Add 8250 earlyprintk support
A   xen: arm64: Add Basic Platform support for APM X-Gene Storm.
A   xen: arm64: Add APM implementor id to processor implementers.
 M  xen: arm: add a quirk to handle platforms with unusual GIC layout
A   xen: arm: allow platform code to select dom0 event channel irq
A   xen: arm64: Map xgene PCI memory regions and interrupts to dom0.
A   xen: arm: include ns16550 driver on arm64 too
 M  xen: arm: Handle cpus nodes with #address-cells > 1
A   xen: arm: Make register bit definitions unsigned.
A   xen: arm: explicitly map 64 bit release address
    xen: arm: enable synchronous console while starting secondary CPUs
A   xen: arm: improve early memory map readability
    xen: arm: handle 40-bit addresses in the p2m

[PATCH v3 01/13] xen: arm64: Add 8250 earlyprintk support

[Ian Campbell]

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Extracted from "Basic Platform support for APM X-Gene Storm."

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Reworked into generic 8250 driver, use EARLY_UART_REG_SHIFT.

While there observe a missing shift in the arm32 version (UART_THR is zero so
it doesn't really matter). Changed for consistency.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v2: Drop unused early_uart_init macro
---
 xen/arch/arm/Rules.mk             |    6 +++++
 xen/arch/arm/arm64/debug-8250.inc |   45 +++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 xen/arch/arm/arm64/debug-8250.inc

diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index c27c2eb..aaa203e 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -82,6 +82,12 @@ EARLY_PRINTK_INC := 8250
 EARLY_UART_BASE_ADDRESS := 0xF0406B00
 EARLY_UART_REG_SHIFT := 2
 endif
+ifeq ($(CONFIG_EARLY_PRINTK), xgene-storm)
+EARLY_PRINTK_INC := 8250
+EARLY_PRINTK_BAUD := 115200
+EARLY_UART_BASE_ADDRESS := 0x1c020000
+EARLY_UART_REG_SHIFT := 2
+endif
 
 ifneq ($(EARLY_PRINTK_INC),)
 EARLY_PRINTK := y
diff --git a/xen/arch/arm/arm64/debug-8250.inc b/xen/arch/arm/arm64/debug-8250.inc
new file mode 100644
index 0000000..158549a
--- /dev/null
+++ b/xen/arch/arm/arm64/debug-8250.inc
@@ -0,0 +1,45 @@
+/*
+ * xen/arch/arm/arm64/debug-8250.inc
+ *
+ * 8250 specific debug code
+ *
+ * Copyright (c) 2013 Applied Micro.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/8250-uart.h>
+
+/* UART wait UART to be ready to transmit
+ * xb: register which contains the UART base address
+ * c: scratch register */
+.macro early_uart_ready xb c
+1:
+       ldrb  w\c, [\xb, #UART_LSR << EARLY_UART_REG_SHIFT]
+       and w\c, w\c, #UART_LSR_THRE
+       cmp w\c, #UART_LSR_THRE
+       b.ne 1b
+.endm
+
+/* UART transmit character
+ * xb: register which contains the UART base address
+ * wt: register which contains the character to transmit */
+.macro early_uart_transmit xb wt
+        /* UART_THR  transmit holding */
+        strb   \wt, [\xb, #UART_THR << EARLY_UART_REG_SHIFT]
+.endm
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
1.7.10.4

Re: [PATCH v3 01/13] xen: arm64: Add 8250 earlyprintk support

[Julien Grall]

On 11/25/2013 11:06 AM, Ian Campbell wrote:
> From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
>
> Extracted from "Basic Platform support for APM X-Gene Storm."
>
> Signed-off-by: Anup Patel <anup.patel@linaro.org>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
>
> Reworked into generic 8250 driver, use EARLY_UART_REG_SHIFT.
>
> While there observe a missing shift in the arm32 version (UART_THR is zero so
> it doesn't really matter). Changed for consistency.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>

My ack is missing here. I have already acked this patch on V2.

> ---
> v2: Drop unused early_uart_init macro
> ---
>   xen/arch/arm/Rules.mk             |    6 +++++
>   xen/arch/arm/arm64/debug-8250.inc |   45 +++++++++++++++++++++++++++++++++++++
>   2 files changed, 51 insertions(+)
>   create mode 100644 xen/arch/arm/arm64/debug-8250.inc
>
> diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
> index c27c2eb..aaa203e 100644
> --- a/xen/arch/arm/Rules.mk
> +++ b/xen/arch/arm/Rules.mk
> @@ -82,6 +82,12 @@ EARLY_PRINTK_INC := 8250
>   EARLY_UART_BASE_ADDRESS := 0xF0406B00
>   EARLY_UART_REG_SHIFT := 2
>   endif
> +ifeq ($(CONFIG_EARLY_PRINTK), xgene-storm)
> +EARLY_PRINTK_INC := 8250
> +EARLY_PRINTK_BAUD := 115200
> +EARLY_UART_BASE_ADDRESS := 0x1c020000
> +EARLY_UART_REG_SHIFT := 2
> +endif
>
>   ifneq ($(EARLY_PRINTK_INC),)
>   EARLY_PRINTK := y
> diff --git a/xen/arch/arm/arm64/debug-8250.inc b/xen/arch/arm/arm64/debug-8250.inc
> new file mode 100644
> index 0000000..158549a
> --- /dev/null
> +++ b/xen/arch/arm/arm64/debug-8250.inc
> @@ -0,0 +1,45 @@
> +/*
> + * xen/arch/arm/arm64/debug-8250.inc
> + *
> + * 8250 specific debug code
> + *
> + * Copyright (c) 2013 Applied Micro.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <xen/8250-uart.h>
> +
> +/* UART wait UART to be ready to transmit
> + * xb: register which contains the UART base address
> + * c: scratch register */
> +.macro early_uart_ready xb c
> +1:
> +       ldrb  w\c, [\xb, #UART_LSR << EARLY_UART_REG_SHIFT]
> +       and w\c, w\c, #UART_LSR_THRE
> +       cmp w\c, #UART_LSR_THRE
> +       b.ne 1b
> +.endm
> +
> +/* UART transmit character
> + * xb: register which contains the UART base address
> + * wt: register which contains the character to transmit */
> +.macro early_uart_transmit xb wt
> +        /* UART_THR  transmit holding */
> +        strb   \wt, [\xb, #UART_THR << EARLY_UART_REG_SHIFT]
> +.endm
> +
> +/*
> + * Local variables:
> + * mode: ASM
> + * indent-tabs-mode: nil
> + * End:
> + */
>

-- 
Julien Grall

Re: [PATCH v3 01/13] xen: arm64: Add 8250 earlyprintk support

[Ian Campbell]

On Mon, 2013-11-25 at 12:29 +0000, Julien Grall wrote:
> 
> On 11/25/2013 11:06 AM, Ian Campbell wrote:
> > From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
> >
> > Extracted from "Basic Platform support for APM X-Gene Storm."
> >
> > Signed-off-by: Anup Patel <anup.patel@linaro.org>
> > Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
> >
> > Reworked into generic 8250 driver, use EARLY_UART_REG_SHIFT.
> >
> > While there observe a missing shift in the arm32 version (UART_THR is zero so
> > it doesn't really matter). Changed for consistency.
> >
> > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> 
> My ack is missing here. I have already acked this patch on V2.

So you did, Sorry.

Ian.

[PATCH v3 02/13] xen: arm64: Add Basic Platform support for APM X-Gene Storm.

[Ian Campbell]

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

This patch adds initial platform stubs for APM X-Gene.

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

Drop earlyprintk (split into earlier patch). Only build on ARM64.

Drop empty init and reset hooks and enable 1:1 workaround.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
v3: Drop unused headers, use __initconst
v2: Drop empty hooks, merge the 1:1 workaround patch, drop early_printk.h
---
 xen/arch/arm/platforms/Makefile      |    1 +
 xen/arch/arm/platforms/xgene-storm.c |   48 ++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 xen/arch/arm/platforms/xgene-storm.c

diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile
index f0dd72c..680364f 100644
--- a/xen/arch/arm/platforms/Makefile
+++ b/xen/arch/arm/platforms/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARM_32) += exynos5.o
 obj-$(CONFIG_ARM_32) += midway.o
 obj-$(CONFIG_ARM_32) += omap5.o
 obj-$(CONFIG_ARM_32) += sunxi.o
+obj-$(CONFIG_ARM_64) += xgene-storm.o
diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
new file mode 100644
index 0000000..0198cec
--- /dev/null
+++ b/xen/arch/arm/platforms/xgene-storm.c
@@ -0,0 +1,48 @@
+/*
+ * xen/arch/arm/platforms/xgene-storm.c
+ *
+ * Applied Micro's X-Gene specific settings
+ *
+ * Pranavkumar Sawargaonkar <psawargaonkar@apm.com>
+ * Anup Patel <apatel@apm.com>
+ * Copyright (c) 2013 Applied Micro.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <asm/platform.h>
+
+static uint32_t xgene_storm_quirks(void)
+{
+    return PLATFORM_QUIRK_DOM0_MAPPING_11;
+}
+
+
+static const char * const xgene_storm_dt_compat[] __initconst =
+{
+    "apm,xgene-storm",
+    NULL
+};
+
+PLATFORM_START(xgene_storm, "APM X-GENE STORM")
+    .compatible = xgene_storm_dt_compat,
+    .quirks = xgene_storm_quirks,
+PLATFORM_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
1.7.10.4

[PATCH v3 03/13] xen: arm64: Add APM implementor id to processor implementers.

[Ian Campbell]

From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

This patch updates the list of processor implementers with APM implementor id.

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
 xen/arch/arm/setup.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index b032030..d252131 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -64,6 +64,7 @@ static const char * __initdata processor_implementers[] = {
     ['B'] = "Broadcom Corporation",
     ['D'] = "Digital Equipment Corp",
     ['M'] = "Motorola, Freescale Semiconductor Inc.",
+    ['P'] = "Applied Micro",
     ['Q'] = "Qualcomm Inc.",
     ['V'] = "Marvell Semiconductor Inc.",
     ['i'] = "Intel Corporation",
-- 
1.7.10.4

[PATCH v3 04/13] xen: arm: add a quirk to handle platforms with unusual GIC layout

[Ian Campbell]

On some platforms the pages are placed at a 64K stride instead of as
contiguous 4K pages.

This is because the ARM64 architecture allows for page sizes of 4/16/64K in
the MMU so a larger stride allow more granular control of mappings. We only
currently support 4K.

Use this quirk on the xgene platform.

This should ideally be fixed by an extension to the device tree bindings as
described in http://www.spinics.net/lists/devicetree/msg10473.html especially
http://www.spinics.net/lists/devicetree/msg10478.html. However for the time
being a platform specific quirk will do.

Note that we always map the GICV to the guest (including dom0) at a 4K stride
length and this is reflected in the DTB passed to the guest.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v3: Always map the GICV to the guest as contiguous 4k pages.
v2: This replaces "xen: arm: GICC_DIR register at offset 0x10000 instead of 0x1000"
---
 xen/arch/arm/gic.c                   |   37 ++++++++++++++++++++++++++++------
 xen/arch/arm/platforms/xgene-storm.c |    2 +-
 xen/include/asm-arm/platform.h       |    5 +++++
 3 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index ab49106..da4685e 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -30,6 +30,7 @@
 #include <xen/device_tree.h>
 #include <asm/p2m.h>
 #include <asm/domain.h>
+#include <asm/platform.h>
 
 #include <asm/gic.h>
 
@@ -444,7 +445,10 @@ void __init gic_init(void)
     BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
                  FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
     set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
-    set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 1, DEV_SHARED);
+    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
+    else
+        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
     set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
 
     /* Global settings: interrupt distributor */
@@ -823,6 +827,8 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
 
 int gicv_setup(struct domain *d)
 {
+    int ret;
+
     /*
      * Domain 0 gets the hardware address.
      * Guests get the virtual platform layout.
@@ -840,11 +846,30 @@ int gicv_setup(struct domain *d)
 
     d->arch.vgic.nr_lines = 0;
 
-    /* map the gic virtual cpu interface in the gic cpu interface region of
-     * the guest */
-    return map_mmio_regions(d, d->arch.vgic.cbase,
-                            d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
-                            gic.vbase);
+    /*
+     * Map the gic virtual cpu interface in the gic cpu interface
+     * region of the guest.
+     *
+     * The second page is always mapped at +4K irrespective of the
+     * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
+     */
+    ret = map_mmio_regions(d, d->arch.vgic.cbase,
+                           d->arch.vgic.cbase + PAGE_SIZE - 1,
+                           gic.vbase);
+    if (ret)
+        return ret;
+
+    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+                               gic.vbase + PAGE_SIZE);
+    else
+        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+                               gic.vbase + 16*PAGE_SIZE);
+
+    return ret;
+
 }
 
 static void gic_irq_eoi(void *info)
diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
index 0198cec..23ec46d 100644
--- a/xen/arch/arm/platforms/xgene-storm.c
+++ b/xen/arch/arm/platforms/xgene-storm.c
@@ -23,7 +23,7 @@
 
 static uint32_t xgene_storm_quirks(void)
 {
-    return PLATFORM_QUIRK_DOM0_MAPPING_11;
+    return PLATFORM_QUIRK_DOM0_MAPPING_11|PLATFORM_QUIRK_GIC_64K_STRIDE;
 }
 
 
diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h
index c282b30..c9314e5 100644
--- a/xen/include/asm-arm/platform.h
+++ b/xen/include/asm-arm/platform.h
@@ -44,6 +44,11 @@ struct platform_desc {
  * Useful on platform where System MMU is not yet implemented
  */
 #define PLATFORM_QUIRK_DOM0_MAPPING_11 (1 << 0)
+/*
+ * Quirk for platforms where the 4K GIC register ranges are placed at
+ * 64K stride.
+ */
+#define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 1)
 
 void __init platform_init(void);
 int __init platform_init_time(void);
-- 
1.7.10.4

Re: [PATCH v3 04/13] xen: arm: add a quirk to handle platforms with unusual GIC layout

[Julien Grall]

On 11/25/2013 11:06 AM, Ian Campbell wrote:
> On some platforms the pages are placed at a 64K stride instead of as
> contiguous 4K pages.
>
> This is because the ARM64 architecture allows for page sizes of 4/16/64K in
> the MMU so a larger stride allow more granular control of mappings. We only
> currently support 4K.
>
> Use this quirk on the xgene platform.
>
> This should ideally be fixed by an extension to the device tree bindings as
> described in http://www.spinics.net/lists/devicetree/msg10473.html especially
> http://www.spinics.net/lists/devicetree/msg10478.html. However for the time
> being a platform specific quirk will do.
>
> Note that we always map the GICV to the guest (including dom0) at a 4K stride
> length and this is reflected in the DTB passed to the guest.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> ---
> v3: Always map the GICV to the guest as contiguous 4k pages.
> v2: This replaces "xen: arm: GICC_DIR register at offset 0x10000 instead of 0x1000"
> ---
>   xen/arch/arm/gic.c                   |   37 ++++++++++++++++++++++++++++------
>   xen/arch/arm/platforms/xgene-storm.c |    2 +-
>   xen/include/asm-arm/platform.h       |    5 +++++
>   3 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index ab49106..da4685e 100644

[..]

> @@ -823,6 +827,8 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
>
>   int gicv_setup(struct domain *d)
>   {
> +    int ret;
> +
>       /*
>        * Domain 0 gets the hardware address.
>        * Guests get the virtual platform layout.
> @@ -840,11 +846,30 @@ int gicv_setup(struct domain *d)
>
>       d->arch.vgic.nr_lines = 0;
>
> -    /* map the gic virtual cpu interface in the gic cpu interface region of
> -     * the guest */
> -    return map_mmio_regions(d, d->arch.vgic.cbase,
> -                            d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> -                            gic.vbase);
> +    /*
> +     * Map the gic virtual cpu interface in the gic cpu interface
> +     * region of the guest.
> +     *
> +     * The second page is always mapped at +4K irrespective of the
> +     * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
> +     */
> +    ret = map_mmio_regions(d, d->arch.vgic.cbase,
> +                           d->arch.vgic.cbase + PAGE_SIZE - 1,
> +                           gic.vbase);
> +    if (ret)
> +        return ret;
> +
> +    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> +                               gic.vbase + PAGE_SIZE);
> +    else
> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> +                               gic.vbase + 16*PAGE_SIZE);

The condition needs to be inverted here ... the CPU second page is at 
64K only on platform where the quirk is enabled.

-- 
Julien Grall

Re: [PATCH v3 04/13] xen: arm: add a quirk to handle platforms with unusual GIC layout

[Ian Campbell]

On Mon, 2013-11-25 at 12:34 +0000, Julien Grall wrote:
> > +    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> > +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> > +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> > +                               gic.vbase + PAGE_SIZE);
> > +    else
> > +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> > +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> > +                               gic.vbase + 16*PAGE_SIZE);
> 
> The condition needs to be inverted here ... the CPU second page is at 
> 64K only on platform where the quirk is enabled.

Doh! Shows how much use Linux makes of the secnd page of registers (i.e.
none!)

Ian.

Re: [PATCH v3 04/13] xen: arm: add a quirk to handle platforms with unusual GIC layout

[Ian Campbell]

On Mon, 2013-11-25 at 12:36 +0000, Ian Campbell wrote:
> On Mon, 2013-11-25 at 12:34 +0000, Julien Grall wrote:
> > > +    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> > > +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> > > +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> > > +                               gic.vbase + PAGE_SIZE);
> > > +    else
> > > +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> > > +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> > > +                               gic.vbase + 16*PAGE_SIZE);
> > 
> > The condition needs to be inverted here ... the CPU second page is at 
> > 64K only on platform where the quirk is enabled.
> 
> Doh! Shows how much use Linux makes of the secnd page of registers (i.e.
> none!)

Here is what would be in v4:

8>------------

>From 5221157d3b9986cdfede8b1299f35569e6e29670 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ian.campbell@citrix.com>
Date: Thu, 21 Nov 2013 15:55:37 +0000
Subject: [PATCH] xen: arm: add a quirk to handle platforms with unusual GIC
 layout

On some platforms the pages are placed at a 64K stride instead of as
contiguous 4K pages.

This is because the ARM64 architecture allows for page sizes of 4/16/64K in
the MMU so a larger stride allow more granular control of mappings. We only
currently support 4K.

Use this quirk on the xgene platform.

This should ideally be fixed by an extension to the device tree bindings as
described in http://www.spinics.net/lists/devicetree/msg10473.html especially
http://www.spinics.net/lists/devicetree/msg10478.html. However for the time
being a platform specific quirk will do.

Note that we always map the GICV to the guest (including dom0) at a 4K stride
length and this is reflected in the DTB passed to the guest.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v4: FIx the condition when mapping the GIC to the guest.
v3: Always map the GICV to the guest as contiguous 4k pages.
v2: This replaces "xen: arm: GICC_DIR register at offset 0x10000 instead of 0x1000"
---
 xen/arch/arm/gic.c                   |   37 ++++++++++++++++++++++++++++------
 xen/arch/arm/platforms/xgene-storm.c |    2 +-
 xen/include/asm-arm/platform.h       |    5 +++++
 3 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index ab49106..0084f50 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -30,6 +30,7 @@
 #include <xen/device_tree.h>
 #include <asm/p2m.h>
 #include <asm/domain.h>
+#include <asm/platform.h>
 
 #include <asm/gic.h>
 
@@ -444,7 +445,10 @@ void __init gic_init(void)
     BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
                  FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
     set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
-    set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 1, DEV_SHARED);
+    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
+    else
+        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
     set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
 
     /* Global settings: interrupt distributor */
@@ -823,6 +827,8 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
 
 int gicv_setup(struct domain *d)
 {
+    int ret;
+
     /*
      * Domain 0 gets the hardware address.
      * Guests get the virtual platform layout.
@@ -840,11 +846,30 @@ int gicv_setup(struct domain *d)
 
     d->arch.vgic.nr_lines = 0;
 
-    /* map the gic virtual cpu interface in the gic cpu interface region of
-     * the guest */
-    return map_mmio_regions(d, d->arch.vgic.cbase,
-                            d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
-                            gic.vbase);
+    /*
+     * Map the gic virtual cpu interface in the gic cpu interface
+     * region of the guest.
+     *
+     * The second page is always mapped at +4K irrespective of the
+     * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
+     */
+    ret = map_mmio_regions(d, d->arch.vgic.cbase,
+                           d->arch.vgic.cbase + PAGE_SIZE - 1,
+                           gic.vbase);
+    if (ret)
+        return ret;
+
+    if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+                               gic.vbase + PAGE_SIZE);
+    else
+        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+                               gic.vbase + 16*PAGE_SIZE);
+
+    return ret;
+
 }
 
 static void gic_irq_eoi(void *info)
diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
index 0198cec..23ec46d 100644
--- a/xen/arch/arm/platforms/xgene-storm.c
+++ b/xen/arch/arm/platforms/xgene-storm.c
@@ -23,7 +23,7 @@
 
 static uint32_t xgene_storm_quirks(void)
 {
-    return PLATFORM_QUIRK_DOM0_MAPPING_11;
+    return PLATFORM_QUIRK_DOM0_MAPPING_11|PLATFORM_QUIRK_GIC_64K_STRIDE;
 }
 
 
diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h
index c282b30..c9314e5 100644
--- a/xen/include/asm-arm/platform.h
+++ b/xen/include/asm-arm/platform.h
@@ -44,6 +44,11 @@ struct platform_desc {
  * Useful on platform where System MMU is not yet implemented
  */
 #define PLATFORM_QUIRK_DOM0_MAPPING_11 (1 << 0)
+/*
+ * Quirk for platforms where the 4K GIC register ranges are placed at
+ * 64K stride.
+ */
+#define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 1)
 
 void __init platform_init(void);
 int __init platform_init_time(void);
-- 
1.7.10.4

Re: [PATCH v3 04/13] xen: arm: add a quirk to handle platforms with unusual GIC layout

[Julien Grall]

On 11/25/2013 12:38 PM, Ian Campbell wrote:
> On Mon, 2013-11-25 at 12:36 +0000, Ian Campbell wrote:
>> On Mon, 2013-11-25 at 12:34 +0000, Julien Grall wrote:
>>>> +    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
>>>> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
>>>> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
>>>> +                               gic.vbase + PAGE_SIZE);
>>>> +    else
>>>> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
>>>> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
>>>> +                               gic.vbase + 16*PAGE_SIZE);
>>>
>>> The condition needs to be inverted here ... the CPU second page is at
>>> 64K only on platform where the quirk is enabled.
>>
>> Doh! Shows how much use Linux makes of the secnd page of registers (i.e.
>> none!)
>
> Here is what would be in v4:
>
> 8>------------
>
>  From 5221157d3b9986cdfede8b1299f35569e6e29670 Mon Sep 17 00:00:00 2001
> From: Ian Campbell <ian.campbell@citrix.com>
> Date: Thu, 21 Nov 2013 15:55:37 +0000
> Subject: [PATCH] xen: arm: add a quirk to handle platforms with unusual GIC
>   layout
>
> On some platforms the pages are placed at a 64K stride instead of as
> contiguous 4K pages.
>
> This is because the ARM64 architecture allows for page sizes of 4/16/64K in
> the MMU so a larger stride allow more granular control of mappings. We only
> currently support 4K.
>
> Use this quirk on the xgene platform.
>
> This should ideally be fixed by an extension to the device tree bindings as
> described in http://www.spinics.net/lists/devicetree/msg10473.html especially
> http://www.spinics.net/lists/devicetree/msg10478.html. However for the time
> being a platform specific quirk will do.
>
> Note that we always map the GICV to the guest (including dom0) at a 4K stride
> length and this is reflected in the DTB passed to the guest.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>

For V4:
Acked-by: Julien Grall <julien.grall@linaro.org>

> ---
> v4: FIx the condition when mapping the GIC to the guest.
> v3: Always map the GICV to the guest as contiguous 4k pages.
> v2: This replaces "xen: arm: GICC_DIR register at offset 0x10000 instead of 0x1000"
> ---
>   xen/arch/arm/gic.c                   |   37 ++++++++++++++++++++++++++++------
>   xen/arch/arm/platforms/xgene-storm.c |    2 +-
>   xen/include/asm-arm/platform.h       |    5 +++++
>   3 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index ab49106..0084f50 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -30,6 +30,7 @@
>   #include <xen/device_tree.h>
>   #include <asm/p2m.h>
>   #include <asm/domain.h>
> +#include <asm/platform.h>
>
>   #include <asm/gic.h>
>
> @@ -444,7 +445,10 @@ void __init gic_init(void)
>       BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
>                    FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
>       set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
> -    set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 1, DEV_SHARED);
> +    if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> +        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
> +    else
> +        set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
>       set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
>
>       /* Global settings: interrupt distributor */
> @@ -823,6 +827,8 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
>
>   int gicv_setup(struct domain *d)
>   {
> +    int ret;
> +
>       /*
>        * Domain 0 gets the hardware address.
>        * Guests get the virtual platform layout.
> @@ -840,11 +846,30 @@ int gicv_setup(struct domain *d)
>
>       d->arch.vgic.nr_lines = 0;
>
> -    /* map the gic virtual cpu interface in the gic cpu interface region of
> -     * the guest */
> -    return map_mmio_regions(d, d->arch.vgic.cbase,
> -                            d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> -                            gic.vbase);
> +    /*
> +     * Map the gic virtual cpu interface in the gic cpu interface
> +     * region of the guest.
> +     *
> +     * The second page is always mapped at +4K irrespective of the
> +     * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
> +     */
> +    ret = map_mmio_regions(d, d->arch.vgic.cbase,
> +                           d->arch.vgic.cbase + PAGE_SIZE - 1,
> +                           gic.vbase);
> +    if (ret)
> +        return ret;
> +
> +    if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> +                               gic.vbase + PAGE_SIZE);
> +    else
> +        ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
> +                               d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
> +                               gic.vbase + 16*PAGE_SIZE);
> +
> +    return ret;
> +
>   }
>
>   static void gic_irq_eoi(void *info)
> diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
> index 0198cec..23ec46d 100644
> --- a/xen/arch/arm/platforms/xgene-storm.c
> +++ b/xen/arch/arm/platforms/xgene-storm.c
> @@ -23,7 +23,7 @@
>
>   static uint32_t xgene_storm_quirks(void)
>   {
> -    return PLATFORM_QUIRK_DOM0_MAPPING_11;
> +    return PLATFORM_QUIRK_DOM0_MAPPING_11|PLATFORM_QUIRK_GIC_64K_STRIDE;
>   }
>
>
> diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h
> index c282b30..c9314e5 100644
> --- a/xen/include/asm-arm/platform.h
> +++ b/xen/include/asm-arm/platform.h
> @@ -44,6 +44,11 @@ struct platform_desc {
>    * Useful on platform where System MMU is not yet implemented
>    */
>   #define PLATFORM_QUIRK_DOM0_MAPPING_11 (1 << 0)
> +/*
> + * Quirk for platforms where the 4K GIC register ranges are placed at
> + * 64K stride.
> + */
> +#define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 1)
>
>   void __init platform_init(void);
>   int __init platform_init_time(void);
>

-- 
Julien Grall

[PATCH v3 05/13] xen: arm: allow platform code to select dom0 event channel irq

[Ian Campbell]

Currently the hardcoded use of GUEST_EVTCHN_PPI is problematic if that is a
real PPI on the platform.

We really need to be smarter about selecting an unused PPI but in the meantime
we can at least give the platform code the option of hardcoding a number which
works for the platform.

Hardcode a suitable PPI on the Xgene platform.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
 xen/arch/arm/domain.c                |    7 +++++--
 xen/arch/arm/platform.c              |    7 +++++++
 xen/arch/arm/platforms/xgene-storm.c |    1 +
 xen/include/asm-arm/platform.h       |    5 +++++
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 2f57d01..52d2403 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -31,6 +31,7 @@
 #include <asm/processor-ca15.h>
 
 #include <asm/gic.h>
+#include <asm/platform.h>
 #include "vtimer.h"
 #include "vuart.h"
 
@@ -526,8 +527,10 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags)
     if ( (rc = vcpu_domain_init(d)) != 0 )
         goto fail;
 
-    /* XXX dom0 needs more intelligent selection of PPI */
-    d->arch.evtchn_irq = GUEST_EVTCHN_PPI;
+    if ( d->domain_id )
+        d->arch.evtchn_irq = GUEST_EVTCHN_PPI;
+    else
+        d->arch.evtchn_irq = platform_dom0_evtchn_ppi();
 
     /*
      * Virtual UART is only used by linux early printk and decompress code.
diff --git a/xen/arch/arm/platform.c b/xen/arch/arm/platform.c
index 0fbbdc7..a7f9ee4 100644
--- a/xen/arch/arm/platform.c
+++ b/xen/arch/arm/platform.c
@@ -156,6 +156,13 @@ bool_t platform_device_is_blacklisted(const struct dt_device_node *node)
     return dt_match_node(blacklist, node);
 }
 
+unsigned int platform_dom0_evtchn_ppi(void)
+{
+    if ( platform && platform->dom0_evtchn_ppi )
+        return platform->dom0_evtchn_ppi;
+    return GUEST_EVTCHN_PPI;
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
index 23ec46d..f416da3 100644
--- a/xen/arch/arm/platforms/xgene-storm.c
+++ b/xen/arch/arm/platforms/xgene-storm.c
@@ -36,6 +36,7 @@ static const char * const xgene_storm_dt_compat[] __initconst =
 PLATFORM_START(xgene_storm, "APM X-GENE STORM")
     .compatible = xgene_storm_dt_compat,
     .quirks = xgene_storm_quirks,
+    .dom0_evtchn_ppi = 24,
 PLATFORM_END
 
 /*
diff --git a/xen/include/asm-arm/platform.h b/xen/include/asm-arm/platform.h
index c9314e5..5900ee4 100644
--- a/xen/include/asm-arm/platform.h
+++ b/xen/include/asm-arm/platform.h
@@ -37,6 +37,10 @@ struct platform_desc {
      * List of devices which must not pass-through to a guest
      */
     const struct dt_device_match *blacklist_dev;
+    /*
+     * The IRQ (PPI) to use to inject event channels to dom0.
+     */
+    unsigned int dom0_evtchn_ppi;
 };
 
 /*
@@ -61,6 +65,7 @@ void platform_reset(void);
 void platform_poweroff(void);
 bool_t platform_has_quirk(uint32_t quirk);
 bool_t platform_device_is_blacklisted(const struct dt_device_node *node);
+unsigned int platform_dom0_evtchn_ppi(void);
 
 #define PLATFORM_START(_name, _namestr)                         \
 static const struct platform_desc  __plat_desc_##_name __used   \
-- 
1.7.10.4

[PATCH v3 06/13] xen: arm64: Map xgene PCI memory regions and interrupts to dom0.

[Ian Campbell]

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
v3: Add a comment on why this is needed.
v2: This replaces "HACK: xen: arm: map PCI controller ranges region MMIOs to
dom0."
---
 xen/arch/arm/platforms/xgene-storm.c |   82 ++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c
index f416da3..ea9b0f4 100644
--- a/xen/arch/arm/platforms/xgene-storm.c
+++ b/xen/arch/arm/platforms/xgene-storm.c
@@ -20,12 +20,93 @@
 
 #include <xen/config.h>
 #include <asm/platform.h>
+#include <asm/gic.h>
 
 static uint32_t xgene_storm_quirks(void)
 {
     return PLATFORM_QUIRK_DOM0_MAPPING_11|PLATFORM_QUIRK_GIC_64K_STRIDE;
 }
 
+static int map_one_mmio(struct domain *d, const char *what,
+                         paddr_t start, paddr_t end)
+{
+    int ret;
+
+    printk("Additional MMIO %"PRIpaddr"-%"PRIpaddr" (%s)\n",
+           start, end, what);
+    ret = map_mmio_regions(d, start, end, start);
+    if ( ret )
+        printk("Failed to map %s @ %"PRIpaddr" to dom%d\n",
+               what, start, d->domain_id);
+    return ret;
+}
+
+static int map_one_spi(struct domain *d, const char *what,
+                       unsigned int spi, unsigned int type)
+{
+    struct dt_irq irq;
+    int ret;
+
+    irq.type = type;
+
+    irq.irq = spi + 32; /* SPIs start at IRQ 32 */
+
+    printk("Additional IRQ %u (%s)\n", irq.irq, what);
+
+    ret = gic_route_irq_to_guest(d, &irq, what);
+    if ( ret )
+        printk("Failed to route %s to dom%d\n", what, d->domain_id);
+
+    return ret;
+}
+
+/*
+ * Xen does not currently support mapping MMIO regions and interrupt
+ * for bus child devices (referenced via the "ranges" and
+ * "interrupt-map" properties to domain 0). Instead for now map the
+ * necessary resources manually.
+ */
+static int xgene_storm_specific_mapping(struct domain *d)
+{
+    int ret;
+
+    /* Map the PCIe bus resources */
+    ret = map_one_mmio(d, "PCI MEM REGION", 0xe000000000UL, 0xe010000000UL);
+    if ( ret )
+        goto err;
+
+    ret = map_one_mmio(d, "PCI IO REGION", 0xe080000000UL, 0xe080010000UL);
+    if ( ret )
+        goto err;
+
+    ret = map_one_mmio(d, "PCI CFG REGION", 0xe0d0000000UL, 0xe0d0200000UL);
+    if ( ret )
+        goto err;
+    ret = map_one_mmio(d, "PCI MSI REGION", 0xe010000000UL, 0xe010800000UL);
+    if ( ret )
+        goto err;
+
+    ret = map_one_spi(d, "PCI#INTA", 0xc2, DT_IRQ_TYPE_LEVEL_HIGH);
+    if ( ret )
+        goto err;
+
+    ret = map_one_spi(d, "PCI#INTB", 0xc3, DT_IRQ_TYPE_LEVEL_HIGH);
+    if ( ret )
+        goto err;
+
+    ret = map_one_spi(d, "PCI#INTC", 0xc4, DT_IRQ_TYPE_LEVEL_HIGH);
+    if ( ret )
+        goto err;
+
+    ret = map_one_spi(d, "PCI#INTD", 0xc5, DT_IRQ_TYPE_LEVEL_HIGH);
+    if ( ret )
+        goto err;
+
+    ret = 0;
+err:
+    return ret;
+}
+
 
 static const char * const xgene_storm_dt_compat[] __initconst =
 {
@@ -36,6 +117,7 @@ static const char * const xgene_storm_dt_compat[] __initconst =
 PLATFORM_START(xgene_storm, "APM X-GENE STORM")
     .compatible = xgene_storm_dt_compat,
     .quirks = xgene_storm_quirks,
+    .specific_mapping = xgene_storm_specific_mapping,
     .dom0_evtchn_ppi = 24,
 PLATFORM_END
 
-- 
1.7.10.4

[PATCH v3 07/13] xen: arm: include ns16550 driver on arm64 too

[Ian Campbell]

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
 config/arm64.mk |    1 +
 1 file changed, 1 insertion(+)

diff --git a/config/arm64.mk b/config/arm64.mk
index 49055fa..15b57a4 100644
--- a/config/arm64.mk
+++ b/config/arm64.mk
@@ -7,6 +7,7 @@ CONFIG_XEN_INSTALL_SUFFIX :=
 CFLAGS += #-marm -march= -mcpu= etc
 
 HAS_PL011 := y
+HAS_NS16550 := y
 
 # Use only if calling $(LD) directly.
 LDFLAGS_DIRECT += -EL
-- 
1.7.10.4

[PATCH v3 08/13] xen: arm: Handle cpus nodes with #address-cells > 1

[Ian Campbell]

The APM X-Gene Mustang board DTS has #address-cells = 2.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v3: Correct check for property length (bytes not cells)
v2: Use dt_read_number, check the property length
---
 xen/arch/arm/smpboot.c |   34 +++++++++++++++++++++++++++++-----
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index 6c90fa6..7636ab8 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -125,18 +125,42 @@ void __init smp_init_cpus(void)
 
     dt_for_each_child_node( cpus, cpu )
     {
-        u32 hwid;
+        const __be32 *prop;
+        u64 addr;
+        u32 reg_len, hwid;
 
         if ( !dt_device_type_is_equal(cpu, "cpu") )
             continue;
 
-        if ( !dt_property_read_u32(cpu, "reg", &hwid) )
+        if ( dt_n_size_cells(cpu) != 0 )
+            printk(XENLOG_WARNING "cpu node `%s`: #size-cells %d\n",
+                   dt_node_full_name(cpu), dt_n_size_cells(cpu));
+
+        prop = dt_get_property(cpu, "reg", &reg_len);
+        if ( !prop )
+        {
+            printk(XENLOG_WARNING "cpu node `%s`: has no reg property\n",
+                   dt_node_full_name(cpu));
+            continue;
+        }
+
+        if ( reg_len < dt_cells_to_size(dt_n_addr_cells(cpu)) )
         {
-            printk(XENLOG_WARNING "cpu node `%s`: missing reg property\n",
+            printk(XENLOG_WARNING "cpu node `%s`: reg property too short\n",
                    dt_node_full_name(cpu));
             continue;
         }
 
+        addr = dt_read_number(prop, dt_n_addr_cells(cpu));
+
+        hwid = addr;
+        if ( hwid != addr )
+        {
+            printk(XENLOG_WARNING "cpu node `%s`: hwid overflow %"PRIx64"\n",
+                   dt_node_full_name(cpu), addr);
+            continue;
+        }
+
         /*
          * 8 MSBs must be set to 0 in the DT since the reg property
          * defines the MPIDR[23:0]
@@ -159,8 +183,8 @@ void __init smp_init_cpus(void)
             if ( tmp_map[j] == hwid )
             {
                 printk(XENLOG_WARNING
-                       "cpu node `%s`: duplicate /cpu reg properties in the DT\n",
-                       dt_node_full_name(cpu));
+                       "cpu node `%s`: duplicate /cpu reg properties %"PRIx32" in the DT\n",
+                       dt_node_full_name(cpu), hwid);
                 break;
             }
         }
-- 
1.7.10.4

Re: [PATCH v3 08/13] xen: arm: Handle cpus nodes with #address-cells > 1

[Julien Grall]

On 11/25/2013 11:07 AM, Ian Campbell wrote:
> The APM X-Gene Mustang board DTS has #address-cells = 2.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>

> ---
> v3: Correct check for property length (bytes not cells)
> v2: Use dt_read_number, check the property length
> ---
>   xen/arch/arm/smpboot.c |   34 +++++++++++++++++++++++++++++-----
>   1 file changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
> index 6c90fa6..7636ab8 100644
> --- a/xen/arch/arm/smpboot.c
> +++ b/xen/arch/arm/smpboot.c
> @@ -125,18 +125,42 @@ void __init smp_init_cpus(void)
>
>       dt_for_each_child_node( cpus, cpu )
>       {
> -        u32 hwid;
> +        const __be32 *prop;
> +        u64 addr;
> +        u32 reg_len, hwid;
>
>           if ( !dt_device_type_is_equal(cpu, "cpu") )
>               continue;
>
> -        if ( !dt_property_read_u32(cpu, "reg", &hwid) )
> +        if ( dt_n_size_cells(cpu) != 0 )
> +            printk(XENLOG_WARNING "cpu node `%s`: #size-cells %d\n",
> +                   dt_node_full_name(cpu), dt_n_size_cells(cpu));
> +
> +        prop = dt_get_property(cpu, "reg", &reg_len);
> +        if ( !prop )
> +        {
> +            printk(XENLOG_WARNING "cpu node `%s`: has no reg property\n",
> +                   dt_node_full_name(cpu));
> +            continue;
> +        }
> +
> +        if ( reg_len < dt_cells_to_size(dt_n_addr_cells(cpu)) )
>           {
> -            printk(XENLOG_WARNING "cpu node `%s`: missing reg property\n",
> +            printk(XENLOG_WARNING "cpu node `%s`: reg property too short\n",
>                      dt_node_full_name(cpu));
>               continue;
>           }
>
> +        addr = dt_read_number(prop, dt_n_addr_cells(cpu));
> +
> +        hwid = addr;
> +        if ( hwid != addr )
> +        {
> +            printk(XENLOG_WARNING "cpu node `%s`: hwid overflow %"PRIx64"\n",
> +                   dt_node_full_name(cpu), addr);
> +            continue;
> +        }
> +
>           /*
>            * 8 MSBs must be set to 0 in the DT since the reg property
>            * defines the MPIDR[23:0]
> @@ -159,8 +183,8 @@ void __init smp_init_cpus(void)
>               if ( tmp_map[j] == hwid )
>               {
>                   printk(XENLOG_WARNING
> -                       "cpu node `%s`: duplicate /cpu reg properties in the DT\n",
> -                       dt_node_full_name(cpu));
> +                       "cpu node `%s`: duplicate /cpu reg properties %"PRIx32" in the DT\n",
> +                       dt_node_full_name(cpu), hwid);
>                   break;
>               }
>           }
>

-- 
Julien Grall

[PATCH v3 09/13] xen: arm: Make register bit definitions unsigned.

[Ian Campbell]

Otherwise the results of the shifting can be undefined and/or sign extended.

Most registers are 32-bit on both arm32 and arm64 and hence are just unsigned
ints, however HCR is 64-bit on arm64 and therefore is unsigned long.

Pointed out in the context of HCR_* by Pranavkumar Sawargaonkar.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Cc: Pranavkumar Sawargaonkar <psawargaonkar@apm.com>
---
v2:
Make 64-bit registers unsigned long
---
 xen/include/asm-arm/processor.h |  144 +++++++++++++++++++--------------------
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 3da3a3d..b2746cc 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -18,71 +18,71 @@
 #define MPIDR_INVALID       (~MPIDR_HWID_MASK)
 
 /* TTBCR Translation Table Base Control Register */
-#define TTBCR_EAE    0x80000000
-#define TTBCR_N_MASK 0x07
-#define TTBCR_N_16KB 0x00
-#define TTBCR_N_8KB  0x01
-#define TTBCR_N_4KB  0x02
-#define TTBCR_N_2KB  0x03
-#define TTBCR_N_1KB  0x04
+#define TTBCR_EAE    _AC(0x80000000,U)
+#define TTBCR_N_MASK _AC(0x07,U)
+#define TTBCR_N_16KB _AC(0x00,U)
+#define TTBCR_N_8KB  _AC(0x01,U)
+#define TTBCR_N_4KB  _AC(0x02,U)
+#define TTBCR_N_2KB  _AC(0x03,U)
+#define TTBCR_N_1KB  _AC(0x04,U)
 
 /* SCTLR System Control Register. */
 /* HSCTLR is a subset of this. */
-#define SCTLR_TE        (1<<30)
-#define SCTLR_AFE       (1<<29)
-#define SCTLR_TRE       (1<<28)
-#define SCTLR_NMFI      (1<<27)
-#define SCTLR_EE        (1<<25)
-#define SCTLR_VE        (1<<24)
-#define SCTLR_U         (1<<22)
-#define SCTLR_FI        (1<<21)
-#define SCTLR_WXN       (1<<19)
-#define SCTLR_HA        (1<<17)
-#define SCTLR_RR        (1<<14)
-#define SCTLR_V         (1<<13)
-#define SCTLR_I         (1<<12)
-#define SCTLR_Z         (1<<11)
-#define SCTLR_SW        (1<<10)
-#define SCTLR_B         (1<<7)
-#define SCTLR_C         (1<<2)
-#define SCTLR_A         (1<<1)
-#define SCTLR_M         (1<<0)
-
-#define HSCTLR_BASE       0x30c51878
+#define SCTLR_TE        (_AC(1,U)<<30)
+#define SCTLR_AFE       (_AC(1,U)<<29)
+#define SCTLR_TRE       (_AC(1,U)<<28)
+#define SCTLR_NMFI      (_AC(1,U)<<27)
+#define SCTLR_EE        (_AC(1,U)<<25)
+#define SCTLR_VE        (_AC(1,U)<<24)
+#define SCTLR_U         (_AC(1,U)<<22)
+#define SCTLR_FI        (_AC(1,U)<<21)
+#define SCTLR_WXN       (_AC(1,U)<<19)
+#define SCTLR_HA        (_AC(1,U)<<17)
+#define SCTLR_RR        (_AC(1,U)<<14)
+#define SCTLR_V         (_AC(1,U)<<13)
+#define SCTLR_I         (_AC(1,U)<<12)
+#define SCTLR_Z         (_AC(1,U)<<11)
+#define SCTLR_SW        (_AC(1,U)<<10)
+#define SCTLR_B         (_AC(1,U)<<7)
+#define SCTLR_C         (_AC(1,U)<<2)
+#define SCTLR_A         (_AC(1,U)<<1)
+#define SCTLR_M         (_AC(1,U)<<0)
+
+#define HSCTLR_BASE     _AC(0x30c51878,U)
 
 /* HCR Hyp Configuration Register */
-#define HCR_RW          (1<<31) /* Register Width, ARM64 only */
-#define HCR_TGE         (1<<27) /* Trap General Exceptions */
-#define HCR_TVM         (1<<26) /* Trap Virtual Memory Controls */
-#define HCR_TTLB        (1<<25) /* Trap TLB Maintenance Operations */
-#define HCR_TPU         (1<<24) /* Trap Cache Maintenance Operations to PoU */
-#define HCR_TPC         (1<<23) /* Trap Cache Maintenance Operations to PoC */
-#define HCR_TSW         (1<<22) /* Trap Set/Way Cache Maintenance Operations */
-#define HCR_TAC         (1<<21) /* Trap ACTLR Accesses */
-#define HCR_TIDCP       (1<<20) /* Trap lockdown */
-#define HCR_TSC         (1<<19) /* Trap SMC instruction */
-#define HCR_TID3        (1<<18) /* Trap ID Register Group 3 */
-#define HCR_TID2        (1<<17) /* Trap ID Register Group 2 */
-#define HCR_TID1        (1<<16) /* Trap ID Register Group 1 */
-#define HCR_TID0        (1<<15) /* Trap ID Register Group 0 */
-#define HCR_TWE         (1<<14) /* Trap WFE instruction */
-#define HCR_TWI         (1<<13) /* Trap WFI instruction */
-#define HCR_DC          (1<<12) /* Default cacheable */
-#define HCR_BSU_MASK    (3<<10) /* Barrier Shareability Upgrade */
-#define HCR_BSU_NONE     (0<<10)
-#define HCR_BSU_INNER    (1<<10)
-#define HCR_BSU_OUTER    (2<<10)
-#define HCR_BSU_FULL     (3<<10)
-#define HCR_FB          (1<<9) /* Force Broadcast of Cache/BP/TLB operations */
-#define HCR_VA          (1<<8) /* Virtual Asynchronous Abort */
-#define HCR_VI          (1<<7) /* Virtual IRQ */
-#define HCR_VF          (1<<6) /* Virtual FIQ */
-#define HCR_AMO         (1<<5) /* Override CPSR.A */
-#define HCR_IMO         (1<<4) /* Override CPSR.I */
-#define HCR_FMO         (1<<3) /* Override CPSR.F */
-#define HCR_PTW         (1<<2) /* Protected Walk */
-#define HCR_SWIO        (1<<1) /* Set/Way Invalidation Override */
-#define HCR_VM          (1<<0) /* Virtual MMU Enable */
+#define HCR_RW          (_AC(1,UL)<<31) /* Register Width, ARM64 only */
+#define HCR_TGE         (_AC(1,UL)<<27) /* Trap General Exceptions */
+#define HCR_TVM         (_AC(1,UL)<<26) /* Trap Virtual Memory Controls */
+#define HCR_TTLB        (_AC(1,UL)<<25) /* Trap TLB Maintenance Operations */
+#define HCR_TPU         (_AC(1,UL)<<24) /* Trap Cache Maintenance Operations to PoU */
+#define HCR_TPC         (_AC(1,UL)<<23) /* Trap Cache Maintenance Operations to PoC */
+#define HCR_TSW         (_AC(1,UL)<<22) /* Trap Set/Way Cache Maintenance Operations */
+#define HCR_TAC         (_AC(1,UL)<<21) /* Trap ACTLR Accesses */
+#define HCR_TIDCP       (_AC(1,UL)<<20) /* Trap lockdown */
+#define HCR_TSC         (_AC(1,UL)<<19) /* Trap SMC instruction */
+#define HCR_TID3        (_AC(1,UL)<<18) /* Trap ID Register Group 3 */
+#define HCR_TID2        (_AC(1,UL)<<17) /* Trap ID Register Group 2 */
+#define HCR_TID1        (_AC(1,UL)<<16) /* Trap ID Register Group 1 */
+#define HCR_TID0        (_AC(1,UL)<<15) /* Trap ID Register Group 0 */
+#define HCR_TWE         (_AC(1,UL)<<14) /* Trap WFE instruction */
+#define HCR_TWI         (_AC(1,UL)<<13) /* Trap WFI instruction */
+#define HCR_DC          (_AC(1,UL)<<12) /* Default cacheable */
+#define HCR_BSU_MASK    (_AC(3,UL)<<10) /* Barrier Shareability Upgrade */
+#define HCR_BSU_NONE     (_AC(0,UL)<<10)
+#define HCR_BSU_INNER    (_AC(1,UL)<<10)
+#define HCR_BSU_OUTER    (_AC(2,UL)<<10)
+#define HCR_BSU_FULL     (_AC(3,UL)<<10)
+#define HCR_FB          (_AC(1,UL)<<9) /* Force Broadcast of Cache/BP/TLB operations */
+#define HCR_VA          (_AC(1,UL)<<8) /* Virtual Asynchronous Abort */
+#define HCR_VI          (_AC(1,UL)<<7) /* Virtual IRQ */
+#define HCR_VF          (_AC(1,UL)<<6) /* Virtual FIQ */
+#define HCR_AMO         (_AC(1,UL)<<5) /* Override CPSR.A */
+#define HCR_IMO         (_AC(1,UL)<<4) /* Override CPSR.I */
+#define HCR_FMO         (_AC(1,UL)<<3) /* Override CPSR.F */
+#define HCR_PTW         (_AC(1,UL)<<2) /* Protected Walk */
+#define HCR_SWIO        (_AC(1,UL)<<1) /* Set/Way Invalidation Override */
+#define HCR_VM          (_AC(1,UL)<<0) /* Virtual MMU Enable */
 
 #define HSR_EC_UNKNOWN              0x00
 #define HSR_EC_WFI_WFE              0x01
@@ -346,20 +346,20 @@ union hsr {
                               HSR_SYSREG_OP2_MASK)
 
 /* Physical Address Register */
-#define PAR_F           (1<<0)
+#define PAR_F           (_AC(1,U)<<0)
 
 /* .... If F == 1 */
 #define PAR_FSC_SHIFT   (1)
-#define PAR_FSC_MASK    (0x3f<<PAR_FSC_SHIFT)
-#define PAR_STAGE21     (1<<8)     /* Stage 2 Fault During Stage 1 Walk */
-#define PAR_STAGE2      (1<<9)     /* Stage 2 Fault */
+#define PAR_FSC_MASK    (_AC(0x3f,U)<<PAR_FSC_SHIFT)
+#define PAR_STAGE21     (_AC(1,U)<<8)     /* Stage 2 Fault During Stage 1 Walk */
+#define PAR_STAGE2      (_AC(1,U)<<9)     /* Stage 2 Fault */
 
 /* If F == 0 */
 #define PAR_MAIR_SHIFT  56                       /* Memory Attributes */
 #define PAR_MAIR_MASK   (0xffLL<<PAR_MAIR_SHIFT)
-#define PAR_NS          (1<<9)                   /* Non-Secure */
+#define PAR_NS          (_AC(1,U)<<9)                   /* Non-Secure */
 #define PAR_SH_SHIFT    7                        /* Shareability */
-#define PAR_SH_MASK     (3<<PAR_SH_SHIFT)
+#define PAR_SH_MASK     (_AC(3,U)<<PAR_SH_SHIFT)
 
 /* Fault Status Register */
 /*
@@ -372,11 +372,11 @@ union hsr {
  * 10xxxx -- Other
  * 11xxxx -- Implementation Defined
  */
-#define FSC_TYPE_MASK (0x3<<4)
-#define FSC_TYPE_FAULT (0x00<<4)
-#define FSC_TYPE_ABT   (0x01<<4)
-#define FSC_TYPE_OTH   (0x02<<4)
-#define FSC_TYPE_IMPL  (0x03<<4)
+#define FSC_TYPE_MASK (_AC(0x3,U)<<4)
+#define FSC_TYPE_FAULT (_AC(0x00,U)<<4)
+#define FSC_TYPE_ABT   (_AC(0x01,U)<<4)
+#define FSC_TYPE_OTH   (_AC(0x02,U)<<4)
+#define FSC_TYPE_IMPL  (_AC(0x03,U)<<4)
 
 #define FSC_FLT_TRANS  (0x04)
 #define FSC_FLT_ACCESS (0x08)
@@ -391,7 +391,7 @@ union hsr {
 #define FSC_LKD        (0x34) /* Lockdown Abort */
 #define FSC_CPR        (0x3a) /* Coprocossor Abort */
 
-#define FSC_LL_MASK    (0x03<<0)
+#define FSC_LL_MASK    (_AC(0x03,U)<<0)
 
 /* Time counter hypervisor control register */
 #define CNTHCTL_PA      (1u<<0)  /* Kernel/user access to physical counter */
-- 
1.7.10.4

[PATCH v3 10/13] xen: arm: explicitly map 64 bit release address

[Ian Campbell]

In case it is outside visible ram.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
 xen/arch/arm/arm64/smpboot.c |   14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm64/smpboot.c b/xen/arch/arm/arm64/smpboot.c
index 8239590..8696ed6 100644
--- a/xen/arch/arm/arm64/smpboot.c
+++ b/xen/arch/arm/arm64/smpboot.c
@@ -4,6 +4,8 @@
 #include <xen/errno.h>
 #include <xen/mm.h>
 #include <xen/smp.h>
+#include <xen/vmap.h>
+#include <asm/io.h>
 
 struct smp_enable_ops {
         int             (*prepare_cpu)(int);
@@ -14,7 +16,7 @@ static struct smp_enable_ops smp_enable_ops[NR_CPUS];
 
 static int __init smp_spin_table_cpu_up(int cpu)
 {
-    paddr_t *release;
+    paddr_t __iomem *release;
 
     if (!cpu_release_addr[cpu])
     {
@@ -22,12 +24,20 @@ static int __init smp_spin_table_cpu_up(int cpu)
         return -ENODEV;
     }
 
-    release = __va(cpu_release_addr[cpu]);
+    release = ioremap_nocache(cpu_release_addr[cpu], 8);
+    if ( !release )
+    {
+        dprintk(XENLOG_ERR, "CPU%d: Unable to map release address\n", cpu);
+        return -EFAULT;
+    }
 
     release[0] = __pa(init_secondary);
     flush_xen_data_tlb_range_va((vaddr_t)release, sizeof(*release));
 
+    iounmap(release);
+
     sev();
+
     return 0;
 }
 
-- 
1.7.10.4

[PATCH v3 11/13] xen: arm: enable synchronous console while starting secondary CPUs

[Ian Campbell]

Setting synchronous console ensures that any printk hits the buffer
immediately and that any outstanding queued log messages are flushed. This
ensures that such log messages are not being printed while the secondary CPU
may be using early_printk during early bringup.

Signed-of-by: Ian Campbell <ian.campbell@citrix.com>
Cc: Keir Fraser <keir@xen.org>
---
v2: improved commit message.
---
 xen/arch/arm/smpboot.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
index 7636ab8..e862477 100644
--- a/xen/arch/arm/smpboot.c
+++ b/xen/arch/arm/smpboot.c
@@ -28,6 +28,7 @@
 #include <xen/softirq.h>
 #include <xen/timer.h>
 #include <xen/irq.h>
+#include <xen/console.h>
 #include <asm/gic.h>
 
 cpumask_t cpu_online_map;
@@ -356,6 +357,8 @@ int __cpu_up(unsigned int cpu)
     if ( rc < 0 )
         return rc;
 
+    console_start_sync(); /* Secondary may use early_printk */
+
     /* Tell the remote CPU which stack to boot on. */
     init_data.stack = idle_vcpu[cpu]->arch.stack;
 
@@ -368,6 +371,8 @@ int __cpu_up(unsigned int cpu)
 
     rc = arch_cpu_up(cpu);
 
+    console_end_sync();
+
     if ( rc < 0 )
     {
         printk("Failed to bring up CPU%d\n", cpu);
-- 
1.7.10.4

Re: [PATCH v3 11/13] xen: arm: enable synchronous console while starting secondary CPUs

[Julien Grall]

On 11/25/2013 11:07 AM, Ian Campbell wrote:
> Setting synchronous console ensures that any printk hits the buffer
> immediately and that any outstanding queued log messages are flushed. This
> ensures that such log messages are not being printed while the secondary CPU
> may be using early_printk during early bringup.
>
> Signed-of-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
> Cc: Keir Fraser <keir@xen.org>
> ---
> v2: improved commit message.
> ---
>   xen/arch/arm/smpboot.c |    5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c
> index 7636ab8..e862477 100644
> --- a/xen/arch/arm/smpboot.c
> +++ b/xen/arch/arm/smpboot.c
> @@ -28,6 +28,7 @@
>   #include <xen/softirq.h>
>   #include <xen/timer.h>
>   #include <xen/irq.h>
> +#include <xen/console.h>
>   #include <asm/gic.h>
>
>   cpumask_t cpu_online_map;
> @@ -356,6 +357,8 @@ int __cpu_up(unsigned int cpu)
>       if ( rc < 0 )
>           return rc;
>
> +    console_start_sync(); /* Secondary may use early_printk */
> +
>       /* Tell the remote CPU which stack to boot on. */
>       init_data.stack = idle_vcpu[cpu]->arch.stack;
>
> @@ -368,6 +371,8 @@ int __cpu_up(unsigned int cpu)
>
>       rc = arch_cpu_up(cpu);
>
> +    console_end_sync();
> +
>       if ( rc < 0 )
>       {
>           printk("Failed to bring up CPU%d\n", cpu);
>

-- 
Julien Grall

[PATCH v3 12/13] xen: arm: improve early memory map readability

[Ian Campbell]

Purely cosmetic, put a blank line after the early memory map to separate it
from the subsequent information. This looks better since the memory map is
preceded by a blank line too.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
 xen/common/device_tree.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c
index 44253da..943b181 100644
--- a/xen/common/device_tree.c
+++ b/xen/common/device_tree.c
@@ -452,6 +452,7 @@ static void __init early_print_info(void)
         early_printk(" RESVD[%d]: %"PRIpaddr" - %"PRIpaddr"\n",
                      i, s, e);
     }
+    early_printk("\n");
 }
 
 /**
-- 
1.7.10.4

[PATCH v3 13/13] xen: arm: handle 40-bit addresses in the p2m

[Ian Campbell]

On the X-gene platform there are resources up this high which must be mapped
to dom0.

Remove the first level page from the p2m->pages list since it is actually two
pages and must be freed as such. Do so in p2m_teardown.

I've also punted on the implementation of dump_p2m_lookup for high
addresses...

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v2:
Remove irrelevant commentary from commit message
No longer RFC
---
 xen/arch/arm/p2m.c |   60 +++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 48 insertions(+), 12 deletions(-)

diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
index 82dda65..af32511 100644
--- a/xen/arch/arm/p2m.c
+++ b/xen/arch/arm/p2m.c
@@ -7,6 +7,10 @@
 #include <asm/flushtlb.h>
 #include <asm/gic.h>
 
+/* First level P2M is 2 consecutive pages */
+#define P2M_FIRST_ORDER 1
+#define P2M_FIRST_ENTRIES (LPAE_ENTRIES<<P2M_FIRST_ORDER)
+
 void dump_p2m_lookup(struct domain *d, paddr_t addr)
 {
     struct p2m_domain *p2m = &d->arch.p2m;
@@ -14,6 +18,12 @@ void dump_p2m_lookup(struct domain *d, paddr_t addr)
 
     printk("dom%d IPA 0x%"PRIpaddr"\n", d->domain_id, addr);
 
+    if ( first_linear_offset(addr) > LPAE_ENTRIES )
+    {
+        printk("Cannot dump addresses in second of first level pages...\n");
+        return;
+    }
+
     printk("P2M @ %p mfn:0x%lx\n",
            p2m->first_level, page_to_mfn(p2m->first_level));
 
@@ -31,6 +41,30 @@ void p2m_load_VTTBR(struct domain *d)
     isb(); /* Ensure update is visible */
 }
 
+static int p2m_first_level_index(paddr_t addr)
+{
+    /*
+     * 1st pages are concatenated so zeroeth offset gives us the
+     * index of the 1st page
+     */
+    return zeroeth_table_offset(addr);
+}
+
+/*
+ * Map whichever of the first pages contain addr. The caller should
+ * then use first_table_offset as an index.
+ */
+static lpae_t *p2m_map_first(struct p2m_domain *p2m, paddr_t addr)
+{
+    struct page_info *page;
+
+    BUG_ON(first_linear_offset(addr) > P2M_FIRST_ENTRIES);
+
+    page = p2m->first_level + p2m_first_level_index(addr);
+
+    return __map_domain_page(page);
+}
+
 /*
  * Lookup the MFN corresponding to a domain's PFN.
  *
@@ -45,7 +79,7 @@ paddr_t p2m_lookup(struct domain *d, paddr_t paddr)
 
     spin_lock(&p2m->lock);
 
-    first = __map_domain_page(p2m->first_level);
+    first = p2m_map_first(p2m, paddr);
 
     pte = first[first_table_offset(paddr)];
     if ( !pte.p2m.valid || !pte.p2m.table )
@@ -135,18 +169,21 @@ static int create_p2m_entries(struct domain *d,
     struct p2m_domain *p2m = &d->arch.p2m;
     lpae_t *first = NULL, *second = NULL, *third = NULL;
     paddr_t addr;
-    unsigned long cur_first_offset = ~0, cur_second_offset = ~0;
+    unsigned long cur_first_page = ~0,
+                  cur_first_offset = ~0,
+                  cur_second_offset = ~0;
 
     spin_lock(&p2m->lock);
 
-    /* XXX Don't actually handle 40 bit guest physical addresses */
-    BUG_ON(start_gpaddr & 0x8000000000ULL);
-    BUG_ON(end_gpaddr   & 0x8000000000ULL);
-
-    first = __map_domain_page(p2m->first_level);
-
     for(addr = start_gpaddr; addr < end_gpaddr; addr += PAGE_SIZE)
     {
+        if ( cur_first_page != p2m_first_level_index(addr) )
+        {
+            if ( first ) unmap_domain_page(first);
+            first = p2m_map_first(p2m, addr);
+            cur_first_page = p2m_first_level_index(addr);
+        }
+
         if ( !first[first_table_offset(addr)].p2m.valid )
         {
             rc = p2m_create_table(d, &first[first_table_offset(addr)]);
@@ -279,15 +316,12 @@ int p2m_alloc_table(struct domain *d)
     struct page_info *page;
     void *p;
 
-    /* First level P2M is 2 consecutive pages */
-    page = alloc_domheap_pages(NULL, 1, 0);
+    page = alloc_domheap_pages(NULL, P2M_FIRST_ORDER, 0);
     if ( page == NULL )
         return -ENOMEM;
 
     spin_lock(&p2m->lock);
 
-    page_list_add(page, &p2m->pages);
-
     /* Clear both first level pages */
     p = __map_domain_page(page);
     clear_page(p);
@@ -380,6 +414,8 @@ void p2m_teardown(struct domain *d)
     while ( (pg = page_list_remove_head(&p2m->pages)) )
         free_domheap_page(pg);
 
+    free_domheap_pages(p2m->first_level, P2M_FIRST_ORDER);
+
     p2m->first_level = NULL;
 
     p2m_free_vmid(d);
-- 
1.7.10.4

Re: [PATCH v3 13/13] xen: arm: handle 40-bit addresses in the p2m

[Ian Campbell]

This is the only unacked patch in this series.

Stefano, you previously said that the patch looked fine but asked for
some changes to the commit message. Is this version OK?

On Mon, 2013-11-25 at 11:07 +0000, Ian Campbell wrote:
> On the X-gene platform there are resources up this high which must be mapped
> to dom0.
> 
> Remove the first level page from the p2m->pages list since it is actually two
> pages and must be freed as such. Do so in p2m_teardown.
> 
> I've also punted on the implementation of dump_p2m_lookup for high
> addresses...
> 
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> ---
> v2:
> Remove irrelevant commentary from commit message
> No longer RFC
> ---
>  xen/arch/arm/p2m.c |   60 +++++++++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 48 insertions(+), 12 deletions(-)
> 
> diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c
> index 82dda65..af32511 100644
> --- a/xen/arch/arm/p2m.c
> +++ b/xen/arch/arm/p2m.c
> @@ -7,6 +7,10 @@
>  #include <asm/flushtlb.h>
>  #include <asm/gic.h>
>  
> +/* First level P2M is 2 consecutive pages */
> +#define P2M_FIRST_ORDER 1
> +#define P2M_FIRST_ENTRIES (LPAE_ENTRIES<<P2M_FIRST_ORDER)
> +
>  void dump_p2m_lookup(struct domain *d, paddr_t addr)
>  {
>      struct p2m_domain *p2m = &d->arch.p2m;
> @@ -14,6 +18,12 @@ void dump_p2m_lookup(struct domain *d, paddr_t addr)
>  
>      printk("dom%d IPA 0x%"PRIpaddr"\n", d->domain_id, addr);
>  
> +    if ( first_linear_offset(addr) > LPAE_ENTRIES )
> +    {
> +        printk("Cannot dump addresses in second of first level pages...\n");
> +        return;
> +    }
> +
>      printk("P2M @ %p mfn:0x%lx\n",
>             p2m->first_level, page_to_mfn(p2m->first_level));
>  
> @@ -31,6 +41,30 @@ void p2m_load_VTTBR(struct domain *d)
>      isb(); /* Ensure update is visible */
>  }
>  
> +static int p2m_first_level_index(paddr_t addr)
> +{
> +    /*
> +     * 1st pages are concatenated so zeroeth offset gives us the
> +     * index of the 1st page
> +     */
> +    return zeroeth_table_offset(addr);
> +}
> +
> +/*
> + * Map whichever of the first pages contain addr. The caller should
> + * then use first_table_offset as an index.
> + */
> +static lpae_t *p2m_map_first(struct p2m_domain *p2m, paddr_t addr)
> +{
> +    struct page_info *page;
> +
> +    BUG_ON(first_linear_offset(addr) > P2M_FIRST_ENTRIES);
> +
> +    page = p2m->first_level + p2m_first_level_index(addr);
> +
> +    return __map_domain_page(page);
> +}
> +
>  /*
>   * Lookup the MFN corresponding to a domain's PFN.
>   *
> @@ -45,7 +79,7 @@ paddr_t p2m_lookup(struct domain *d, paddr_t paddr)
>  
>      spin_lock(&p2m->lock);
>  
> -    first = __map_domain_page(p2m->first_level);
> +    first = p2m_map_first(p2m, paddr);
>  
>      pte = first[first_table_offset(paddr)];
>      if ( !pte.p2m.valid || !pte.p2m.table )
> @@ -135,18 +169,21 @@ static int create_p2m_entries(struct domain *d,
>      struct p2m_domain *p2m = &d->arch.p2m;
>      lpae_t *first = NULL, *second = NULL, *third = NULL;
>      paddr_t addr;
> -    unsigned long cur_first_offset = ~0, cur_second_offset = ~0;
> +    unsigned long cur_first_page = ~0,
> +                  cur_first_offset = ~0,
> +                  cur_second_offset = ~0;
>  
>      spin_lock(&p2m->lock);
>  
> -    /* XXX Don't actually handle 40 bit guest physical addresses */
> -    BUG_ON(start_gpaddr & 0x8000000000ULL);
> -    BUG_ON(end_gpaddr   & 0x8000000000ULL);
> -
> -    first = __map_domain_page(p2m->first_level);
> -
>      for(addr = start_gpaddr; addr < end_gpaddr; addr += PAGE_SIZE)
>      {
> +        if ( cur_first_page != p2m_first_level_index(addr) )
> +        {
> +            if ( first ) unmap_domain_page(first);
> +            first = p2m_map_first(p2m, addr);
> +            cur_first_page = p2m_first_level_index(addr);
> +        }
> +
>          if ( !first[first_table_offset(addr)].p2m.valid )
>          {
>              rc = p2m_create_table(d, &first[first_table_offset(addr)]);
> @@ -279,15 +316,12 @@ int p2m_alloc_table(struct domain *d)
>      struct page_info *page;
>      void *p;
>  
> -    /* First level P2M is 2 consecutive pages */
> -    page = alloc_domheap_pages(NULL, 1, 0);
> +    page = alloc_domheap_pages(NULL, P2M_FIRST_ORDER, 0);
>      if ( page == NULL )
>          return -ENOMEM;
>  
>      spin_lock(&p2m->lock);
>  
> -    page_list_add(page, &p2m->pages);
> -
>      /* Clear both first level pages */
>      p = __map_domain_page(page);
>      clear_page(p);
> @@ -380,6 +414,8 @@ void p2m_teardown(struct domain *d)
>      while ( (pg = page_list_remove_head(&p2m->pages)) )
>          free_domheap_page(pg);
>  
> +    free_domheap_pages(p2m->first_level, P2M_FIRST_ORDER);
> +
>      p2m->first_level = NULL;
>  
>      p2m_free_vmid(d);