Re: [PATCH 5/6] iommu/tegra124: smmu: {TLB,PTC} reset value per SoC

[Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>]

On 12/05/2013 05:25 AM, Hiroshi Doyu wrote:
> T124 has some new register bits in {TLB,PTC}_CONFIG:
> 
> - TLB_RR_ARB and PTC_REQ_LIMIT
> - TLB_ACTIVE_LINES 0x20 instead of 0x10
> 
> They are defined as platform data now.

> diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c

> @@ -239,6 +240,8 @@ struct smmu_device {
>  	struct page *avp_vector_page;	/* dummy page shared by all AS's */
>  
>  	int nr_xlats;		/* number of translation_enable registers */
> +	u32 tlb_reset;		/* TLB config reset value */
> +	u32 ptc_reset;		/* PTC config reset value */

> @@ -1320,6 +1327,10 @@ static int tegra_smmu_probe(struct platform_device *pdev)

> +	smmu->tlb_reset = (pdata && pdata->tlb_reset) ? pdata->tlb_reset :
> +		(SMMU_TLB_CONFIG_RESET_VAL | 0x10);
> +	smmu->ptc_reset = (pdata && pdata->ptc_reset) ? pdata->ptc_reset :
> +		(SMMU_PTC_CONFIG_RESET_VAL | SMMU_PTC_REQ_LIMIT);

These two parts of this patch could be removed, given my suggestions re:
patch 3/6.