Re: [PATCH 4/6] iommu/tegra124: smmu: support more than 32 bit pa

[Mark Zhang <nvmarkzhang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

On 01/08/2014 09:45 PM, Thierry Reding wrote:
> On Tue, Jan 07, 2014 at 01:25:37PM +0800, Mark Zhang wrote:
>> On 12/05/2013 08:25 PM, Hiroshi Doyu wrote:
> [...]
>>> @@ -526,6 +530,21 @@ static int smmu_setup_regs(struct smmu_device *smmu)
>>>  	return 0;
>>>  }
>>>  
>>> +static void flush_ptc_by_addr(struct smmu_device *smmu, unsigned long *pte,
>>> +			      struct page *page)
>>> +{
>>> +	u32 val;
>>> +
>>> +	val = VA_PAGE_TO_PA_HI(pte, page);
>>> +	if (val)
>>> +		smmu_write(smmu, val, SMMU_PTC_FLUSH_1);
>>> +
>>
>> This is not correct, according to my tests. We should write
>> "SMMU_PTC_FLUSH_1" even when the "val" is zero.
>>
>> So I just copied Pavan's original work here, after applied this, the
>> SMMU works correctly:
>>
>> -       val = VA_PAGE_TO_PA_HI(pte, page);
>> -       if (val)
>> +       if (!pte) {
>> +               smmu_write(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
>> +               return;
>> +       }
>> +
>> +       if (of_machine_is_compatible("nvidia,tegra124")) {
> 
> This check should be replaced by some flag so we don't have to compare
> strings every time the PTC is flushed.
> 

Yes, I believe Hiroshi will consider this in his v8 series.

Mark
> Thierry
>