Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras <Markos.Chandras@imgtec.com>]

Hi Sergei,

On 01/29/2014 01:31 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 29-01-2014 17:10, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> This patch is for the upstream-sfr/mips-for-linux-next tree
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..e790524 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>       case CPU_PROAPTIV:
>>           if (current_cpu_type() == CPU_74K)
>>               alias_74k_erratum(c);
>> -        if ((read_c0_config7() & (1 << 16))) {
>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>> +            if (c->icache.waysize > PAGE_SIZE)
>
>     Why not fold these to a single *if*?
I suppose I could do that. Thanks

>
>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>> +        if (read_c0_config7() & MIPS_CONF7_AR) {
>
>     You didn't document this change. Ideally, it should be in a separate
> patch.

Nothing has changed. Instead of using the '16' magic value, I just 
documented that bit along with the IAR one.

-- 
markos