* [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 13:10 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 13:10 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
This patch is for the upstream-sfr/mips-for-linux-next tree
---
arch/mips/include/asm/mipsregs.h | 3 +++
arch/mips/mm/c-r4k.c | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..e790524 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
case CPU_PROAPTIV:
if (current_cpu_type() == CPU_74K)
alias_74k_erratum(c);
- if ((read_c0_config7() & (1 << 16))) {
+ if (!(read_c0_config7() & MIPS_CONF7_IAR))
+ if (c->icache.waysize > PAGE_SIZE)
+ c->icache.flags |= MIPS_CACHE_ALIASES;
+ if (read_c0_config7() & MIPS_CONF7_AR) {
/* effectively physically indexed dcache,
thus no virtual aliases. */
c->dcache.flags |= MIPS_CACHE_PINDEX;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 13:10 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 13:10 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
This patch is for the upstream-sfr/mips-for-linux-next tree
---
arch/mips/include/asm/mipsregs.h | 3 +++
arch/mips/mm/c-r4k.c | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..e790524 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
case CPU_PROAPTIV:
if (current_cpu_type() == CPU_74K)
alias_74k_erratum(c);
- if ((read_c0_config7() & (1 << 16))) {
+ if (!(read_c0_config7() & MIPS_CONF7_IAR))
+ if (c->icache.waysize > PAGE_SIZE)
+ c->icache.flags |= MIPS_CACHE_ALIASES;
+ if (read_c0_config7() & MIPS_CONF7_AR) {
/* effectively physically indexed dcache,
thus no virtual aliases. */
c->dcache.flags |= MIPS_CACHE_PINDEX;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
2014-01-29 13:10 ` Markos Chandras
(?)
@ 2014-01-29 13:31 ` Sergei Shtylyov
2014-01-29 13:41 ` Markos Chandras
-1 siblings, 1 reply; 14+ messages in thread
From: Sergei Shtylyov @ 2014-01-29 13:31 UTC (permalink / raw)
To: Markos Chandras, linux-mips
Hello.
On 29-01-2014 17:10, Markos Chandras wrote:
> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> has hardware support to remove instruction cache aliasing.
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
> This patch is for the upstream-sfr/mips-for-linux-next tree
[...]
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 13b549a..e790524 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
> case CPU_PROAPTIV:
> if (current_cpu_type() == CPU_74K)
> alias_74k_erratum(c);
> - if ((read_c0_config7() & (1 << 16))) {
> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
> + if (c->icache.waysize > PAGE_SIZE)
Why not fold these to a single *if*?
> + c->icache.flags |= MIPS_CACHE_ALIASES;
> + if (read_c0_config7() & MIPS_CONF7_AR) {
You didn't document this change. Ideally, it should be in a separate patch.
WBR, Sergei
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 13:41 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 13:41 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
Hi Sergei,
On 01/29/2014 01:31 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 29-01-2014 17:10, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> This patch is for the upstream-sfr/mips-for-linux-next tree
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..e790524 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>> case CPU_PROAPTIV:
>> if (current_cpu_type() == CPU_74K)
>> alias_74k_erratum(c);
>> - if ((read_c0_config7() & (1 << 16))) {
>> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
>> + if (c->icache.waysize > PAGE_SIZE)
>
> Why not fold these to a single *if*?
I suppose I could do that. Thanks
>
>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>> + if (read_c0_config7() & MIPS_CONF7_AR) {
>
> You didn't document this change. Ideally, it should be in a separate
> patch.
Nothing has changed. Instead of using the '16' magic value, I just
documented that bit along with the IAR one.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 13:41 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 13:41 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
Hi Sergei,
On 01/29/2014 01:31 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 29-01-2014 17:10, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> This patch is for the upstream-sfr/mips-for-linux-next tree
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..e790524 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>> case CPU_PROAPTIV:
>> if (current_cpu_type() == CPU_74K)
>> alias_74k_erratum(c);
>> - if ((read_c0_config7() & (1 << 16))) {
>> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
>> + if (c->icache.waysize > PAGE_SIZE)
>
> Why not fold these to a single *if*?
I suppose I could do that. Thanks
>
>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>> + if (read_c0_config7() & MIPS_CONF7_AR) {
>
> You didn't document this change. Ideally, it should be in a separate
> patch.
Nothing has changed. Instead of using the '16' magic value, I just
documented that bit along with the IAR one.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
2014-01-29 13:41 ` Markos Chandras
(?)
@ 2014-01-29 18:10 ` Sergei Shtylyov
2014-01-29 17:17 ` Markos Chandras
-1 siblings, 1 reply; 14+ messages in thread
From: Sergei Shtylyov @ 2014-01-29 18:10 UTC (permalink / raw)
To: Markos Chandras, linux-mips
Hello.
On 01/29/2014 04:41 PM, Markos Chandras wrote:
>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>> has hardware support to remove instruction cache aliasing.
>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>> ---
>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>> [...]
>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>> index 13b549a..e790524 100644
>>> --- a/arch/mips/mm/c-r4k.c
>>> +++ b/arch/mips/mm/c-r4k.c
>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>> case CPU_PROAPTIV:
>>> if (current_cpu_type() == CPU_74K)
>>> alias_74k_erratum(c);
>>> - if ((read_c0_config7() & (1 << 16))) {
>>> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>> + if (c->icache.waysize > PAGE_SIZE)
>> Why not fold these to a single *if*?
> I suppose I could do that. Thanks
>>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>>> + if (read_c0_config7() & MIPS_CONF7_AR) {
>> You didn't document this change. Ideally, it should be in a separate
>> patch.
> Nothing has changed. Instead of using the '16' magic value, I just documented
> that bit along with the IAR one.
You should have noted that in the changelog, at least.
WBR, Sergei
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 17:17 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 17:17 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
On 01/29/2014 06:10 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/29/2014 04:41 PM, Markos Chandras wrote:
>
>>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>>> has hardware support to remove instruction cache aliasing.
>
>>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>>> ---
>>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>>> [...]
>
>>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>>> index 13b549a..e790524 100644
>>>> --- a/arch/mips/mm/c-r4k.c
>>>> +++ b/arch/mips/mm/c-r4k.c
>>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>>> case CPU_PROAPTIV:
>>>> if (current_cpu_type() == CPU_74K)
>>>> alias_74k_erratum(c);
>>>> - if ((read_c0_config7() & (1 << 16))) {
>>>> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>>> + if (c->icache.waysize > PAGE_SIZE)
>
>>> Why not fold these to a single *if*?
>
>> I suppose I could do that. Thanks
>
>>>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>>>> + if (read_c0_config7() & MIPS_CONF7_AR) {
>
>>> You didn't document this change. Ideally, it should be in a separate
>>> patch.
>
>> Nothing has changed. Instead of using the '16' magic value, I just
>> documented
>> that bit along with the IAR one.
>
> You should have noted that in the changelog, at least.
>
> WBR, Sergei
>
>
Ok I will submit a v2 soon. Thanks for the review.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-29 17:17 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-29 17:17 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
On 01/29/2014 06:10 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/29/2014 04:41 PM, Markos Chandras wrote:
>
>>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>>> has hardware support to remove instruction cache aliasing.
>
>>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>>> ---
>>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>>> [...]
>
>>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>>> index 13b549a..e790524 100644
>>>> --- a/arch/mips/mm/c-r4k.c
>>>> +++ b/arch/mips/mm/c-r4k.c
>>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>>> case CPU_PROAPTIV:
>>>> if (current_cpu_type() == CPU_74K)
>>>> alias_74k_erratum(c);
>>>> - if ((read_c0_config7() & (1 << 16))) {
>>>> + if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>>> + if (c->icache.waysize > PAGE_SIZE)
>
>>> Why not fold these to a single *if*?
>
>> I suppose I could do that. Thanks
>
>>>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>>>> + if (read_c0_config7() & MIPS_CONF7_AR) {
>
>>> You didn't document this change. Ideally, it should be in a separate
>>> patch.
>
>> Nothing has changed. Instead of using the '16' magic value, I just
>> documented
>> that bit along with the IAR one.
>
> You should have noted that in the changelog, at least.
>
> WBR, Sergei
>
>
Ok I will submit a v2 soon. Thanks for the review.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-30 17:21 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-30 17:21 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
Changes since v1:
- Merge conditionals thanks to Sergei Shtylyov
- Improve commit message to mention that CONF7/AR has also been defined
thanks to Sergei Shtylyov
arch/mips/include/asm/mipsregs.h | 3 +++
arch/mips/mm/c-r4k.c | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..8017f6e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
case CPU_PROAPTIV:
if (current_cpu_type() == CPU_74K)
alias_74k_erratum(c);
- if ((read_c0_config7() & (1 << 16))) {
+ if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+ (c->icache.waysize > PAGE_SIZE))
+ c->icache.flags |= MIPS_CACHE_ALIASES;
+ if (read_c0_config7() & MIPS_CONF7_AR) {
/* effectively physically indexed dcache,
thus no virtual aliases. */
c->dcache.flags |= MIPS_CACHE_PINDEX;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-30 17:21 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-30 17:21 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
Changes since v1:
- Merge conditionals thanks to Sergei Shtylyov
- Improve commit message to mention that CONF7/AR has also been defined
thanks to Sergei Shtylyov
arch/mips/include/asm/mipsregs.h | 3 +++
arch/mips/mm/c-r4k.c | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..8017f6e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
case CPU_PROAPTIV:
if (current_cpu_type() == CPU_74K)
alias_74k_erratum(c);
- if ((read_c0_config7() & (1 << 16))) {
+ if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+ (c->icache.waysize > PAGE_SIZE))
+ c->icache.flags |= MIPS_CACHE_ALIASES;
+ if (read_c0_config7() & MIPS_CONF7_AR) {
/* effectively physically indexed dcache,
thus no virtual aliases. */
c->dcache.flags |= MIPS_CACHE_PINDEX;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
2014-01-30 17:21 ` Markos Chandras
(?)
@ 2014-01-30 18:33 ` Sergei Shtylyov
2014-01-30 17:35 ` Markos Chandras
-1 siblings, 1 reply; 14+ messages in thread
From: Sergei Shtylyov @ 2014-01-30 18:33 UTC (permalink / raw)
To: Markos Chandras, linux-mips
Hello.
On 01/30/2014 08:21 PM, Markos Chandras wrote:
> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> has hardware support to remove instruction cache aliasing.
> This also defines the CONF7/AR bit in order to avoid using
> the '16' magic number.
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
[...]
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 13b549a..8017f6e 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
> case CPU_PROAPTIV:
> if (current_cpu_type() == CPU_74K)
> alias_74k_erratum(c);
> - if ((read_c0_config7() & (1 << 16))) {
> + if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
> + (c->icache.waysize > PAGE_SIZE))
> + c->icache.flags |= MIPS_CACHE_ALIASES;
Sigh, you forgot to "outdent" this statement by a tab... :-(
WBR, Sergei
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-30 17:35 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-30 17:35 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
On 01/30/2014 06:33 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/30/2014 08:21 PM, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> This also defines the CONF7/AR bit in order to avoid using
>> the '16' magic number.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..8017f6e 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>> case CPU_PROAPTIV:
>> if (current_cpu_type() == CPU_74K)
>> alias_74k_erratum(c);
>> - if ((read_c0_config7() & (1 << 16))) {
>> + if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
>> + (c->icache.waysize > PAGE_SIZE))
>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>
> Sigh, you forgot to "outdent" this statement by a tab... :-(
>
> WBR, Sergei
>
Indeed I did :) I will make sure the one committed will be fixed properly.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
@ 2014-01-30 17:35 ` Markos Chandras
0 siblings, 0 replies; 14+ messages in thread
From: Markos Chandras @ 2014-01-30 17:35 UTC (permalink / raw)
To: Sergei Shtylyov, linux-mips
On 01/30/2014 06:33 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/30/2014 08:21 PM, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> This also defines the CONF7/AR bit in order to avoid using
>> the '16' magic number.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..8017f6e 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>> case CPU_PROAPTIV:
>> if (current_cpu_type() == CPU_74K)
>> alias_74k_erratum(c);
>> - if ((read_c0_config7() & (1 << 16))) {
>> + if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
>> + (c->icache.waysize > PAGE_SIZE))
>> + c->icache.flags |= MIPS_CACHE_ALIASES;
>
> Sigh, you forgot to "outdent" this statement by a tab... :-(
>
> WBR, Sergei
>
Indeed I did :) I will make sure the one committed will be fixed properly.
--
markos
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases
2014-01-30 17:35 ` Markos Chandras
(?)
@ 2014-02-04 15:57 ` Ralf Baechle
-1 siblings, 0 replies; 14+ messages in thread
From: Ralf Baechle @ 2014-02-04 15:57 UTC (permalink / raw)
To: Markos Chandras; +Cc: Sergei Shtylyov, linux-mips
On Thu, Jan 30, 2014 at 05:35:51PM +0000, Markos Chandras wrote:
> >>The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> >>has hardware support to remove instruction cache aliasing.
> >
> >>This also defines the CONF7/AR bit in order to avoid using
> >>the '16' magic number.
> >
> >>Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> >[...]
> >
> >>diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> >>index 13b549a..8017f6e 100644
> >>--- a/arch/mips/mm/c-r4k.c
> >>+++ b/arch/mips/mm/c-r4k.c
> >>@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
> >> case CPU_PROAPTIV:
> >> if (current_cpu_type() == CPU_74K)
> >> alias_74k_erratum(c);
> >>- if ((read_c0_config7() & (1 << 16))) {
> >>+ if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
> >>+ (c->icache.waysize > PAGE_SIZE))
> >>+ c->icache.flags |= MIPS_CACHE_ALIASES;
> >
> > Sigh, you forgot to "outdent" this statement by a tab... :-(
> >
> >WBR, Sergei
> >
> Indeed I did :) I will make sure the one committed will be fixed properly.
>
I fixed that in my commit along with the non-Linux-codingstyle compliant
comment.
Thanks,
Ralf
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2014-02-04 15:57 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-01-29 13:10 [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases Markos Chandras
2014-01-29 13:10 ` Markos Chandras
2014-01-29 13:31 ` Sergei Shtylyov
2014-01-29 13:41 ` Markos Chandras
2014-01-29 13:41 ` Markos Chandras
2014-01-29 18:10 ` Sergei Shtylyov
2014-01-29 17:17 ` Markos Chandras
2014-01-29 17:17 ` Markos Chandras
2014-01-30 17:21 ` [PATCH v2] " Markos Chandras
2014-01-30 17:21 ` Markos Chandras
2014-01-30 18:33 ` Sergei Shtylyov
2014-01-30 17:35 ` Markos Chandras
2014-01-30 17:35 ` Markos Chandras
2014-02-04 15:57 ` Ralf Baechle
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