[PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
This patch is for the upstream-sfr/mips-for-linux-next tree
---
 arch/mips/include/asm/mipsregs.h | 3 +++
 arch/mips/mm/c-r4k.c             | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..e790524 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
 	case CPU_PROAPTIV:
 		if (current_cpu_type() == CPU_74K)
 			alias_74k_erratum(c);
-		if ((read_c0_config7() & (1 << 16))) {
+		if (!(read_c0_config7() & MIPS_CONF7_IAR))
+			if (c->icache.waysize > PAGE_SIZE)
+				c->icache.flags |= MIPS_CACHE_ALIASES;
+		if (read_c0_config7() & MIPS_CONF7_AR) {
 			/* effectively physically indexed dcache,
 			   thus no virtual aliases. */
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
-- 
1.8.5.3

[PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
This patch is for the upstream-sfr/mips-for-linux-next tree
---
 arch/mips/include/asm/mipsregs.h | 3 +++
 arch/mips/mm/c-r4k.c             | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..e790524 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
 	case CPU_PROAPTIV:
 		if (current_cpu_type() == CPU_74K)
 			alias_74k_erratum(c);
-		if ((read_c0_config7() & (1 << 16))) {
+		if (!(read_c0_config7() & MIPS_CONF7_IAR))
+			if (c->icache.waysize > PAGE_SIZE)
+				c->icache.flags |= MIPS_CACHE_ALIASES;
+		if (read_c0_config7() & MIPS_CONF7_AR) {
 			/* effectively physically indexed dcache,
 			   thus no virtual aliases. */
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
-- 
1.8.5.3

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Sergei Shtylyov]

Hello.

On 29-01-2014 17:10, Markos Chandras wrote:

> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> has hardware support to remove instruction cache aliasing.

> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
> This patch is for the upstream-sfr/mips-for-linux-next tree
[...]

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 13b549a..e790524 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>   	case CPU_PROAPTIV:
>   		if (current_cpu_type() == CPU_74K)
>   			alias_74k_erratum(c);
> -		if ((read_c0_config7() & (1 << 16))) {
> +		if (!(read_c0_config7() & MIPS_CONF7_IAR))
> +			if (c->icache.waysize > PAGE_SIZE)

    Why not fold these to a single *if*?

> +				c->icache.flags |= MIPS_CACHE_ALIASES;
> +		if (read_c0_config7() & MIPS_CONF7_AR) {

    You didn't document this change. Ideally, it should be in a separate patch.

WBR, Sergei

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

Hi Sergei,

On 01/29/2014 01:31 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 29-01-2014 17:10, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> This patch is for the upstream-sfr/mips-for-linux-next tree
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..e790524 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>       case CPU_PROAPTIV:
>>           if (current_cpu_type() == CPU_74K)
>>               alias_74k_erratum(c);
>> -        if ((read_c0_config7() & (1 << 16))) {
>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>> +            if (c->icache.waysize > PAGE_SIZE)
>
>     Why not fold these to a single *if*?
I suppose I could do that. Thanks

>
>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>> +        if (read_c0_config7() & MIPS_CONF7_AR) {
>
>     You didn't document this change. Ideally, it should be in a separate
> patch.

Nothing has changed. Instead of using the '16' magic value, I just 
documented that bit along with the IAR one.

-- 
markos

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

Hi Sergei,

On 01/29/2014 01:31 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 29-01-2014 17:10, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>> ---
>> This patch is for the upstream-sfr/mips-for-linux-next tree
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..e790524 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>       case CPU_PROAPTIV:
>>           if (current_cpu_type() == CPU_74K)
>>               alias_74k_erratum(c);
>> -        if ((read_c0_config7() & (1 << 16))) {
>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>> +            if (c->icache.waysize > PAGE_SIZE)
>
>     Why not fold these to a single *if*?
I suppose I could do that. Thanks

>
>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>> +        if (read_c0_config7() & MIPS_CONF7_AR) {
>
>     You didn't document this change. Ideally, it should be in a separate
> patch.

Nothing has changed. Instead of using the '16' magic value, I just 
documented that bit along with the IAR one.

-- 
markos

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

On 01/29/2014 06:10 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/29/2014 04:41 PM, Markos Chandras wrote:
>
>>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>>> has hardware support to remove instruction cache aliasing.
>
>>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>>> ---
>>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>>> [...]
>
>>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>>> index 13b549a..e790524 100644
>>>> --- a/arch/mips/mm/c-r4k.c
>>>> +++ b/arch/mips/mm/c-r4k.c
>>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>>>       case CPU_PROAPTIV:
>>>>           if (current_cpu_type() == CPU_74K)
>>>>               alias_74k_erratum(c);
>>>> -        if ((read_c0_config7() & (1 << 16))) {
>>>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>>> +            if (c->icache.waysize > PAGE_SIZE)
>
>>>     Why not fold these to a single *if*?
>
>> I suppose I could do that. Thanks
>
>>>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>>>> +        if (read_c0_config7() & MIPS_CONF7_AR) {
>
>>>     You didn't document this change. Ideally, it should be in a separate
>>> patch.
>
>> Nothing has changed. Instead of using the '16' magic value, I just
>> documented
>> that bit along with the IAR one.
>
>     You should have noted that in the changelog, at least.
>
> WBR, Sergei
>
>

Ok I will submit a v2 soon. Thanks for the review.

-- 
markos

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

On 01/29/2014 06:10 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/29/2014 04:41 PM, Markos Chandras wrote:
>
>>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>>> has hardware support to remove instruction cache aliasing.
>
>>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>>> ---
>>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>>> [...]
>
>>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>>> index 13b549a..e790524 100644
>>>> --- a/arch/mips/mm/c-r4k.c
>>>> +++ b/arch/mips/mm/c-r4k.c
>>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>>>       case CPU_PROAPTIV:
>>>>           if (current_cpu_type() == CPU_74K)
>>>>               alias_74k_erratum(c);
>>>> -        if ((read_c0_config7() & (1 << 16))) {
>>>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>>> +            if (c->icache.waysize > PAGE_SIZE)
>
>>>     Why not fold these to a single *if*?
>
>> I suppose I could do that. Thanks
>
>>>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>>>> +        if (read_c0_config7() & MIPS_CONF7_AR) {
>
>>>     You didn't document this change. Ideally, it should be in a separate
>>> patch.
>
>> Nothing has changed. Instead of using the '16' magic value, I just
>> documented
>> that bit along with the IAR one.
>
>     You should have noted that in the changelog, at least.
>
> WBR, Sergei
>
>

Ok I will submit a v2 soon. Thanks for the review.

-- 
markos

Re: [PATCH] MIPS: mm: c-r4k: Detect instruction cache aliases

[Sergei Shtylyov]

Hello.

On 01/29/2014 04:41 PM, Markos Chandras wrote:

>>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>>> has hardware support to remove instruction cache aliasing.

>>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
>>> ---
>>> This patch is for the upstream-sfr/mips-for-linux-next tree
>> [...]

>>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>>> index 13b549a..e790524 100644
>>> --- a/arch/mips/mm/c-r4k.c
>>> +++ b/arch/mips/mm/c-r4k.c
>>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>>       case CPU_PROAPTIV:
>>>           if (current_cpu_type() == CPU_74K)
>>>               alias_74k_erratum(c);
>>> -        if ((read_c0_config7() & (1 << 16))) {
>>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR))
>>> +            if (c->icache.waysize > PAGE_SIZE)

>>     Why not fold these to a single *if*?

> I suppose I could do that. Thanks

>>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>>> +        if (read_c0_config7() & MIPS_CONF7_AR) {

>>     You didn't document this change. Ideally, it should be in a separate
>> patch.

> Nothing has changed. Instead of using the '16' magic value, I just documented
> that bit along with the IAR one.

    You should have noted that in the changelog, at least.

WBR, Sergei

[PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
Changes since v1:
- Merge conditionals thanks to Sergei Shtylyov
- Improve commit message to mention that CONF7/AR has also been defined
thanks to Sergei Shtylyov

 arch/mips/include/asm/mipsregs.h | 3 +++
 arch/mips/mm/c-r4k.c             | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..8017f6e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
 	case CPU_PROAPTIV:
 		if (current_cpu_type() == CPU_74K)
 			alias_74k_erratum(c);
-		if ((read_c0_config7() & (1 << 16))) {
+		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+		    (c->icache.waysize > PAGE_SIZE))
+				c->icache.flags |= MIPS_CACHE_ALIASES;
+		if (read_c0_config7() & MIPS_CONF7_AR) {
 			/* effectively physically indexed dcache,
 			   thus no virtual aliases. */
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
-- 
1.8.5.3

[PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.

This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
---
Changes since v1:
- Merge conditionals thanks to Sergei Shtylyov
- Improve commit message to mention that CONF7/AR has also been defined
thanks to Sergei Shtylyov

 arch/mips/include/asm/mipsregs.h | 3 +++
 arch/mips/mm/c-r4k.c             | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..0c74617 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -653,6 +653,9 @@
 
 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+
 /*  EntryHI bit definition */
 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 13b549a..8017f6e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
 	case CPU_PROAPTIV:
 		if (current_cpu_type() == CPU_74K)
 			alias_74k_erratum(c);
-		if ((read_c0_config7() & (1 << 16))) {
+		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
+		    (c->icache.waysize > PAGE_SIZE))
+				c->icache.flags |= MIPS_CACHE_ALIASES;
+		if (read_c0_config7() & MIPS_CONF7_AR) {
 			/* effectively physically indexed dcache,
 			   thus no virtual aliases. */
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
-- 
1.8.5.3

Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

On 01/30/2014 06:33 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/30/2014 08:21 PM, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> This also defines the CONF7/AR bit in order to avoid using
>> the '16' magic number.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..8017f6e 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>       case CPU_PROAPTIV:
>>           if (current_cpu_type() == CPU_74K)
>>               alias_74k_erratum(c);
>> -        if ((read_c0_config7() & (1 << 16))) {
>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
>> +            (c->icache.waysize > PAGE_SIZE))
>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>
>      Sigh, you forgot to "outdent" this statement by a tab... :-(
>
> WBR, Sergei
>
Indeed I did :) I will make sure the one committed will be fixed properly.

-- 
markos

Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Markos Chandras]

On 01/30/2014 06:33 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 01/30/2014 08:21 PM, Markos Chandras wrote:
>
>> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
>> has hardware support to remove instruction cache aliasing.
>
>> This also defines the CONF7/AR bit in order to avoid using
>> the '16' magic number.
>
>> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> [...]
>
>> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
>> index 13b549a..8017f6e 100644
>> --- a/arch/mips/mm/c-r4k.c
>> +++ b/arch/mips/mm/c-r4k.c
>> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>>       case CPU_PROAPTIV:
>>           if (current_cpu_type() == CPU_74K)
>>               alias_74k_erratum(c);
>> -        if ((read_c0_config7() & (1 << 16))) {
>> +        if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
>> +            (c->icache.waysize > PAGE_SIZE))
>> +                c->icache.flags |= MIPS_CACHE_ALIASES;
>
>      Sigh, you forgot to "outdent" this statement by a tab... :-(
>
> WBR, Sergei
>
Indeed I did :) I will make sure the one committed will be fixed properly.

-- 
markos

Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Sergei Shtylyov]

Hello.

On 01/30/2014 08:21 PM, Markos Chandras wrote:

> The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> has hardware support to remove instruction cache aliasing.

> This also defines the CONF7/AR bit in order to avoid using
> the '16' magic number.

> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
[...]

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 13b549a..8017f6e 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1110,7 +1110,10 @@ static void probe_pcache(void)
>   	case CPU_PROAPTIV:
>   		if (current_cpu_type() == CPU_74K)
>   			alias_74k_erratum(c);
> -		if ((read_c0_config7() & (1 << 16))) {
> +		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
> +		    (c->icache.waysize > PAGE_SIZE))
> +				c->icache.flags |= MIPS_CACHE_ALIASES;

     Sigh, you forgot to "outdent" this statement by a tab... :-(

WBR, Sergei

Re: [PATCH v2] MIPS: mm: c-r4k: Detect instruction cache aliases

[Ralf Baechle]

On Thu, Jan 30, 2014 at 05:35:51PM +0000, Markos Chandras wrote:

> >>The *Aptiv cores can use the CONF7/IAR bit to detect if the core
> >>has hardware support to remove instruction cache aliasing.
> >
> >>This also defines the CONF7/AR bit in order to avoid using
> >>the '16' magic number.
> >
> >>Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> >[...]
> >
> >>diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> >>index 13b549a..8017f6e 100644
> >>--- a/arch/mips/mm/c-r4k.c
> >>+++ b/arch/mips/mm/c-r4k.c
> >>@@ -1110,7 +1110,10 @@ static void probe_pcache(void)
> >>      case CPU_PROAPTIV:
> >>          if (current_cpu_type() == CPU_74K)
> >>              alias_74k_erratum(c);
> >>-        if ((read_c0_config7() & (1 << 16))) {
> >>+        if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
> >>+            (c->icache.waysize > PAGE_SIZE))
> >>+                c->icache.flags |= MIPS_CACHE_ALIASES;
> >
> >     Sigh, you forgot to "outdent" this statement by a tab... :-(
> >
> >WBR, Sergei
> >
> Indeed I did :) I will make sure the one committed will be fixed properly.
> 

I fixed that in my commit along with the non-Linux-codingstyle compliant
comment.

Thanks,

  Ralf