* [U-Boot] Fwd: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR [not found] <1392069354-24578-1-git-send-email-yorksun@freescale.com> @ 2014-02-10 21:58 ` York Sun [not found] ` <1392069354-24578-3-git-send-email-yorksun@freescale.com> 2014-02-13 3:13 ` [U-Boot] [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR FengHua 2 siblings, 0 replies; 4+ messages in thread From: York Sun @ 2014-02-10 21:58 UTC (permalink / raw) To: u-boot -------- Original Message -------- Subject: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR Date: Mon, 10 Feb 2014 13:55:52 -0800 From: York Sun <yorksun@freescale.com> To: <albert.u.boot@aribaud.net> CC: <scottwood@freescale.com>, York Sun <yorksun@freescale.com>, David Feng <fenghua@phytium.com.cn> Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with sub-architecture. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> --- arch/arm/cpu/armv8/cache_v8.c | 22 +++++++++++++++++++--- arch/arm/cpu/armv8/start.S | 22 ---------------------- 2 files changed, 19 insertions(+), 25 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 131fdab..7acae1b 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -45,15 +45,31 @@ static void mmu_setup(void) /* load TTBR0 */ el = current_el(); - if (el == 1) + if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else if (el == 2) + asm volatile("msr tcr_el1, %0" + : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) + : "memory"); + asm volatile("msr mair_el1, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else if (el == 2) { asm volatile("msr ttbr0_el2, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else + asm volatile("msr tcr_el2, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el2, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else { asm volatile("msr ttbr0_el3, %0" : : "r" (gd->arch.tlb_addr) : "memory"); + asm volatile("msr tcr_el3, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el3, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index bcc2603..90daa4d 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -128,28 +128,6 @@ ENTRY(c_runtime_cpu_setup) isb sy #endif -#ifndef CONFIG_SYS_DCACHE_OFF - /* - * Setup MAIR and TCR. - */ - ldr x0, =MEMORY_ATTRIBUTES - ldr x1, =TCR_FLAGS - - switch_el x2, 3f, 2f, 1f -3: orr x1, x1, TCR_EL3_IPS_BITS - msr mair_el3, x0 - msr tcr_el3, x1 - b 0f -2: orr x1, x1, TCR_EL2_IPS_BITS - msr mair_el2, x0 - msr tcr_el2, x1 - b 0f -1: orr x1, x1, TCR_EL1_IPS_BITS - msr mair_el1, x0 - msr tcr_el1, x1 -0: -#endif - /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <1392069354-24578-3-git-send-email-yorksun@freescale.com>]
* [U-Boot] Fwd: [PATCH 3/3] armv8/cache: Change cache invalidate and flush function [not found] ` <1392069354-24578-3-git-send-email-yorksun@freescale.com> @ 2014-02-10 21:58 ` York Sun [not found] ` <4997fa.12c4.144296ae1fc.Coremail.fenghua@phytium.com.cn> 1 sibling, 0 replies; 4+ messages in thread From: York Sun @ 2014-02-10 21:58 UTC (permalink / raw) To: u-boot -------- Original Message -------- Subject: [PATCH 3/3] armv8/cache: Change cache invalidate and flush function Date: Mon, 10 Feb 2014 13:55:54 -0800 From: York Sun <yorksun@freescale.com> To: <albert.u.boot@aribaud.net> CC: <scottwood@freescale.com>, York Sun <yorksun@freescale.com>, David Feng <fenghua@phytium.com.cn> When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> --- arch/arm/cpu/armv8/cache.S | 53 +++++++++++++++++++++++++++++------------ arch/arm/cpu/armv8/cache_v8.c | 2 +- arch/arm/cpu/armv8/start.S | 2 +- arch/arm/include/asm/system.h | 1 + 4 files changed, 41 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 546a83e..249799c 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -19,11 +19,12 @@ * clean and invalidate one level cache. * * x0: cache level - * x1~x9: clobbered + * x1: 0 flush & invalidate, 1 invalidate only + * x2~x9: clobbered */ ENTRY(__asm_flush_dcache_level) - lsl x1, x0, #1 - msr csselr_el1, x1 /* select cache level */ + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ @@ -35,7 +36,7 @@ ENTRY(__asm_flush_dcache_level) clz w5, w4 /* bit position of #ways */ mov x4, #0x7fff and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ - /* x1 <- cache level << 1 */ + /* x12 <- cache level << 1 */ /* x2 <- line length offset */ /* x3 <- number of cache ways - 1 */ /* x4 <- number of cache sets - 1 */ @@ -45,11 +46,14 @@ loop_set: mov x6, x3 /* x6 <- working copy of #ways */ loop_way: lsl x7, x6, x5 - orr x9, x1, x7 /* map way and level to cisw value */ + orr x9, x12, x7 /* map way and level to cisw value */ lsl x7, x4, x2 orr x9, x9, x7 /* map set number to cisw value */ - dc cisw, x9 /* clean & invalidate by set/way */ - subs x6, x6, #1 /* decrement the way */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ b.ge loop_way subs x4, x4, #1 /* decrement the set */ b.ge loop_set @@ -58,11 +62,14 @@ loop_way: ENDPROC(__asm_flush_dcache_level) /* - * void __asm_flush_dcache_all(void) + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 flush & invalidate, 1 invalidate only * * clean and invalidate all data cache by SET/WAY. */ -ENTRY(__asm_flush_dcache_all) +ENTRY(__asm_dcache_all) + mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ lsr x11, x10, #24 @@ -76,13 +83,13 @@ ENTRY(__asm_flush_dcache_all) /* x15 <- return address */ loop_level: - lsl x1, x0, #1 - add x1, x1, x0 /* x0 <- tripled cache level */ - lsr x1, x10, x1 - and x1, x1, #7 /* x1 <- cache type */ - cmp x1, #2 + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level + bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0 @@ -96,8 +103,24 @@ skip: finished: ret +ENDPROC(__asm_dcache_all) + +ENTRY(__asm_flush_dcache_all) + mov x16, lr + mov x0, #0 + bl __asm_dcache_all + mov lr, x16 + ret ENDPROC(__asm_flush_dcache_all) +ENTRY(__asm_invalidate_dcache_all) + mov x16, lr + mov x0, #0xffff + bl __asm_dcache_all + mov lr, x16 + ret +ENDPROC(__asm_invalidate_dcache_all) + /* * void __asm_flush_dcache_range(start, end) * diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 7acae1b..3ce391ea 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -80,7 +80,7 @@ static void mmu_setup(void) */ void invalidate_dcache_all(void) { - __asm_flush_dcache_all(); + __asm_invalidate_dcache_all(); } /* diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e70c51d..7b9ac21 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -65,9 +65,9 @@ reset: 0: /* Cache/BPB/TLB Invalidate */ - bl __asm_flush_dcache_all /* dCache clean&invalidate */ bl __asm_invalidate_icache_all /* iCache invalidate */ bl __asm_invalidate_tlb_all /* invalidate TLBs */ + /* d-cache invalidation is done before enabling d-cache */ /* Processor specific initialization */ bl lowlevel_init diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4178f8c..74ee9a4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -66,6 +66,7 @@ static inline void set_sctlr(unsigned int val) } void __asm_flush_dcache_all(void); +void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 4+ messages in thread
[parent not found: <4997fa.12c4.144296ae1fc.Coremail.fenghua@phytium.com.cn>]
* [U-Boot] [PATCH 3/3] armv8/cache: Change cache invalidate and flush function [not found] ` <4997fa.12c4.144296ae1fc.Coremail.fenghua@phytium.com.cn> @ 2014-02-13 17:29 ` York Sun 0 siblings, 0 replies; 4+ messages in thread From: York Sun @ 2014-02-13 17:29 UTC (permalink / raw) To: u-boot On 02/12/2014 08:04 PM, FengHua wrote: > > > >> -----Original Messages----- >> From: "York Sun" <yorksun@freescale.com> >> Sent Time: 2014-02-11 05:55:54 (Tuesday) >> To: albert.u.boot at aribaud.net >> Cc: scottwood at freescale.com, "York Sun" <yorksun@freescale.com>, "David Feng" <fenghua@phytium.com.cn> >> Subject: [PATCH 3/3] armv8/cache: Change cache invalidate and flush function >> <snip> >> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S >> index e70c51d..7b9ac21 100644 >> --- a/arch/arm/cpu/armv8/start.S >> +++ b/arch/arm/cpu/armv8/start.S >> @@ -65,9 +65,9 @@ reset: >> 0: >> >> /* Cache/BPB/TLB Invalidate */ >> - bl __asm_flush_dcache_all /* dCache clean&invalidate */ >> bl __asm_invalidate_icache_all /* iCache invalidate */ >> bl __asm_invalidate_tlb_all /* invalidate TLBs */ > How about remove the icache and tlb invalidate operations? We can move the calling of __asm_invalidate_tlb_all to before mmu_setup, and move calling __asm_invalidate_icache_all to before icache_enable. But leaving them here makes sense as the initial setup procedure. And more important, it won't get lost. These functions run very fast, not like invalidating dcache. York ^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR [not found] <1392069354-24578-1-git-send-email-yorksun@freescale.com> 2014-02-10 21:58 ` [U-Boot] Fwd: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR York Sun [not found] ` <1392069354-24578-3-git-send-email-yorksun@freescale.com> @ 2014-02-13 3:13 ` FengHua 2 siblings, 0 replies; 4+ messages in thread From: FengHua @ 2014-02-13 3:13 UTC (permalink / raw) To: u-boot hi York, > -----Original Messages----- > From: "York Sun" <yorksun@freescale.com> > Sent Time: 2014-02-11 05:55:52 (Tuesday) > To: albert.u.boot at aribaud.net > Cc: scottwood at freescale.com, "York Sun" <yorksun@freescale.com>, "David Feng" <fenghua@phytium.com.cn> > Subject: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR > > Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with > sub-architecture. > > Signed-off-by: York Sun <yorksun@freescale.com> > CC: David Feng <fenghua@phytium.com.cn> > --- > arch/arm/cpu/armv8/cache_v8.c | 22 +++++++++++++++++++--- > arch/arm/cpu/armv8/start.S | 22 ---------------------- > 2 files changed, 19 insertions(+), 25 deletions(-) > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c > index 131fdab..7acae1b 100644 > --- a/arch/arm/cpu/armv8/cache_v8.c > +++ b/arch/arm/cpu/armv8/cache_v8.c > @@ -45,15 +45,31 @@ static void mmu_setup(void) > > /* load TTBR0 */ > el = current_el(); > - if (el == 1) > + if (el == 1) { > asm volatile("msr ttbr0_el1, %0" > : : "r" (gd->arch.tlb_addr) : "memory"); > - else if (el == 2) > + asm volatile("msr tcr_el1, %0" > + : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) > + : "memory"); > + asm volatile("msr mair_el1, %0" > + : : "r" (MEMORY_ATTRIBUTES) : "memory"); > + } else if (el == 2) { > asm volatile("msr ttbr0_el2, %0" > : : "r" (gd->arch.tlb_addr) : "memory"); > - else > + asm volatile("msr tcr_el2, %0" > + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) > + : "memory"); > + asm volatile("msr mair_el2, %0" > + : : "r" (MEMORY_ATTRIBUTES) : "memory"); > + } else { > asm volatile("msr ttbr0_el3, %0" > : : "r" (gd->arch.tlb_addr) : "memory"); > + asm volatile("msr tcr_el3, %0" > + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) > + : "memory"); > + asm volatile("msr mair_el3, %0" > + : : "r" (MEMORY_ATTRIBUTES) : "memory"); > + } > > /* enable the mmu */ > set_sctlr(get_sctlr() | CR_M); > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > index bcc2603..90daa4d 100644 > --- a/arch/arm/cpu/armv8/start.S > +++ b/arch/arm/cpu/armv8/start.S > @@ -128,28 +128,6 @@ ENTRY(c_runtime_cpu_setup) > isb sy > #endif > > -#ifndef CONFIG_SYS_DCACHE_OFF > - /* > - * Setup MAIR and TCR. > - */ > - ldr x0, =MEMORY_ATTRIBUTES > - ldr x1, =TCR_FLAGS > - > - switch_el x2, 3f, 2f, 1f > -3: orr x1, x1, TCR_EL3_IPS_BITS > - msr mair_el3, x0 > - msr tcr_el3, x1 > - b 0f > -2: orr x1, x1, TCR_EL2_IPS_BITS > - msr mair_el2, x0 > - msr tcr_el2, x1 > - b 0f > -1: orr x1, x1, TCR_EL1_IPS_BITS > - msr mair_el1, x0 > - msr tcr_el1, x1 > -0: > -#endif > - > /* Relocate vBAR */ > adr x0, vectors > switch_el x1, 3f, 2f, 1f > -- > 1.7.9.5 > This will be better. Acked. ^ permalink raw reply [flat|nested] 4+ messages in thread
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2014-02-10 21:58 ` [U-Boot] Fwd: [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR York Sun
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2014-02-10 21:58 ` [U-Boot] Fwd: [PATCH 3/3] armv8/cache: Change cache invalidate and flush function York Sun
[not found] ` <4997fa.12c4.144296ae1fc.Coremail.fenghua@phytium.com.cn>
2014-02-13 17:29 ` [U-Boot] " York Sun
2014-02-13 3:13 ` [U-Boot] [PATCH 1/3] armv8/cache: Consolidate setting for MAIR and TCR FengHua
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