Re: [PATCH] I/O space write barrier

[Roland Dreier <roland@topspin.com>]

    Benjamin> I don't understand that neither. You can never guarantee
    Benjamin> any ordering between writes from different CPUs unless
    Benjamin> you have a sinlock. If you have an ordering problem with
    Benjamin> spinlocks, then it's a totally different issue, a bit
    Benjamin> more like MMIO vs. cacheable mem that we have on PPC. If
    Benjamin> this is the problem you are trying to chase, then we
    Benjamin> could use such a barrier on ppc too and make it a hard
    Benjamin> sync, but it has nothing to do with the write barrier we
    Benjamin> already have in our IO accessors...

As I understand it, the problem is that on some Itanium boxes, it's
possible to have the following code run:

	CPU 1				CPU 2
    spin_lock(&devlock);
    writel(foo);
    spin_unlock(&devlock);

				    spin_lock(&devlock);
				    writel(bar);
				    spin_unlock(&devlock);

and still have bar arrive at the device before foo.  One possibility
would be to add a read after the writel() to flush the posted write.
The proposed mmiowb() function is somewhat lighter weight -- it
guarantees that later writes will not hit the device before any writes
already issued, but it doesn't say anything about writes making it all
the way to the device.

I could be wrong but I think that the eieio in the ppc IO write
functions should be strong enough that mmiowb() can be a no-op.

By the way, are the ordering rules different for ppc32 and ppc64?  I
notice that the ppc32 out_xxx() functions do eieio while the ppc64
versions do a full sync.

Thanks,
  Roland