From: Stephen Warren <swarren@wwwdotorg.org>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Russell King <linux@arm.linux.org.uk>,
Thierry Reding <thierry.reding@gmail.com>,
Andrew Morton <akpm@linux-foundation.org>,
Linus Walleij <linus.walleij@linaro.org>,
Wolfram Sang <wsa@the-dreams.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 3/5] misc: fuse: Add efuse driver for Tegra
Date: Fri, 30 May 2014 10:12:43 -0600 [thread overview]
Message-ID: <5388ADFB.1060505@wwwdotorg.org> (raw)
In-Reply-To: <20140530113618.GQ5961@tbergstrom-lnx.Nvidia.com>
On 05/30/2014 05:36 AM, Peter De Schrijver wrote:
> On Thu, May 29, 2014 at 09:04:33PM +0200, Stephen Warren wrote:
>> On 05/28/2014 06:54 AM, Peter De Schrijver wrote:
>>> Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124.
>>
>>> diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse
>>
>>> +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
>>> + and Tegra124 SoC's from NVIDIA. The efuses contain write once
>>> + data programmed at the factory. The data is layed out in 32bit
>>> + words in LSB first formnat. The number of valid bits depends
>>
>> s/formnat/format/
>>
>>> + on the word and the SoC. The mapping is as follows:
>>> +
>>> + For Tegra20:
>>> + Word 0 - 1 : bit 0
>>> + Word 2 : unused
>>> + Word 3 : bits 0 - 31
>>> + Word 4 : bits 0 - 7
>>
>> Do we really need these long tables that indicate which bits are used?
>> As I mentioned before, when I asked for documentation of the format of
>> these files, all I wanted was a brief not indicating that the data was
>> binary, and that each bit potentially represents a fuse... Either we
>> should leave it at that, or actually document what each bit represents,
>> which would hopefully be a pointless duplication of the TRM.
>
> Some fuses are OEM defined, so there is no way to document all fuses there.
> Would you be ok with just dropping the tables then?
Yes.
> So, the description would become:
>
> Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
> and Tegra124 SoC's from NVIDIA. The efuses contain write once
> data programmed at the factory. The data is layed out in 32bit
> words in LSB first format. The number of valid bits depends
> on the word and the SoC.
Almost. That's still missing the key information that the data format is
one bit per fuse, and the ordering. Perhaps change from:
The data is layed out in 32bit words in LSB first format.
to:
The data is laid out in 32bit words in LSB first format. Each bit
represents a single fuse value. Bits order/assignment exactly matches
the HW registers, including any unused bits.
WARNING: multiple messages have this Message-ID (diff)
From: swarren@wwwdotorg.org (Stephen Warren)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 3/5] misc: fuse: Add efuse driver for Tegra
Date: Fri, 30 May 2014 10:12:43 -0600 [thread overview]
Message-ID: <5388ADFB.1060505@wwwdotorg.org> (raw)
In-Reply-To: <20140530113618.GQ5961@tbergstrom-lnx.Nvidia.com>
On 05/30/2014 05:36 AM, Peter De Schrijver wrote:
> On Thu, May 29, 2014 at 09:04:33PM +0200, Stephen Warren wrote:
>> On 05/28/2014 06:54 AM, Peter De Schrijver wrote:
>>> Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124.
>>
>>> diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse
>>
>>> +Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
>>> + and Tegra124 SoC's from NVIDIA. The efuses contain write once
>>> + data programmed at the factory. The data is layed out in 32bit
>>> + words in LSB first formnat. The number of valid bits depends
>>
>> s/formnat/format/
>>
>>> + on the word and the SoC. The mapping is as follows:
>>> +
>>> + For Tegra20:
>>> + Word 0 - 1 : bit 0
>>> + Word 2 : unused
>>> + Word 3 : bits 0 - 31
>>> + Word 4 : bits 0 - 7
>>
>> Do we really need these long tables that indicate which bits are used?
>> As I mentioned before, when I asked for documentation of the format of
>> these files, all I wanted was a brief not indicating that the data was
>> binary, and that each bit potentially represents a fuse... Either we
>> should leave it at that, or actually document what each bit represents,
>> which would hopefully be a pointless duplication of the TRM.
>
> Some fuses are OEM defined, so there is no way to document all fuses there.
> Would you be ok with just dropping the tables then?
Yes.
> So, the description would become:
>
> Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
> and Tegra124 SoC's from NVIDIA. The efuses contain write once
> data programmed at the factory. The data is layed out in 32bit
> words in LSB first format. The number of valid bits depends
> on the word and the SoC.
Almost. That's still missing the key information that the data format is
one bit per fuse, and the ordering. Perhaps change from:
The data is layed out in 32bit words in LSB first format.
to:
The data is laid out in 32bit words in LSB first format. Each bit
represents a single fuse value. Bits order/assignment exactly matches
the HW registers, including any unused bits.
next prev parent reply other threads:[~2014-05-30 16:12 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-28 12:54 [PATCH v5 0/5] efuse driver for Tegra Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` [PATCH v5 1/5] ARM: tegra: export apb dma readl/writel Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` [PATCH v5 2/5] ARM: tegra: move fuse exports to tegra-soc.h Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
[not found] ` <1401281677-32110-3-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-29 19:01 ` Stephen Warren
2014-05-29 19:01 ` Stephen Warren
2014-05-29 19:01 ` Stephen Warren
2014-05-28 12:54 ` [PATCH v5 3/5] misc: fuse: Add efuse driver for Tegra Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-29 19:04 ` Stephen Warren
2014-05-29 19:04 ` Stephen Warren
2014-05-30 11:36 ` Peter De Schrijver
2014-05-30 11:36 ` Peter De Schrijver
2014-05-30 16:12 ` Stephen Warren [this message]
2014-05-30 16:12 ` Stephen Warren
2014-05-28 12:54 ` [PATCH v5 4/5] ARM: tegra: Add efuse and apbmisc bindings Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
[not found] ` <1401281677-32110-5-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-29 19:13 ` Stephen Warren
2014-05-29 19:13 ` Stephen Warren
2014-05-29 19:13 ` Stephen Warren
2014-05-28 12:54 ` [PATCH v5 5/5] ARM: tegra: build new fuse driver in drivers/misc Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
2014-05-28 12:54 ` Peter De Schrijver
[not found] ` <1401281677-32110-6-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-29 19:14 ` Stephen Warren
2014-05-29 19:14 ` Stephen Warren
2014-05-29 19:14 ` Stephen Warren
[not found] ` <1401281677-32110-1-git-send-email-pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-28 13:16 ` [PATCH v5 0/5] efuse driver for Tegra Andrew Morton
2014-05-28 13:16 ` Andrew Morton
2014-05-28 13:16 ` Andrew Morton
[not found] ` <20140528061645.252c2fbc.akpm-de/tnXTf+JLsfHDXvbKv3WD2FQJk+8+b@public.gmane.org>
2014-05-29 19:22 ` Stephen Warren
2014-05-29 19:22 ` Stephen Warren
2014-05-29 19:22 ` Stephen Warren
2014-05-29 19:01 ` Stephen Warren
2014-05-29 19:01 ` Stephen Warren
2014-05-29 19:01 ` Stephen Warren
[not found] ` <53878407.3050409-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-05-30 8:23 ` Peter De Schrijver
2014-05-30 8:23 ` Peter De Schrijver
2014-05-30 8:23 ` Peter De Schrijver
[not found] ` <20140530082356.GP5961-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2014-05-30 16:17 ` Stephen Warren
2014-05-30 16:17 ` Stephen Warren
2014-05-30 16:17 ` Stephen Warren
2014-06-02 8:27 ` Peter De Schrijver
2014-06-02 8:27 ` Peter De Schrijver
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