* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 9:38 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 9:38 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, linux,
sebastian.hesselbarth, alexandre.belloni, antoine.tenart
Cc: devicetree, linux-arm-kernel, linux-kernel, Jisheng Zhang
For all BG2Q SoCs, 2 cycles is the best/correct value
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm/boot/dts/berlin2q.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 635a16a..3f95dc5 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -90,6 +90,8 @@
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-level = <2>;
+ arm,data-latency = <2 2 2>;
+ arm,tag-latency = <2 2 2>;
};
scu: snoop-control-unit@ad0000 {
--
2.0.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 9:38 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 9:38 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, linux,
sebastian.hesselbarth, alexandre.belloni, antoine.tenart
Cc: devicetree, linux-arm-kernel, linux-kernel, Jisheng Zhang
For all BG2Q SoCs, 2 cycles is the best/correct value
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
arch/arm/boot/dts/berlin2q.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 635a16a..3f95dc5 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -90,6 +90,8 @@
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-level = <2>;
+ arm,data-latency = <2 2 2>;
+ arm,tag-latency = <2 2 2>;
};
scu: snoop-control-unit@ad0000 {
--
2.0.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
2014-06-12 9:38 ` Jisheng Zhang
@ 2014-06-12 9:44 ` Russell King - ARM Linux
-1 siblings, 0 replies; 13+ messages in thread
From: Russell King - ARM Linux @ 2014-06-12 9:44 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 9:44 ` Russell King - ARM Linux
0 siblings, 0 replies; 13+ messages in thread
From: Russell King - ARM Linux @ 2014-06-12 9:44 UTC (permalink / raw)
To: Jisheng Zhang
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
sebastian.hesselbarth, alexandre.belloni, antoine.tenart,
devicetree, linux-arm-kernel, linux-kernel
On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 10:15 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
>
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
>
Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 10:15 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:15 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
sebastian.hesselbarth@gmail.com,
alexandre.belloni@free-electrons.com,
antoine.tenart@free-electrons.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Hi Russell,
On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
>
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
>
Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 10:15 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:15 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Hi Russell,
On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
>
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
>
Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.
Thanks,
Jisheng
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
2014-06-12 10:15 ` Jisheng Zhang
(?)
@ 2014-06-12 10:19 ` Jisheng Zhang
-1 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:19 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
On Thu, 12 Jun 2014 03:15:03 -0700
Jisheng Zhang <jszhang@marvell.com> wrote:
> Hi Russell,
>
> On Thu, 12 Jun 2014 02:44:23 -0700
> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
>
> > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > > For all BG2Q SoCs, 2 cycles is the best/correct value
> >
> > It would be a good idea to set all these parameters if you need to set
> > them at all - in other words, setting arm,dirty-latency as well, as
> > that's all part of the timing specification.
> >
>
> Thanks for reviewing this patch. I will check with SoC people to find the
> correct dirty-latency value.
The BG2Q L2 cache controller is PL310, so no "dirty-latency"
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 10:19 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:19 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
sebastian.hesselbarth@gmail.com,
alexandre.belloni@free-electrons.com,
antoine.tenart@free-electrons.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Hi Russell,
On Thu, 12 Jun 2014 03:15:03 -0700
Jisheng Zhang <jszhang@marvell.com> wrote:
> Hi Russell,
>
> On Thu, 12 Jun 2014 02:44:23 -0700
> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:
>
> > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > > For all BG2Q SoCs, 2 cycles is the best/correct value
> >
> > It would be a good idea to set all these parameters if you need to set
> > them at all - in other words, setting arm,dirty-latency as well, as
> > that's all part of the timing specification.
> >
>
> Thanks for reviewing this patch. I will check with SoC people to find the
> correct dirty-latency value.
The BG2Q L2 cache controller is PL310, so no "dirty-latency"
Thanks,
Jisheng
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-12 10:19 ` Jisheng Zhang
0 siblings, 0 replies; 13+ messages in thread
From: Jisheng Zhang @ 2014-06-12 10:19 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Hi Russell,
On Thu, 12 Jun 2014 03:15:03 -0700
Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> wrote:
> Hi Russell,
>
> On Thu, 12 Jun 2014 02:44:23 -0700
> Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
>
> > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > > For all BG2Q SoCs, 2 cycles is the best/correct value
> >
> > It would be a good idea to set all these parameters if you need to set
> > them at all - in other words, setting arm,dirty-latency as well, as
> > that's all part of the timing specification.
> >
>
> Thanks for reviewing this patch. I will check with SoC people to find the
> correct dirty-latency value.
The BG2Q L2 cache controller is PL310, so no "dirty-latency"
Thanks,
Jisheng
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
2014-06-12 9:38 ` Jisheng Zhang
@ 2014-06-16 11:24 ` Sebastian Hesselbarth
-1 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-06-16 11:24 UTC (permalink / raw)
To: linux-arm-kernel
On 06/12/2014 11:38 AM, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Applied to berlin/dt with following fixed patch title:
"ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles"
Thanks!
> ---
> arch/arm/boot/dts/berlin2q.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 635a16a..3f95dc5 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -90,6 +90,8 @@
> compatible = "arm,pl310-cache";
> reg = <0xac0000 0x1000>;
> cache-level = <2>;
> + arm,data-latency = <2 2 2>;
> + arm,tag-latency = <2 2 2>;
> };
>
> scu: snoop-control-unit at ad0000 {
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
@ 2014-06-16 11:24 ` Sebastian Hesselbarth
0 siblings, 0 replies; 13+ messages in thread
From: Sebastian Hesselbarth @ 2014-06-16 11:24 UTC (permalink / raw)
To: Jisheng Zhang, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
galak, linux, alexandre.belloni, antoine.tenart
Cc: devicetree, linux-arm-kernel, linux-kernel
On 06/12/2014 11:38 AM, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Applied to berlin/dt with following fixed patch title:
"ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles"
Thanks!
> ---
> arch/arm/boot/dts/berlin2q.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 635a16a..3f95dc5 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -90,6 +90,8 @@
> compatible = "arm,pl310-cache";
> reg = <0xac0000 0x1000>;
> cache-level = <2>;
> + arm,data-latency = <2 2 2>;
> + arm,tag-latency = <2 2 2>;
> };
>
> scu: snoop-control-unit@ad0000 {
>
^ permalink raw reply [flat|nested] 13+ messages in thread