From: Sudeep Holla <sudeep.holla@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Rob Herring <robh@kernel.org>,
"linux-s390@vger.kernel.org" <linux-s390@vger.kernel.org>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"x86@kernel.org" <x86@kernel.org>,
Heiko Carstens <heiko.carstens@de.ibm.com>,
"linux390@de.ibm.com" <linux390@de.ibm.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
Date: Thu, 26 Jun 2014 18:41:32 +0000 [thread overview]
Message-ID: <53AC695C.2090406@arm.com> (raw)
In-Reply-To: <20140625222355.GK32514@n2100.arm.linux.org.uk>
Hi,
On 25/06/14 23:23, Russell King - ARM Linux wrote:
> On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:
>> + coherency_line_size: the minimum amount of data that gets transferred
>
> So, what value to do envision this taking for a CPU where the cache
> line size is 32 bytes, but each cache line has two dirty bits which
> allow it to only evict either the upper or lower 16 bytes depending
> on which are dirty?
>
IIUC most of existing implementations of cacheinfo on various architectures
are representing the cache line size as coherency_line_size, in which case I
need fix the definition in this file.
BTW will there be any architectural way of finding such configuration ?
Regards,
Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Rob Herring <robh@kernel.org>,
"linux-s390@vger.kernel.org" <linux-s390@vger.kernel.org>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"x86@kernel.org" <x86@kernel.org>,
Heiko Carstens <heiko.carstens@de.ibm.com>,
"linux390@de.ibm.com" <linux390@de.ibm.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
Date: Thu, 26 Jun 2014 19:41:32 +0100 [thread overview]
Message-ID: <53AC695C.2090406@arm.com> (raw)
In-Reply-To: <20140625222355.GK32514@n2100.arm.linux.org.uk>
Hi,
On 25/06/14 23:23, Russell King - ARM Linux wrote:
> On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:
>> + coherency_line_size: the minimum amount of data that gets transferred
>
> So, what value to do envision this taking for a CPU where the cache
> line size is 32 bytes, but each cache line has two dirty bits which
> allow it to only evict either the upper or lower 16 bytes depending
> on which are dirty?
>
IIUC most of existing implementations of cacheinfo on various architectures
are representing the cache line size as coherency_line_size, in which case I
need fix the definition in this file.
BTW will there be any architectural way of finding such configuration ?
Regards,
Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Rob Herring <robh@kernel.org>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
"linux-ia64@vger.kernel.org" <linux-ia64@vger.kernel.org>,
"linux-s390@vger.kernel.org" <linux-s390@vger.kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
Heiko Carstens <heiko.carstens@de.ibm.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
"linux390@de.ibm.com" <linux390@de.ibm.com>,
"x86@kernel.org" <x86@kernel.org>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
Date: Thu, 26 Jun 2014 19:41:32 +0100 [thread overview]
Message-ID: <53AC695C.2090406@arm.com> (raw)
In-Reply-To: <20140625222355.GK32514@n2100.arm.linux.org.uk>
Hi,
On 25/06/14 23:23, Russell King - ARM Linux wrote:
> On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:
>> +=09=09coherency_line_size: the minimum amount of data that gets transfe=
rred
>
> So, what value to do envision this taking for a CPU where the cache
> line size is 32 bytes, but each cache line has two dirty bits which
> allow it to only evict either the upper or lower 16 bytes depending
> on which are dirty?
>
IIUC most of existing implementations of cacheinfo on various architectures
are representing the cache line size as coherency_line_size, in which case =
I
need fix the definition in this file.
BTW will there be any architectural way of finding such configuration ?
Regards,
Sudeep
WARNING: multiple messages have this Message-ID (diff)
From: sudeep.holla@arm.com (Sudeep Holla)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs
Date: Thu, 26 Jun 2014 19:41:32 +0100 [thread overview]
Message-ID: <53AC695C.2090406@arm.com> (raw)
In-Reply-To: <20140625222355.GK32514@n2100.arm.linux.org.uk>
Hi,
On 25/06/14 23:23, Russell King - ARM Linux wrote:
> On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:
>> + coherency_line_size: the minimum amount of data that gets transferred
>
> So, what value to do envision this taking for a CPU where the cache
> line size is 32 bytes, but each cache line has two dirty bits which
> allow it to only evict either the upper or lower 16 bytes depending
> on which are dirty?
>
IIUC most of existing implementations of cacheinfo on various architectures
are representing the cache line size as coherency_line_size, in which case I
need fix the definition in this file.
BTW will there be any architectural way of finding such configuration ?
Regards,
Sudeep
next prev parent reply other threads:[~2014-06-26 18:41 UTC|newest]
Thread overview: 126+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-25 17:30 [PATCH 0/9] drivers: cacheinfo support Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` [PATCH 1/9] drivers: base: add new class "cpu" to group cpu devices Sudeep Holla
2014-06-25 17:30 ` [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 22:23 ` Russell King - ARM Linux
2014-06-25 22:23 ` Russell King - ARM Linux
2014-06-25 22:23 ` Russell King - ARM Linux
2014-06-25 22:23 ` Russell King - ARM Linux
2014-06-26 18:41 ` Sudeep Holla [this message]
2014-06-26 18:41 ` Sudeep Holla
2014-06-26 18:41 ` Sudeep Holla
2014-06-26 18:41 ` Sudeep Holla
2014-06-26 18:50 ` Russell King - ARM Linux
2014-06-26 18:50 ` Russell King - ARM Linux
2014-06-26 18:50 ` Russell King - ARM Linux
2014-06-26 18:50 ` Russell King - ARM Linux
2014-06-26 19:03 ` Sudeep Holla
2014-06-26 19:03 ` Sudeep Holla
2014-06-26 19:03 ` Sudeep Holla
2014-06-26 19:03 ` Sudeep Holla
2014-07-10 0:09 ` Greg Kroah-Hartman
2014-07-10 0:09 ` Greg Kroah-Hartman
2014-07-10 0:09 ` Greg Kroah-Hartman
2014-07-10 0:09 ` Greg Kroah-Hartman
2014-07-10 13:37 ` Sudeep Holla
2014-07-10 13:37 ` Sudeep Holla
2014-07-10 13:37 ` Sudeep Holla
2014-07-10 13:37 ` Sudeep Holla
2014-06-25 17:30 ` [PATCH 3/9] ia64: move cacheinfo sysfs to generic cacheinfo infrastructure Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` [PATCH 4/9] s390: " Sudeep Holla
2014-06-25 17:30 ` [PATCH 5/9] x86: " Sudeep Holla
2014-06-25 17:30 ` [PATCH 6/9] powerpc: " Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 17:30 ` [PATCH 7/9] ARM64: kernel: add support for cpu cache information Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-27 10:36 ` Mark Rutland
2014-06-27 10:36 ` Mark Rutland
2014-06-27 11:22 ` Sudeep Holla
2014-06-27 11:22 ` Sudeep Holla
2014-06-27 11:34 ` Mark Rutland
2014-06-27 11:34 ` Mark Rutland
2014-06-25 17:30 ` [PATCH 8/9] ARM: " Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 22:33 ` Russell King - ARM Linux
2014-06-25 22:33 ` Russell King - ARM Linux
2014-06-26 11:33 ` Sudeep Holla
2014-06-26 11:33 ` Sudeep Holla
2014-06-26 0:19 ` Stephen Boyd
2014-06-26 0:19 ` Stephen Boyd
2014-06-26 11:36 ` Sudeep Holla
2014-06-26 11:36 ` Sudeep Holla
2014-06-26 18:45 ` Stephen Boyd
2014-06-26 18:45 ` Stephen Boyd
2014-06-27 9:38 ` Sudeep Holla
2014-06-27 9:38 ` Sudeep Holla
2014-06-25 17:30 ` [PATCH 9/9] ARM: kernel: add outer cache support for cacheinfo implementation Sudeep Holla
2014-06-25 17:30 ` Sudeep Holla
2014-06-25 22:37 ` Russell King - ARM Linux
2014-06-25 22:37 ` Russell King - ARM Linux
2014-06-26 13:02 ` Sudeep Holla
2014-06-26 13:02 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 0/9] drivers: cacheinfo support Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 1/9] drivers: base: add new class "cpu" to group cpu devices Sudeep Holla
2014-07-25 19:09 ` Stephen Boyd
2014-07-28 13:37 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 2/9] drivers: base: support cpu cache information interface to userspace via sysfs Sudeep Holla
2014-07-29 23:09 ` Stephen Boyd
2014-07-30 16:23 ` Sudeep Holla
2014-07-31 19:46 ` Stephen Boyd
2014-08-05 18:15 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 3/9] ia64: move cacheinfo sysfs to generic cacheinfo infrastructure Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 4/9] s390: " Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 5/9] x86: " Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 6/9] powerpc: " Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 7/9] ARM64: kernel: add support for cpu cache information Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 8/9] ARM: " Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-07-25 16:44 ` [PATCH v2 9/9] ARM: kernel: add outer cache support for cacheinfo implementation Sudeep Holla
2014-07-25 16:44 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 00/11] drivers: cacheinfo support Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 01/11] cpumask: factor out show_cpumap into separate helper function Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 02/11] topology: replace custom attribute macros with standard DEVICE_ATTR* Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 03/11] drivers: base: add new class "cpu" to group cpu devices Sudeep Holla
2014-08-21 11:20 ` David Herrmann
2014-08-21 12:30 ` Sudeep Holla
2014-08-21 12:37 ` David Herrmann
2014-08-21 14:54 ` Sudeep Holla
2014-08-22 9:12 ` Kay Sievers
2014-08-22 11:29 ` [PATCH] drivers: base: add cpu_device_create to support per-cpu devices Sudeep Holla
2014-08-22 11:37 ` David Herrmann
2014-08-22 11:41 ` David Herrmann
2014-08-22 12:33 ` Sudeep Holla
2014-08-26 16:54 ` Sudeep Holla
2014-08-26 17:08 ` David Herrmann
2014-08-22 12:17 ` Sudeep Holla
2014-09-02 17:22 ` Sudeep Holla
2014-09-02 17:26 ` Greg Kroah-Hartman
2014-09-02 17:40 ` Sudeep Holla
2014-09-02 17:55 ` Greg Kroah-Hartman
2014-08-21 10:59 ` [PATCH v3 04/11] drivers: base: support cpu cache information interface to userspace via sysfs Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 05/11] ia64: move cacheinfo sysfs to generic cacheinfo infrastructure Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 06/11] s390: " Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 07/11] x86: " Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 08/11] powerpc: " Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 09/11] ARM64: kernel: add support for cpu cache information Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 10/11] ARM: " Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
2014-08-21 10:59 ` [PATCH v3 11/11] ARM: kernel: add outer cache support for cacheinfo implementation Sudeep Holla
2014-08-21 10:59 ` Sudeep Holla
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