From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
To: "Antoine Ténart" <antoine.tenart@free-electrons.com>,
"Sergei Shtylyov" <sergei.shtylyov@cogentembedded.com>
Cc: tj@kernel.org, kishon@ti.com,
thomas.petazzoni@free-electrons.com, zmxu@marvell.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-ide@vger.kernel.org, alexandre.belloni@free-electrons.com,
jszhang@marvell.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY
Date: Mon, 30 Jun 2014 16:40:49 +0200 [thread overview]
Message-ID: <53B176F1.5060308@gmail.com> (raw)
In-Reply-To: <20140630095940.GB10058@kwain>
On 06/30/2014 11:59 AM, Antoine Ténart wrote:
> On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote:
>> On 06/23/2014 05:39 PM, Antoine Ténart wrote:
>>> + /* set the controller speed */
>>> + writel(0x31, ctrl_reg + PORT_SCR_CTL);
>>
>> Value undocumented? Or is this the SATA SControl register by chance?
>
> Some magic is still there...
Antoine,
I guess Sergei was referring to AHCI spec here. PORT_SCR bits are
documented in AHCI spec as:
7:4 = 0x3 Limit speed negotiation to a rate not greater than Gen3
communication rate.
3:0 = 0x1 Perform interface communication sequence [...]. This is
functionally equivalent to a hard reset [...].
So, the question is: Should we really need to reset controller in the
PHY driver or is it already done in AHCI common code? At least we
should change the comment to something like
/* set Gen3 controller speed and perform hard reset */
Sebastian
WARNING: multiple messages have this Message-ID (diff)
From: sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY
Date: Mon, 30 Jun 2014 16:40:49 +0200 [thread overview]
Message-ID: <53B176F1.5060308@gmail.com> (raw)
In-Reply-To: <20140630095940.GB10058@kwain>
On 06/30/2014 11:59 AM, Antoine T?nart wrote:
> On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote:
>> On 06/23/2014 05:39 PM, Antoine T?nart wrote:
>>> + /* set the controller speed */
>>> + writel(0x31, ctrl_reg + PORT_SCR_CTL);
>>
>> Value undocumented? Or is this the SATA SControl register by chance?
>
> Some magic is still there...
Antoine,
I guess Sergei was referring to AHCI spec here. PORT_SCR bits are
documented in AHCI spec as:
7:4 = 0x3 Limit speed negotiation to a rate not greater than Gen3
communication rate.
3:0 = 0x1 Perform interface communication sequence [...]. This is
functionally equivalent to a hard reset [...].
So, the question is: Should we really need to reset controller in the
PHY driver or is it already done in AHCI common code? At least we
should change the comment to something like
/* set Gen3 controller speed and perform hard reset */
Sebastian
next prev parent reply other threads:[~2014-06-30 14:40 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-23 13:39 [PATCH v7 0/7] ARM: berlin: add AHCI support Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-25 19:03 ` Sergei Shtylyov
2014-06-25 19:03 ` Sergei Shtylyov
2014-06-30 9:59 ` Antoine Ténart
2014-06-30 9:59 ` Antoine Ténart
2014-06-30 14:40 ` Sebastian Hesselbarth [this message]
2014-06-30 14:40 ` Sebastian Hesselbarth
2014-06-30 15:44 ` Antoine Ténart
2014-06-30 15:44 ` Antoine Ténart
2014-06-30 16:55 ` Sergei Shtylyov
2014-06-30 16:55 ` Sergei Shtylyov
[not found] ` <1403530783-17180-1-git-send-email-antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-06-23 13:39 ` [PATCH v7 2/7] Documentation: bindings: add " Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 3/7] ata: libahci: allow to use multiple PHYs Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 4/7] ata: ahci_platform: add a generic AHCI compatible Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 5/7] Documentation: bindings: document the sub-nodes AHCI bindings Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 6/7] ARM: berlin: add the AHCI node for the BG2Q Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
2014-06-23 13:39 ` [PATCH v7 7/7] ARM: berlin: enable the eSATA interface on the BG2Q DMP Antoine Ténart
2014-06-23 13:39 ` Antoine Ténart
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