[PATCH 00/72] staging imx-drm new features and fixes

[PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
except for two patches that affect drm core (patch 53 and 63, see below).

New features for imx-drm staging driver:

- Support for multi-display (HDMI and LVDS).
- Support for global alpha and color-key properties for overlay plane.
- Support for gamma correction.
- The imx-drm crtc devices moved to device tree.
- Support for defining custom display interface pixel mappings in the
  device tree.
- Implements encoder DPMS for LVDS.
- YUV planar pixel formats supported for DRM framebuffers.
- DDC support added for LVDS.
- Page flip handling moved to imx plane driver and implemented with
  IPU double-buffering.
- Support page-flip in the overlay plane (patch 53 affects drm core).
- Add support for parsing pixel clock edge select (patch 63 affects drm core).
- Add LVDS connection detect via drm_probe_ddc().
- Implement crtc mode_set_base using plane page-flip.


Fixed issues:

- HDMI and LVDS now use different PLL clock roots (part of multi-display
  support).
- Use counter added to IPU DC enable/disable (part of multi-display
  support).
- Fixed some HDMI timing issues.
- Wider range of supported DI pixel clocks generated (all EDID modes
  reported from HDMI displays now work).
- Fix separate primary plane objects.
- HDMI must select DI pre clock as DI clock parent during encoder prepare
  (LVDS may have switched DI clock to LDB parent, part of multi-display
  support).
- Assign correct DMFC burst size.
- Resolve some DI synchronous display error cases.



George G. Davis (1):
  ARM: dts: imx6qdl-sabreauto: Add HDMI device

Jiada Wang (1):
  gpu: ipu-v3: fix HDMI timing issues

Steve Longerbeam (70):
  ARM: dts: imx6qdl-sabrelite: Add HDMI device
  ARM: dts: imx6qdl: Create imx-drm crtc nodes
  ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
  ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip
  gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
  gpu: ipu-v3: Add ipu_dp_set_chroma_key()
  gpu: ipu-v3: Add ipu_dp_set_gamma_correction()
  gpu: ipu-v3: Add support for dynamic DC interface pixel maps
  gpu: ipu-v3: Add ipu_dc_uninit_sync()
  gpu: ipu-v3: Pass struct ipu_dc to enable/disable
  gpu: ipu-v3: Add ipu_dp_uninit_channel()
  gpu: ipu-v3: Pass struct ipu_dp to enable/disable
  gpu: ipu-v3: Implement use counter for ipu_dc_enable(),
    ipu_dc_disable()
  gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug
  gpu: ipu-v3: Add ipu_di_uninit_sync_panel()
  gpu: ipu-v3: Split out DI clock enable/disable
  gpu: ipu-v3: Protect more CM reg access with IPU lock
  gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
  gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()
  gpu: ipu-v3: Fix indent/ws in ipu-dmfc
  gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
  gpu: ipu-v3: Remove ipu_dmfc_init_channel()
  gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()
  gpu: ipu-v3: Enumerate the DC channel names
  gpu: ipu-di: Move ipu pointer init
  gpu: ipu-di: Add and improve debug/error messages
  gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg
  gpu: ipu-v3: Remove IPU client registration
  gpu: ipu-di: Set rate of DI pre clock
  gpu: ipu-v3: Add RGB666 interface pixel map
  gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*
  gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()
  gpu: ipu-v3: Add IDMA channel linking support
  gpu: ipu-cpmem: Support YVU422
  gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
  imx-drm: Crtcs moved to device tree
  imx-drm: hdmi: optimize i2c write wait
  imx-drm: parallel-display: Support RGB666 pixel fmt
  imx-drm: imx-ldb: Add debug to connector/encoder entry points
  imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()
  imx-drm: parallel-display: Fix typo when setting mode type
  imx-drm: ipuv3-plane: Fix planar formats
  imx-drm: ipuv3-plane: Allow YUV space for background plane
  imx-drm: ipuv3-plane: Add more supported pixel formats
  imx-drm: ipuv3-plane: Implement global alpha and colorkey properties
  imx-drm: hdmi: rework irq request/free
  imx-drm: imx-ldb: Add DDC support
  imx-drm: Fix separate primary plane objects
  imx-drm: Move page flip handling to plane driver
  imx-drm: Reset ipu unit pointers to NULL on errors
  drm: implement page flipping support for planes
  imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs
  imx-drm: Implement DRM gamma set
  imx-drm: Implement custom ioctl to set gamma
  imx-drm: Add support for interface pixel maps
  imx-drm: parallel-display: Add interface-pix-map DT property
  imx-drm: hdmi: set DI clock source to DI pre clock
  imx-drm: ipuv3-crtc: Set the crtc device name
  imx-drm: hdmi: Save ipu/di mux for later iomux setup
  imx-drm: ipuv3-plane: Assign correct dmfc burst size
  drm_modes: videomode: add pos/neg pixel clock polarity flag
  imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock
    polarity
  imx-drm: imx-ldb: Add all defined of video modes
  imx-drm: parallel-display: Add all defined of video modes
  imx-drm: ipuv3-crtc: Disable fb on crtc unbind
  imx-drm: imx-ldb: Use DDC probe as connection detect
  imx-drm: ipuv3-crtc: Implement mode_set_base
  imx-drm: Cancel pending page flip events at preclose
  imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
  imx-drm: ipuv3-plane: Enable 8 burst locking

 .../bindings/staging/imx-drm/fsl-imx-drm.txt       |   43 +-
 arch/arm/boot/dts/imx6dl.dtsi                      |   10 +-
 arch/arm/boot/dts/imx6q.dtsi                       |  128 +++--
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |    5 +
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi           |   19 +
 arch/arm/boot/dts/imx6qdl.dtsi                     |  125 ++---
 arch/arm/mach-imx/clk-imx6q.c                      |   11 +-
 drivers/gpu/drm/drm_crtc.c                         |  241 +++++----
 drivers/gpu/drm/drm_ioctl.c                        |    1 +
 drivers/gpu/drm/drm_modes.c                        |    4 +
 drivers/gpu/ipu-v3/ipu-common.c                    |  303 +++++++-----
 drivers/gpu/ipu-v3/ipu-cpmem.c                     |   99 ++--
 drivers/gpu/ipu-v3/ipu-dc.c                        |  305 ++++++++----
 drivers/gpu/ipu-v3/ipu-di.c                        |  300 +++++++++---
 drivers/gpu/ipu-v3/ipu-dmfc.c                      |   94 ++--
 drivers/gpu/ipu-v3/ipu-dp.c                        |  214 ++++++--
 drivers/gpu/ipu-v3/ipu-prv.h                       |    1 +
 drivers/staging/imx-drm/imx-drm-core.c             |  190 +++++---
 drivers/staging/imx-drm/imx-drm.h                  |   26 +-
 drivers/staging/imx-drm/imx-hdmi.c                 |   77 ++-
 drivers/staging/imx-drm/imx-ldb.c                  |  268 ++++++----
 drivers/staging/imx-drm/imx-tve.c                  |    5 +-
 drivers/staging/imx-drm/ipuv3-crtc.c               |  515 ++++++++++++++------
 drivers/staging/imx-drm/ipuv3-plane.c              |  399 +++++++++++++--
 drivers/staging/imx-drm/ipuv3-plane.h              |   35 +-
 drivers/staging/imx-drm/parallel-display.c         |   78 ++-
 include/drm/drm_crtc.h                             |   11 +
 include/uapi/drm/drm.h                             |    1 +
 include/uapi/drm/drm_mode.h                        |   12 +
 include/uapi/drm/imx_drm.h                         |   30 ++
 include/video/imx-ipu-v3.h                         |   86 +++-
 31 files changed, 2557 insertions(+), 1079 deletions(-)
 create mode 100644 include/uapi/drm/imx_drm.h

-- 
1.7.9.5

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[PATCH 01/72] ARM: dts: imx6qdl-sabrelite: Add HDMI device

[Steve Longerbeam]

Adds hdmi with DDC on i2c2.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 0a36129..577e4fd 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -173,6 +173,11 @@
 	status = "okay";
 };
 
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
@@ -188,6 +193,13 @@
 	};
 };
 
+&i2c2 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +277,13 @@
 			>;
 		};
 
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
+			>;
+		};
+
 		pinctrl_pwm1: pwm1grp {
 			fsl,pins = <
 				MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
-- 
1.7.9.5

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[PATCH 02/72] ARM: dts: imx6qdl-sabreauto: Add HDMI device

[Steve Longerbeam]

From: "George G. Davis" <george_davis@mentor.com>

Signed-off-by: George G. Davis <george_davis@mentor.com>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd6..1bb3ead 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,11 @@
 	};
 };
 
+&hdmi {
+	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
-- 
1.7.9.5

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[PATCH 03/72] ARM: dts: imx6qdl: Create imx-drm crtc nodes

[Steve Longerbeam]

Create imx-drm crtc device nodes. Each crtc node requires the following
parameters:

- parent ipu phandle.
- di number.
- port endpoints.

Optionally the node can specify a "dual-plane" boolean parameter
to configure the crtc device with a foreground plane. If not given,
the crtc will have only a single plane.

The crtc port lists the endpoints to the remote encoder endpoints.
These endpoints were moved out of the ipu nodes, since they more
logically now belong to the crtc nodes.

As a result, the display-subsystem node should enumerate its crtcs
instead of the former ipu ports.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 arch/arm/boot/dts/imx6dl.dtsi  |    2 +-
 arch/arm/boot/dts/imx6q.dtsi   |  116 ++++++++++++++++++++------------------
 arch/arm/boot/dts/imx6qdl.dtsi |  122 +++++++++++++++++++++-------------------
 3 files changed, 127 insertions(+), 113 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b453e0e..05af0f4 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -98,7 +98,7 @@
 
 	display-subsystem {
 		compatible = "fsl,imx-display-subsystem";
-		ports = <&ipu1_di0>, <&ipu1_di1>;
+		crtcs = <&crtc0>, <&crtc1>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646..9d1f88c 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -140,6 +140,59 @@
 			};
 		};
 
+		crtc2: crtc@2 {
+			compatible = "fsl,imx-ipuv3-crtc";
+			ipu = <&ipu2>;
+			di = <0>;
+			dual-plane;
+
+			port {
+				crtc2_disp0: endpoint@0 {
+				};
+
+				crtc2_hdmi: endpoint@1 {
+					remote-endpoint = <&hdmi_mux_2>;
+				};
+
+				crtc2_mipi: endpoint@2 {
+				};
+
+				crtc2_lvds0: endpoint@3 {
+					remote-endpoint = <&lvds0_mux_2>;
+				};
+
+				crtc2_lvds1: endpoint@4 {
+					remote-endpoint = <&lvds1_mux_2>;
+				};
+			};
+		};
+
+		crtc3: crtc@3 {
+			compatible = "fsl,imx-ipuv3-crtc";
+			ipu = <&ipu2>;
+			di = <1>;
+
+			port {
+				crtc3_disp0: endpoint@0 {
+				};
+
+				crtc3_hdmi: endpoint@1 {
+					remote-endpoint = <&hdmi_mux_3>;
+				};
+
+				crtc3_mipi: endpoint@2 {
+				};
+
+				crtc3_lvds0: endpoint@3 {
+					remote-endpoint = <&lvds0_mux_3>;
+				};
+
+				crtc3_lvds1: endpoint@4 {
+					remote-endpoint = <&lvds1_mux_3>;
+				};
+			};
+		};
+
 		sata: sata@02200000 {
 			compatible = "fsl,imx6q-ahci";
 			reg = <0x02200000 0x4000>;
@@ -171,57 +224,12 @@
 			ipu2_csi1: port@1 {
 				reg = <1>;
 			};
-
-			ipu2_di0: port@2 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <2>;
-
-				ipu2_di0_disp0: endpoint@0 {
-				};
-
-				ipu2_di0_hdmi: endpoint@1 {
-					remote-endpoint = <&hdmi_mux_2>;
-				};
-
-				ipu2_di0_mipi: endpoint@2 {
-				};
-
-				ipu2_di0_lvds0: endpoint@3 {
-					remote-endpoint = <&lvds0_mux_2>;
-				};
-
-				ipu2_di0_lvds1: endpoint@4 {
-					remote-endpoint = <&lvds1_mux_2>;
-				};
-			};
-
-			ipu2_di1: port@3 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <3>;
-
-				ipu2_di1_hdmi: endpoint@1 {
-					remote-endpoint = <&hdmi_mux_3>;
-				};
-
-				ipu2_di1_mipi: endpoint@2 {
-				};
-
-				ipu2_di1_lvds0: endpoint@3 {
-					remote-endpoint = <&lvds0_mux_3>;
-				};
-
-				ipu2_di1_lvds1: endpoint@4 {
-					remote-endpoint = <&lvds1_mux_3>;
-				};
-			};
 		};
 	};
 
 	display-subsystem {
 		compatible = "fsl,imx-display-subsystem";
-		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
+		crtcs = <&crtc0>, <&crtc1>, <&crtc2>, <&crtc3>;
 	};
 };
 
@@ -232,7 +240,7 @@
 		reg = <2>;
 
 		hdmi_mux_2: endpoint {
-			remote-endpoint = <&ipu2_di0_hdmi>;
+			remote-endpoint = <&crtc2_hdmi>;
 		};
 	};
 
@@ -240,7 +248,7 @@
 		reg = <3>;
 
 		hdmi_mux_3: endpoint {
-			remote-endpoint = <&ipu2_di1_hdmi>;
+			remote-endpoint = <&crtc3_hdmi>;
 		};
 	};
 };
@@ -259,7 +267,7 @@
 			reg = <2>;
 
 			lvds0_mux_2: endpoint {
-				remote-endpoint = <&ipu2_di0_lvds0>;
+				remote-endpoint = <&crtc2_lvds0>;
 			};
 		};
 
@@ -267,7 +275,7 @@
 			reg = <3>;
 
 			lvds0_mux_3: endpoint {
-				remote-endpoint = <&ipu2_di1_lvds0>;
+				remote-endpoint = <&crtc3_lvds0>;
 			};
 		};
 	};
@@ -277,7 +285,7 @@
 			reg = <2>;
 
 			lvds1_mux_2: endpoint {
-				remote-endpoint = <&ipu2_di0_lvds1>;
+				remote-endpoint = <&crtc2_lvds1>;
 			};
 		};
 
@@ -285,7 +293,7 @@
 			reg = <3>;
 
 			lvds1_mux_3: endpoint {
-				remote-endpoint = <&ipu2_di1_lvds1>;
+				remote-endpoint = <&crtc3_lvds1>;
 			};
 		};
 	};
@@ -296,7 +304,7 @@
 		reg = <2>;
 
 		mipi_mux_2: endpoint {
-			remote-endpoint = <&ipu2_di0_mipi>;
+			remote-endpoint = <&crtc2_mipi>;
 		};
 	};
 
@@ -304,7 +312,7 @@
 		reg = <3>;
 
 		mipi_mux_3: endpoint {
-			remote-endpoint = <&ipu2_di1_mipi>;
+			remote-endpoint = <&crtc3_mipi>;
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5..13d6b50 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -167,6 +167,62 @@
 			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		crtc0: crtc@0 {
+			compatible = "fsl,imx-ipuv3-crtc";
+			ipu = <&ipu1>;
+			di = <0>;
+			dual-plane;
+
+			port {
+				crtc0_disp0: endpoint@0 {
+				};
+
+				crtc0_hdmi: endpoint@1 {
+					remote-endpoint = <&hdmi_mux_0>;
+				};
+
+				crtc0_mipi: endpoint@2 {
+					remote-endpoint = <&mipi_mux_0>;
+				};
+
+				crtc0_lvds0: endpoint@3 {
+					remote-endpoint = <&lvds0_mux_0>;
+				};
+
+				crtc0_lvds1: endpoint@4 {
+					remote-endpoint = <&lvds1_mux_0>;
+				};
+			};
+
+		};
+
+		crtc1: crtc@1 {
+			compatible = "fsl,imx-ipuv3-crtc";
+			ipu = <&ipu1>;
+			di = <1>;
+
+			port {
+				crtc1_disp0: endpoint@0 {
+				};
+
+				crtc1_hdmi: endpoint@1 {
+					remote-endpoint = <&hdmi_mux_1>;
+				};
+
+				crtc1_mipi: endpoint@2 {
+					remote-endpoint = <&mipi_mux_1>;
+				};
+
+				crtc1_lvds0: endpoint@3 {
+					remote-endpoint = <&lvds0_mux_1>;
+				};
+
+				crtc1_lvds1: endpoint@4 {
+					remote-endpoint = <&lvds1_mux_1>;
+				};
+			};
+		};
+
 		aips-bus@02000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
@@ -711,7 +767,7 @@
 						reg = <0>;
 
 						lvds0_mux_0: endpoint {
-							remote-endpoint = <&ipu1_di0_lvds0>;
+							remote-endpoint = <&crtc0_lvds0>;
 						};
 					};
 
@@ -719,7 +775,7 @@
 						reg = <1>;
 
 						lvds0_mux_1: endpoint {
-							remote-endpoint = <&ipu1_di1_lvds0>;
+							remote-endpoint = <&crtc1_lvds0>;
 						};
 					};
 				};
@@ -734,7 +790,7 @@
 						reg = <0>;
 
 						lvds1_mux_0: endpoint {
-							remote-endpoint = <&ipu1_di0_lvds1>;
+							remote-endpoint = <&crtc0_lvds1>;
 						};
 					};
 
@@ -742,7 +798,7 @@
 						reg = <1>;
 
 						lvds1_mux_1: endpoint {
-							remote-endpoint = <&ipu1_di1_lvds1>;
+							remote-endpoint = <&crtc1_lvds1>;
 						};
 					};
 				};
@@ -763,7 +819,7 @@
 					reg = <0>;
 
 					hdmi_mux_0: endpoint {
-						remote-endpoint = <&ipu1_di0_hdmi>;
+						remote-endpoint = <&crtc0_hdmi>;
 					};
 				};
 
@@ -771,7 +827,7 @@
 					reg = <1>;
 
 					hdmi_mux_1: endpoint {
-						remote-endpoint = <&ipu1_di1_hdmi>;
+						remote-endpoint = <&crtc1_hdmi>;
 					};
 				};
 			};
@@ -1013,7 +1069,7 @@
 					reg = <0>;
 
 					mipi_mux_0: endpoint {
-						remote-endpoint = <&ipu1_di0_mipi>;
+						remote-endpoint = <&crtc0_mipi>;
 					};
 				};
 
@@ -1021,7 +1077,7 @@
 					reg = <1>;
 
 					mipi_mux_1: endpoint {
-						remote-endpoint = <&ipu1_di1_mipi>;
+						remote-endpoint = <&crtc1_mipi>;
 					};
 				};
 			};
@@ -1100,56 +1156,6 @@
 			ipu1_csi1: port@1 {
 				reg = <1>;
 			};
-
-			ipu1_di0: port@2 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <2>;
-
-				ipu1_di0_disp0: endpoint@0 {
-				};
-
-				ipu1_di0_hdmi: endpoint@1 {
-					remote-endpoint = <&hdmi_mux_0>;
-				};
-
-				ipu1_di0_mipi: endpoint@2 {
-					remote-endpoint = <&mipi_mux_0>;
-				};
-
-				ipu1_di0_lvds0: endpoint@3 {
-					remote-endpoint = <&lvds0_mux_0>;
-				};
-
-				ipu1_di0_lvds1: endpoint@4 {
-					remote-endpoint = <&lvds1_mux_0>;
-				};
-			};
-
-			ipu1_di1: port@3 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <3>;
-
-				ipu1_di0_disp1: endpoint@0 {
-				};
-
-				ipu1_di1_hdmi: endpoint@1 {
-					remote-endpoint = <&hdmi_mux_1>;
-				};
-
-				ipu1_di1_mipi: endpoint@2 {
-					remote-endpoint = <&mipi_mux_1>;
-				};
-
-				ipu1_di1_lvds0: endpoint@3 {
-					remote-endpoint = <&lvds0_mux_1>;
-				};
-
-				ipu1_di1_lvds1: endpoint@4 {
-					remote-endpoint = <&lvds1_mux_1>;
-				};
-			};
 		};
 	};
 };
-- 
1.7.9.5

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[PATCH 04/72] ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di

[Steve Longerbeam]

AS pll5_video_div has already been used as clock root for ldb_di,
so use pll2_pfd0_352m as clock root of ipu_di for HDMI.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e79da7..86b58fc 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -483,10 +483,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
 	}
 
-	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
+	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
+	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
+	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
 	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
-- 
1.7.9.5

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[PATCH 05/72] ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip

[Steve Longerbeam]

Select pll3_usb_otg for ldb_di clock for rev 1.0 chips.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 arch/arm/mach-imx/clk-imx6q.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 86b58fc..68064a6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	    cpu_is_imx6dl()) {
 		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
 		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+	} else {
+		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
+		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
 	}
 
 	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
-- 
1.7.9.5

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[PATCH 06/72] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

[Steve Longerbeam]

Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-cpmem.c |    7 +++++++
 include/video/imx-ipu-v3.h     |    1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 3bf05bc..2c93e9c 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -253,6 +253,13 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
 
+void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
+{
+	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
+	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
+}
+EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
+
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
 {
 	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index c74bf4a..03cda50 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -195,6 +195,7 @@ void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
+void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
-- 
1.7.9.5

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[PATCH 07/72] gpu: ipu-v3: Add ipu_dp_set_chroma_key()

[Steve Longerbeam]

Adds the function ipu_dp_set_chroma_key(), which sets up a color key
value for a DP foreground plane.

ipu_dp_set_chroma_key() accepts a color key value in RGB24 format.
If the combiner unit colorspace is YUV, the key must be converted
to YUV444, using the same CSC coefficients as programmed in the DP.
So pull out the CSC coefficients from ipu_dp_csc_init() to make
them available to rgb24_to_yuv444() that converts to color key.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dp.c |  121 ++++++++++++++++++++++++++++++++++++-------
 include/video/imx-ipu-v3.h  |    1 +
 2 files changed, 103 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 98686ed..e4026f1 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -84,6 +84,52 @@ static inline struct ipu_flow *to_flow(struct ipu_dp *dp)
 		return container_of(dp, struct ipu_flow, background);
 }
 
+static const int rgb2yuv_coeff[5][3] = {
+	{ 0x0099, 0x012d, 0x003a },
+	{ 0x03a9, 0x0356, 0x0100 },
+	{ 0x0100, 0x0329, 0x03d6 },
+	{ 0x0000, 0x0200, 0x0200 }, /* B0, B1, B2 */
+	{ 0x2,    0x2,    0x2 },    /* S0, S1, S2 */
+};
+
+static const int yuv2rgb_coeff[5][3] = {
+	{ 0x0095, 0x0000, 0x00cc },
+	{ 0x0095, 0x03ce, 0x0398 },
+	{ 0x0095, 0x00ff, 0x0000 },
+	{ 0x3e42, 0x010a, 0x3dd6 }, /* B0,B1,B2 */
+	{ 0x1,    0x1,    0x1 },    /* S0,S1,S2 */
+};
+
+/*
+ * This is used to convert an RGB24 color key to YUV444, using
+ * the same CSC coefficients as programmed in the DP.
+ */
+static u32 rgb24_to_yuv444(u32 rgb24)
+{
+	u32 red, green, blue;
+	int i, c[3];
+
+	red   = (rgb24 >> 16) & 0xff;
+	green = (rgb24 >>  8) & 0xff;
+	blue  = (rgb24 >>  0) & 0xff;
+
+	for (i = 0; i < 3; i++) {
+		c[i] = red * rgb2yuv_coeff[i][0];
+		c[i] += green * rgb2yuv_coeff[i][1];
+		c[i] += blue * rgb2yuv_coeff[i][2];
+		c[i] /= 16;
+		c[i] += rgb2yuv_coeff[3][i] * 4;
+		c[i] += 8;
+		c[i] /= 16;
+		if (c[i] < 0)
+			c[i] = 0;
+		if (c[i] > 255)
+			c[i] = 255;
+	}
+
+	return (c[0] << 16) | (c[1] << 8) | c[2];
+}
+
 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
 		u8 alpha, bool bg_chan)
 {
@@ -120,6 +166,48 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
 }
 EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);
 
+/*
+ * The input color_key must always be RGB24. It will be converted to
+ * YUV444 if the pixel format to the Combining unit is YUV space.
+ */
+int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key)
+{
+	struct ipu_flow *flow = to_flow(dp);
+	struct ipu_dp_priv *priv = flow->priv;
+	enum ipu_color_space combiner_cs;
+	u32 reg;
+
+	mutex_lock(&priv->mutex);
+
+	if (flow->foreground.in_cs == flow->background.in_cs)
+		combiner_cs = flow->foreground.in_cs;
+	else
+		combiner_cs = flow->out_cs;
+
+	if (combiner_cs == IPUV3_COLORSPACE_YUV)
+		color_key = rgb24_to_yuv444(color_key);
+
+	color_key &= 0x00ffffff;
+
+	if (enable) {
+		reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & ~0x00FFFFFFL;
+		writel(reg | color_key, flow->base + DP_GRAPH_WIND_CTRL);
+
+		reg = readl(flow->base + DP_COM_CONF);
+		writel(reg | DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
+	} else {
+		reg = readl(flow->base + DP_COM_CONF);
+		writel(reg & ~DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
+	}
+
+	ipu_srm_dp_sync_update(priv->ipu);
+
+	mutex_unlock(&priv->mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_dp_set_chroma_key);
+
 int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
 {
 	struct ipu_flow *flow = to_flow(dp);
@@ -138,6 +226,7 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
 		enum ipu_color_space out,
 		u32 place)
 {
+	const int (*c)[3];
 	u32 reg;
 
 	reg = readl(flow->base + DP_COM_CONF);
@@ -148,25 +237,19 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
 		return;
 	}
 
-	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
-		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
-		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
-		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
-		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
-		writel(0x3d6 | (0x0000 << 16) | (2 << 30),
-				flow->base + DP_CSC_0);
-		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
-				flow->base + DP_CSC_1);
-	} else {
-		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
-		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
-		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
-		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
-		writel(0x000 | (0x3e42 << 16) | (1 << 30),
-				flow->base + DP_CSC_0);
-		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
-				flow->base + DP_CSC_1);
-	}
+	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV)
+		c = rgb2yuv_coeff;
+	else
+		c = yuv2rgb_coeff;
+
+	writel(c[0][0] | (c[0][1] << 16), flow->base + DP_CSC_A_0);
+	writel(c[0][2] | (c[1][0] << 16), flow->base + DP_CSC_A_1);
+	writel(c[1][1] | (c[1][2] << 16), flow->base + DP_CSC_A_2);
+	writel(c[2][0] | (c[2][1] << 16), flow->base + DP_CSC_A_3);
+	writel(c[2][2] | (c[3][0] << 16) | (c[4][0] << 30),
+	       flow->base + DP_CSC_0);
+	writel(c[3][1] | (c[4][1] << 14) | (c[3][2] << 16) | (c[4][2] << 30),
+	       flow->base + DP_CSC_1);
 
 	reg |= place;
 
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 03cda50..e878343 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -273,6 +273,7 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
 		bool bg_chan);
+int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key);
 
 /*
  * IPU CMOS Sensor Interface (csi) functions
-- 
1.7.9.5

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[PATCH 08/72] gpu: ipu-v3: Add ipu_dp_set_gamma_correction()

[Steve Longerbeam]

Adds the function ipu_dp_set_gamma_correction(), which programs the
piecewise linear curve that approximates a gamma correction curve.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dp.c |   46 +++++++++++++++++++++++++++++++++++++++++++
 include/video/imx-ipu-v3.h  |    2 ++
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index e4026f1..472acd6 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -29,6 +29,8 @@
 #define DP_COM_CONF		0x0
 #define DP_GRAPH_WIND_CTRL	0x0004
 #define DP_FG_POS		0x0008
+#define DP_GAMMA_C(i)		(0x0014 + ((i) / 2) * 4)
+#define DP_GAMMA_S(i)		(0x0034 + ((i) / 4) * 4)
 #define DP_CSC_A_0		0x0044
 #define DP_CSC_A_1		0x0048
 #define DP_CSC_A_2		0x004C
@@ -45,6 +47,8 @@
 #define DP_COM_CONF_CSC_DEF_FG		(3 << 8)
 #define DP_COM_CONF_CSC_DEF_BG		(2 << 8)
 #define DP_COM_CONF_CSC_DEF_BOTH	(1 << 8)
+#define DP_COM_CONF_GAMMA_EN		(1 << 12)
+#define DP_COM_CONF_GAMMA_YUV_EN	(1 << 13)
 
 #define IPUV3_NUM_FLOWS		3
 
@@ -208,6 +212,48 @@ int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key)
 }
 EXPORT_SYMBOL(ipu_dp_set_chroma_key);
 
+/*
+ * Programs a piecewise linear curve that approximates the gamma curve.
+ * Sixteen lines in the curve must be provided, that is, m[] and b[]
+ * must each have sixteen entries, where m[] and b[] contain the slope
+ * and y-intercept of each line respectively.
+ */
+int ipu_dp_set_gamma_correction(struct ipu_dp *dp, bool enable, u32 *m, u32 *b)
+{
+	struct ipu_flow *flow = to_flow(dp);
+	struct ipu_dp_priv *priv = flow->priv;
+	u32 reg;
+	int i;
+
+	mutex_lock(&priv->mutex);
+
+	for (i = 0; i < 16; i += 2)
+		writel((b[i] & 0x1ff) | ((b[i + 1] & 0x1ff) << 16),
+		       flow->base + DP_GAMMA_C(i));
+	for (i = 0; i < 16; i += 4)
+		writel((m[i] & 0xff) | ((m[i + 1] & 0xff) << 8) |
+		       ((m[i + 2] & 0xff) << 16) | ((m[i + 3] & 0xff) << 24),
+		       flow->base + DP_GAMMA_S(i));
+
+	reg = readl(flow->base + DP_COM_CONF);
+	if (enable) {
+		if (flow->out_cs == IPUV3_COLORSPACE_YUV)
+			reg |= DP_COM_CONF_GAMMA_YUV_EN;
+		else
+			reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
+		reg |= DP_COM_CONF_GAMMA_EN;
+	} else
+		reg &= ~DP_COM_CONF_GAMMA_EN;
+	writel(reg, flow->base + DP_COM_CONF);
+
+	ipu_srm_dp_sync_update(priv->ipu);
+
+	mutex_unlock(&priv->mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(ipu_dp_set_gamma_correction);
+
 int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
 {
 	struct ipu_flow *flow = to_flow(dp);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index e878343..6fa86c7 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -274,6 +274,8 @@ int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
 		bool bg_chan);
 int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key);
+int ipu_dp_set_gamma_correction(struct ipu_dp *dp, bool enable,
+				u32 *m, u32 *b);
 
 /*
  * IPU CMOS Sensor Interface (csi) functions
-- 
1.7.9.5

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[PATCH 09/72] gpu: ipu-v3: Add support for dynamic DC interface pixel maps

[Steve Longerbeam]

Adds support to ipu-dc to dynamically create new display interface
pixel mappings.

The mappings are formally defined by a struct ipu_dc_if_map, which is
passed to ipu_dc_init_sync().

The ipu-dc maintains a list of the currently programmed mappings.
Some mappings are pre-loaded at probe time (RGB24, BGR24, GBR24,
RGB565, BGR666, and "LVDS666").

If the map pointer to ipu_dc_init_sync() is not NULL, a new mapping
is created, otherwise previously loaded mappings will be searched based
on the passed pixel_fmt.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c          |  248 ++++++++++++++++++++++------------
 drivers/staging/imx-drm/ipuv3-crtc.c |    2 +-
 include/video/imx-ipu-v3.h           |   23 +++-
 3 files changed, 184 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 2326c75..36c7c57 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -26,6 +26,7 @@
 
 #define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
 #define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)
+#define DC_MAX_MAPS		24
 
 #define DC_EVT_NF		0
 #define DC_EVT_NL		1
@@ -86,13 +87,40 @@
 
 struct ipu_dc_priv;
 
-enum ipu_dc_map {
-	IPU_DC_MAP_RGB24,
-	IPU_DC_MAP_RGB565,
-	IPU_DC_MAP_GBR24, /* TVEv2 */
-	IPU_DC_MAP_BGR666,
-	IPU_DC_MAP_LVDS666,
-	IPU_DC_MAP_BGR24,
+/* some pre-defined maps */
+static struct ipu_dc_if_map predef_maps[] = {
+	{
+		.src_mask = {0xff, 0xff, 0xff},
+		.dest_msb = {7, 15, 23},
+		.v4l2_fmt = V4L2_PIX_FMT_RGB24,
+	}, {
+		.src_mask = {0xf8, 0xfc, 0xf8},
+		.dest_msb = {4, 10, 15},
+		.v4l2_fmt = V4L2_PIX_FMT_RGB565,
+	}, {
+		/* V4L2_PIX_FMT_GBR24, for TVEv2 */
+		.src_mask = {0xff, 0xff, 0xff},
+		.dest_msb = {23, 7, 15},
+		.v4l2_fmt = v4l2_fourcc('G', 'B', 'R', '3'),
+	}, {
+		.src_mask = {0xfc, 0xfc, 0xfc},
+		.dest_msb = {17, 11, 5},
+		.v4l2_fmt = V4L2_PIX_FMT_BGR666,
+	}, {
+		.src_mask = {0xfc, 0xfc, 0xfc},
+		.dest_msb = {21, 13, 5},
+		.v4l2_fmt = v4l2_fourcc('L', 'V', 'D', '6'),
+	}, {
+		.src_mask = {0xff, 0xff, 0xff},
+		.dest_msb = {23, 15, 7},
+		.v4l2_fmt = V4L2_PIX_FMT_BGR24,
+	},
+};
+
+struct dc_if_map_priv {
+	struct ipu_dc_if_map map;
+	int mapnr;
+	struct list_head list;
 };
 
 struct ipu_dc {
@@ -110,12 +138,20 @@ struct ipu_dc_priv {
 	struct ipu_soc		*ipu;
 	struct device		*dev;
 	struct ipu_dc		channels[IPU_DC_NUM_CHANNELS];
+	struct list_head	map_list;
+	int			next_map;
 	struct mutex		mutex;
 	struct completion	comp;
 	int			dc_irq;
 	int			dp_irq;
 };
 
+/* forward references */
+static void ipu_dc_map_config(struct ipu_dc_priv *priv,
+			      struct dc_if_map_priv *map);
+static void ipu_dc_map_clear(struct ipu_dc_priv *priv,
+			     struct dc_if_map_priv *map);
+
 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 {
 	u32 reg;
@@ -146,39 +182,91 @@ static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 }
 
-static int ipu_pixfmt_to_map(u32 fmt)
+static inline bool identical_mapping(struct ipu_dc_if_map *map1,
+				     struct ipu_dc_if_map *map2)
 {
-	switch (fmt) {
-	case V4L2_PIX_FMT_RGB24:
-		return IPU_DC_MAP_RGB24;
-	case V4L2_PIX_FMT_RGB565:
-		return IPU_DC_MAP_RGB565;
-	case IPU_PIX_FMT_GBR24:
-		return IPU_DC_MAP_GBR24;
-	case V4L2_PIX_FMT_BGR666:
-		return IPU_DC_MAP_BGR666;
-	case v4l2_fourcc('L', 'V', 'D', '6'):
-		return IPU_DC_MAP_LVDS666;
-	case V4L2_PIX_FMT_BGR24:
-		return IPU_DC_MAP_BGR24;
-	default:
-		return -EINVAL;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		if (map1->src_mask[i] != map2->src_mask[i] ||
+		    map1->dest_msb[i] != map2->dest_msb[i])
+			return false;
+	}
+
+	return true;
+}
+
+/* priv->mutex held when calling */
+static struct dc_if_map_priv *ipu_dc_new_map(struct ipu_dc_priv *priv,
+					     struct ipu_dc_if_map *new_map)
+{
+	struct dc_if_map_priv *entry;
+
+	/* first search for an existing map that matches */
+	list_for_each_entry(entry, &priv->map_list, list) {
+		if (identical_mapping(&entry->map, new_map))
+			return entry;
+	}
+
+	if (priv->next_map >= DC_MAX_MAPS) {
+		dev_err(priv->dev, "IPU_DISP: No map space left\n");
+		return ERR_PTR(-ENOSPC);
+	}
+
+	entry = devm_kzalloc(priv->dev, sizeof(*entry), GFP_KERNEL);
+	if (!entry)
+		return ERR_PTR(-ENOMEM);
+
+	/* Copy new map */
+	entry->map = *new_map;
+	entry->mapnr = priv->next_map++;
+	list_add_tail(&entry->list, &priv->map_list);
+
+	ipu_dc_map_clear(priv, entry);
+	ipu_dc_map_config(priv, entry);
+
+	return entry;
+}
+
+static struct dc_if_map_priv *ipu_dc_get_map(struct ipu_dc_priv *priv,
+					     struct ipu_dc_if_map *new_map,
+					     u32 v4l2_fmt)
+{
+	struct dc_if_map_priv *entry = ERR_PTR(-EINVAL);
+
+	mutex_lock(&priv->mutex);
+
+	if (new_map) {
+		/* create a new map */
+		entry = ipu_dc_new_map(priv, new_map);
+	} else if (v4l2_fmt) {
+		/* otherwise search for an existing map */
+		list_for_each_entry(entry, &priv->map_list, list) {
+			if (entry->map.v4l2_fmt == v4l2_fmt)
+				goto unlock;
+		}
+
+		entry = ERR_PTR(-EINVAL);
 	}
+
+unlock:
+	mutex_unlock(&priv->mutex);
+	return entry;
 }
 
 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
-		u32 pixel_fmt, u32 width)
+		     u32 pixel_fmt, struct ipu_dc_if_map *new_map, u32 width)
 {
 	struct ipu_dc_priv *priv = dc->priv;
+	struct dc_if_map_priv *map;
 	u32 reg = 0;
-	int map;
 
 	dc->di = ipu_di_get_num(di);
 
-	map = ipu_pixfmt_to_map(pixel_fmt);
-	if (map < 0) {
+	map = ipu_dc_get_map(priv, new_map, pixel_fmt);
+	if (IS_ERR(map)) {
 		dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
-		return map;
+		return PTR_ERR(map);
 	}
 
 	if (interlaced) {
@@ -187,26 +275,35 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 		dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
 
 		/* Init template microcode */
-		dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
+		dc_write_tmpl(dc, 0, WROD(0), 0, map->mapnr,
+			      SYNC_WAVE, 0, 8, 1);
 	} else {
 		if (dc->di) {
 			dc_link_event(dc, DC_EVT_NL, 2, 3);
 			dc_link_event(dc, DC_EVT_EOL, 3, 2);
 			dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
 			/* Init template microcode */
-			dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
-			dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
-			dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
-			dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+			dc_write_tmpl(dc, 2, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 8, 5, 1);
+			dc_write_tmpl(dc, 3, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 4, 5, 0);
+			dc_write_tmpl(dc, 4, WRG, 0, map->mapnr,
+				      NULL_WAVE, 0, 0, 1);
+			dc_write_tmpl(dc, 1, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 0, 5, 1);
 		} else {
 			dc_link_event(dc, DC_EVT_NL, 5, 3);
 			dc_link_event(dc, DC_EVT_EOL, 6, 2);
 			dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
 			/* Init template microcode */
-			dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
-			dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
-			dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
-			dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
+			dc_write_tmpl(dc, 5, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 8, 5, 1);
+			dc_write_tmpl(dc, 6, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 4, 5, 0);
+			dc_write_tmpl(dc, 7, WRG, 0, map->mapnr,
+				      NULL_WAVE, 0, 0, 1);
+			dc_write_tmpl(dc, 8, WROD(0), 0, map->mapnr,
+				      SYNC_WAVE, 0, 5, 1);
 		}
 	}
 	dc_link_event(dc, DC_EVT_NF, 0, 0);
@@ -298,29 +395,35 @@ void ipu_dc_disable(struct ipu_soc *ipu)
 }
 EXPORT_SYMBOL_GPL(ipu_dc_disable);
 
-static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
-		int byte_num, int offset, int mask)
+static void ipu_dc_map_config(struct ipu_dc_priv *priv,
+			      struct dc_if_map_priv *map)
 {
-	int ptr = map * 3 + byte_num;
+	int i, ptr;
 	u32 reg;
 
-	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
-	reg &= ~(0xffff << (16 * (ptr & 0x1)));
-	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
-	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
+	for (i = 0; i < 3; i++) {
+		ptr = map->mapnr * 3 + i;
 
-	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
-	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
-	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
-	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
+		reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
+		reg &= ~(0xffff << (16 * (ptr & 0x1)));
+		reg |= (((map->map.dest_msb[i] << 8) |
+			 map->map.src_mask[i]) << (16 * (ptr & 0x1)));
+		writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
+
+		reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map->mapnr));
+		reg &= ~(0x1f << ((16 * (map->mapnr & 0x1)) + (5 * i)));
+		reg |= (ptr << ((16 * (map->mapnr & 0x1)) + (5 * i)));
+		writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map->mapnr));
+	}
 }
 
-static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
+static void ipu_dc_map_clear(struct ipu_dc_priv *priv,
+			     struct dc_if_map_priv *map)
 {
-	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
+	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map->mapnr));
 
-	writel(reg & ~(0xffff << (16 * (map & 0x1))),
-		     priv->dc_reg + DC_MAP_CONF_PTR(map));
+	writel(reg & ~(0xffff << (16 * (map->mapnr & 0x1))),
+		     priv->dc_reg + DC_MAP_CONF_PTR(map->mapnr));
 }
 
 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
@@ -416,41 +519,12 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 			base, template_base);
 
-	/* rgb24 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
-
-	/* rgb565 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
-
-	/* gbr24 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
-	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
-	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
-
-	/* bgr666 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
-
-	/* lvds666 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
-	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
-	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
-
-	/* bgr24 */
-	ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
-	ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
+	/* add the pre-defined maps */
+	mutex_lock(&priv->mutex);
+	INIT_LIST_HEAD(&priv->map_list);
+	for (i = 0; i < ARRAY_SIZE(predef_maps); i++)
+		ipu_dc_new_map(priv, &predef_maps[i]);
+	mutex_unlock(&priv->mutex);
 
 	return 0;
 }
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 11e84a2..25c0231 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -186,7 +186,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
 
 	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
-			out_pixel_fmt, mode->hdisplay);
+			out_pixel_fmt, NULL, mode->hdisplay);
 	if (ret) {
 		dev_err(ipu_crtc->dev,
 				"initializing display controller failed with %d\n",
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 6fa86c7..032948b5 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -218,12 +218,33 @@ void ipu_cpmem_dump(struct ipuv3_channel *ch);
 /*
  * IPU Display Controller (dc) functions
  */
+
+/*
+ * This structure defines how to map each color component of the incoming
+ * RGB24 or YUV444 pixels arriving at the DC onto the DI bus:
+ *
+ * src_mask[] defines which bits of each incoming 8-bit RGB24/YUV444
+ *            component are to be selected and forwarded to the DI bus
+ *            (as a bit mask).
+ *
+ * dest_msb[] defines where to place the selected bits of each component
+ *            on the DI bus (as the most-significant-bit position).
+ *
+ * v4l2_fmt   non-zero if this mapping corresponds to a standard
+ *            V4L2 pixel format.
+ */
+struct ipu_dc_if_map {
+	u32 src_mask[3];
+	u32 dest_msb[3];
+	u32 v4l2_fmt;
+};
+
 struct ipu_dc;
 struct ipu_di;
 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
 void ipu_dc_put(struct ipu_dc *dc);
 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
-		u32 pixel_fmt, u32 width);
+		     u32 pixel_fmt, struct ipu_dc_if_map *new_map, u32 width);
 void ipu_dc_enable(struct ipu_soc *ipu);
 void ipu_dc_enable_channel(struct ipu_dc *dc);
 void ipu_dc_disable_channel(struct ipu_dc *dc);
-- 
1.7.9.5

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http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 10/72] gpu: ipu-v3: Add ipu_dc_uninit_sync()

[Steve Longerbeam]

Adds the function ipu_dc_uninit_sync() which tears down
ipu_dc_init_sync().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Muzaffar Mahmood <muzaffar_mahmood@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c |   14 ++++++++++++++
 include/video/imx-ipu-v3.h  |    1 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 36c7c57..6992f84 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -327,6 +327,20 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 }
 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 
+void ipu_dc_uninit_sync(struct ipu_dc *dc)
+{
+	dc_link_event(dc, DC_EVT_NL, 0, 0);
+	dc_link_event(dc, DC_EVT_EOL, 0, 0);
+	dc_link_event(dc, DC_EVT_NEW_DATA, 0, 0);
+	dc_link_event(dc, DC_EVT_NF, 0, 0);
+	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
+	dc_link_event(dc, DC_EVT_EOF, 0, 0);
+	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
+	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
+	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
+}
+EXPORT_SYMBOL_GPL(ipu_dc_uninit_sync);
+
 void ipu_dc_enable(struct ipu_soc *ipu)
 {
 	ipu_module_enable(ipu, IPU_CONF_DC_EN);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 032948b5..758c773 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -245,6 +245,7 @@ struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
 void ipu_dc_put(struct ipu_dc *dc);
 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 		     u32 pixel_fmt, struct ipu_dc_if_map *new_map, u32 width);
+void ipu_dc_uninit_sync(struct ipu_dc *dc);
 void ipu_dc_enable(struct ipu_soc *ipu);
 void ipu_dc_enable_channel(struct ipu_dc *dc);
 void ipu_dc_disable_channel(struct ipu_dc *dc);
-- 
1.7.9.5

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[PATCH 11/72] gpu: ipu-v3: Pass struct ipu_dc to enable/disable

[Steve Longerbeam]

Pass the pointer to DC channel to ipu_dc_enable() and ipu_dc_disable(),
to be more consistent with the other ipu-dc APIs.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c          |   12 ++++++++----
 drivers/staging/imx-drm/ipuv3-crtc.c |    8 ++------
 include/video/imx-ipu-v3.h           |    4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 6992f84..f53fce5 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -341,9 +341,11 @@ void ipu_dc_uninit_sync(struct ipu_dc *dc)
 }
 EXPORT_SYMBOL_GPL(ipu_dc_uninit_sync);
 
-void ipu_dc_enable(struct ipu_soc *ipu)
+void ipu_dc_enable(struct ipu_dc *dc)
 {
-	ipu_module_enable(ipu, IPU_CONF_DC_EN);
+	struct ipu_dc_priv *priv = dc->priv;
+
+	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 }
 EXPORT_SYMBOL_GPL(ipu_dc_enable);
 
@@ -403,9 +405,11 @@ void ipu_dc_disable_channel(struct ipu_dc *dc)
 }
 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 
-void ipu_dc_disable(struct ipu_soc *ipu)
+void ipu_dc_disable(struct ipu_dc *dc)
 {
-	ipu_module_disable(ipu, IPU_CONF_DC_EN);
+	struct ipu_dc_priv *priv = dc->priv;
+
+	ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
 }
 EXPORT_SYMBOL_GPL(ipu_dc_disable);
 
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 25c0231..7053619 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -60,12 +60,10 @@ struct ipu_crtc {
 
 static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
 {
-	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
-
 	if (ipu_crtc->enabled)
 		return;
 
-	ipu_dc_enable(ipu);
+	ipu_dc_enable(ipu_crtc->dc);
 	ipu_plane_enable(ipu_crtc->plane[0]);
 	/* Start DC channel and DI after IDMAC */
 	ipu_dc_enable_channel(ipu_crtc->dc);
@@ -76,8 +74,6 @@ static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
 
 static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
 {
-	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
-
 	if (!ipu_crtc->enabled)
 		return;
 
@@ -85,7 +81,7 @@ static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
 	ipu_dc_disable_channel(ipu_crtc->dc);
 	ipu_di_disable(ipu_crtc->di);
 	ipu_plane_disable(ipu_crtc->plane[0]);
-	ipu_dc_disable(ipu);
+	ipu_dc_disable(ipu_crtc->dc);
 
 	ipu_crtc->enabled = 0;
 }
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 758c773..36309b9 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -246,10 +246,10 @@ void ipu_dc_put(struct ipu_dc *dc);
 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 		     u32 pixel_fmt, struct ipu_dc_if_map *new_map, u32 width);
 void ipu_dc_uninit_sync(struct ipu_dc *dc);
-void ipu_dc_enable(struct ipu_soc *ipu);
+void ipu_dc_enable(struct ipu_dc *dc);
 void ipu_dc_enable_channel(struct ipu_dc *dc);
 void ipu_dc_disable_channel(struct ipu_dc *dc);
-void ipu_dc_disable(struct ipu_soc *ipu);
+void ipu_dc_disable(struct ipu_dc *dc);
 
 /*
  * IPU Display Interface (di) functions
-- 
1.7.9.5

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[PATCH 12/72] gpu: ipu-v3: Add ipu_dp_uninit_channel()

[Steve Longerbeam]

Adds the function ipu_dp_uninit_channel() which tears down
ipu_dp_setup_channel().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Muzaffar Mahmood <muzaffar_mahmood@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dp.c |   18 ++++++++++++++++++
 include/video/imx-ipu-v3.h  |    1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 472acd6..626f738 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -302,6 +302,16 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
 	writel(reg, flow->base + DP_COM_CONF);
 }
 
+static void ipu_dp_csc_disable(struct ipu_flow *flow)
+{
+	writel(0, flow->base + DP_CSC_A_0);
+	writel(0, flow->base + DP_CSC_A_1);
+	writel(0, flow->base + DP_CSC_A_2);
+	writel(0, flow->base + DP_CSC_A_3);
+	writel(0, flow->base + DP_CSC_0);
+	writel(0, flow->base + DP_CSC_1);
+}
+
 int ipu_dp_setup_channel(struct ipu_dp *dp,
 		enum ipu_color_space in,
 		enum ipu_color_space out)
@@ -344,6 +354,14 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
 }
 EXPORT_SYMBOL_GPL(ipu_dp_setup_channel);
 
+void ipu_dp_uninit_channel(struct ipu_dp *dp)
+{
+	struct ipu_flow *flow = to_flow(dp);
+
+	ipu_dp_csc_disable(flow);
+}
+EXPORT_SYMBOL_GPL(ipu_dp_uninit_channel);
+
 int ipu_dp_enable(struct ipu_soc *ipu)
 {
 	struct ipu_dp_priv *priv = ipu->dp_priv;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 36309b9..567ac41 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -292,6 +292,7 @@ void ipu_dp_disable_channel(struct ipu_dp *dp);
 void ipu_dp_disable(struct ipu_soc *ipu);
 int ipu_dp_setup_channel(struct ipu_dp *dp,
 		enum ipu_color_space in, enum ipu_color_space out);
+void ipu_dp_uninit_channel(struct ipu_dp *dp);
 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
 		bool bg_chan);
-- 
1.7.9.5

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[PATCH 13/72] gpu: ipu-v3: Pass struct ipu_dp to enable/disable

[Steve Longerbeam]

Pass the pointer to DP channel to ipu_dp_enable() and ipu_dp_disable(),
to be more consistent with the other ipu-dp APIs.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dp.c           |   10 ++++++----
 drivers/staging/imx-drm/ipuv3-plane.c |    4 ++--
 include/video/imx-ipu-v3.h            |    4 ++--
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 626f738..89173e5 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -362,9 +362,10 @@ void ipu_dp_uninit_channel(struct ipu_dp *dp)
 }
 EXPORT_SYMBOL_GPL(ipu_dp_uninit_channel);
 
-int ipu_dp_enable(struct ipu_soc *ipu)
+int ipu_dp_enable(struct ipu_dp *dp)
 {
-	struct ipu_dp_priv *priv = ipu->dp_priv;
+	struct ipu_flow *flow = to_flow(dp);
+	struct ipu_dp_priv *priv = flow->priv;
 
 	mutex_lock(&priv->mutex);
 
@@ -431,9 +432,10 @@ void ipu_dp_disable_channel(struct ipu_dp *dp)
 }
 EXPORT_SYMBOL_GPL(ipu_dp_disable_channel);
 
-void ipu_dp_disable(struct ipu_soc *ipu)
+void ipu_dp_disable(struct ipu_dp *dp)
 {
-	struct ipu_dp_priv *priv = ipu->dp_priv;
+	struct ipu_flow *flow = to_flow(dp);
+	struct ipu_dp_priv *priv = flow->priv;
 
 	mutex_lock(&priv->mutex);
 
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 944962b..798125e 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -236,7 +236,7 @@ err_out:
 void ipu_plane_enable(struct ipu_plane *ipu_plane)
 {
 	if (ipu_plane->dp)
-		ipu_dp_enable(ipu_plane->ipu);
+		ipu_dp_enable(ipu_plane->dp);
 	ipu_dmfc_enable_channel(ipu_plane->dmfc);
 	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
 	if (ipu_plane->dp)
@@ -256,7 +256,7 @@ void ipu_plane_disable(struct ipu_plane *ipu_plane)
 	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
 	ipu_dmfc_disable_channel(ipu_plane->dmfc);
 	if (ipu_plane->dp)
-		ipu_dp_disable(ipu_plane->ipu);
+		ipu_dp_disable(ipu_plane->dp);
 }
 
 /*
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 567ac41..1665a17 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -286,10 +286,10 @@ void ipu_dmfc_put(struct dmfc_channel *dmfc);
 
 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
 void ipu_dp_put(struct ipu_dp *);
-int ipu_dp_enable(struct ipu_soc *ipu);
+int ipu_dp_enable(struct ipu_dp *dp);
 int ipu_dp_enable_channel(struct ipu_dp *dp);
 void ipu_dp_disable_channel(struct ipu_dp *dp);
-void ipu_dp_disable(struct ipu_soc *ipu);
+void ipu_dp_disable(struct ipu_dp *dp);
 int ipu_dp_setup_channel(struct ipu_dp *dp,
 		enum ipu_color_space in, enum ipu_color_space out);
 void ipu_dp_uninit_channel(struct ipu_dp *dp);
-- 
1.7.9.5

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[PATCH 14/72] gpu: ipu-v3: Implement use counter for ipu_dc_enable(), ipu_dc_disable()

[Steve Longerbeam]

The functions ipu_dc_enable() and ipu_dc_disable() enable/disable the DC
globally in the IPU_CONF register, but the DC is used by multiple clients
on different DC channels. So make sure to only disable/enable the DC
globally based on a use counter.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c |   21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index f53fce5..79879e7 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -144,6 +144,7 @@ struct ipu_dc_priv {
 	struct completion	comp;
 	int			dc_irq;
 	int			dp_irq;
+	int			use_count;
 };
 
 /* forward references */
@@ -345,7 +346,14 @@ void ipu_dc_enable(struct ipu_dc *dc)
 {
 	struct ipu_dc_priv *priv = dc->priv;
 
-	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
+	mutex_lock(&priv->mutex);
+
+	if (!priv->use_count)
+		ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
+
+	priv->use_count++;
+
+	mutex_unlock(&priv->mutex);
 }
 EXPORT_SYMBOL_GPL(ipu_dc_enable);
 
@@ -409,7 +417,16 @@ void ipu_dc_disable(struct ipu_dc *dc)
 {
 	struct ipu_dc_priv *priv = dc->priv;
 
-	ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
+	mutex_lock(&priv->mutex);
+
+	priv->use_count--;
+	if (!priv->use_count)
+		ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
+
+	if (priv->use_count < 0)
+		priv->use_count = 0;
+
+	mutex_unlock(&priv->mutex);
 }
 EXPORT_SYMBOL_GPL(ipu_dc_disable);
 
-- 
1.7.9.5

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[PATCH 15/72] gpu: ipu-v3: fix HDMI timing issues

[Steve Longerbeam]

From: Jiada Wang <jiada_wang@mentor.com>

On some monitors, with high resolution(1920x1080), HDMI is not working,
some resolution have pixel column truncation problem
(shows 1280x1022 instead of 1280x1024), which will result in really strange
picture on some monitors.

This Patch aims to fix these HDMI timing issues.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Deepak Das <deepak_das@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c |   30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index c490ba4..2fafb63 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -511,12 +511,35 @@ static void ipu_di_config_clock(struct ipu_di *di,
 		clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
 }
 
+/*
+ * This function is called to adapt synchronous LCD panel to
+ * IPU restriction.
+ */
+static void adapt_panel_to_ipu_restricitions(struct ipu_di *di,
+					     struct ipu_di_signal_cfg *sig)
+{
+	if (sig->v_end_width < 2) {
+		uint16_t diff = 2 - sig->v_end_width;
+
+		if (sig->v_start_width >= diff) {
+			sig->v_end_width = 2;
+			sig->v_start_width -= diff;
+		} else if (sig->v_sync_width > diff) {
+			sig->v_end_width = 2;
+			sig->v_sync_width = sig->v_sync_width - diff;
+		} else
+			dev_warn(di->ipu->dev, "failed to adapt timing\n");
+
+		dev_warn(di->ipu->dev,
+			 "timing adapted due to IPU restrictions\n");
+	}
+}
+
 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 {
 	u32 reg;
 	u32 di_gen, vsync_cnt;
 	u32 div;
-	u32 h_total, v_total;
 
 	dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
 		di->id, sig->width, sig->height);
@@ -524,10 +547,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 	if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
 		return -EINVAL;
 
-	h_total = sig->width + sig->h_sync_width + sig->h_start_width +
-		sig->h_end_width;
-	v_total = sig->height + sig->v_sync_width + sig->v_start_width +
-		sig->v_end_width;
+	adapt_panel_to_ipu_restricitions(di, sig);
 
 	dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
 		clk_get_rate(di->clk_ipu),
-- 
1.7.9.5

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[PATCH 16/72] gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug

[Steve Longerbeam]

Add debug messages when these modules are globally disabled or enabled
in the IPU_CONF register.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c   |    8 ++++++--
 drivers/gpu/ipu-v3/ipu-di.c   |    2 ++
 drivers/gpu/ipu-v3/ipu-dmfc.c |    5 ++++-
 drivers/gpu/ipu-v3/ipu-dp.c   |    8 ++++++--
 4 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 79879e7..6a3e429 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -348,8 +348,10 @@ void ipu_dc_enable(struct ipu_dc *dc)
 
 	mutex_lock(&priv->mutex);
 
-	if (!priv->use_count)
+	if (!priv->use_count) {
+		dev_dbg(priv->dev, "DC enable\n");
 		ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
+	}
 
 	priv->use_count++;
 
@@ -420,8 +422,10 @@ void ipu_dc_disable(struct ipu_dc *dc)
 	mutex_lock(&priv->mutex);
 
 	priv->use_count--;
-	if (!priv->use_count)
+	if (!priv->use_count) {
+		dev_dbg(priv->dev, "DC disable\n");
 		ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
+	}
 
 	if (priv->use_count < 0)
 		priv->use_count = 0;
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 2fafb63..35ee345 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -649,6 +649,7 @@ int ipu_di_enable(struct ipu_di *di)
 	if (ret)
 		return ret;
 
+	dev_dbg(di->ipu->dev, "DI%d enable\n", di->id);
 	ipu_module_enable(di->ipu, di->module);
 
 	return 0;
@@ -659,6 +660,7 @@ int ipu_di_disable(struct ipu_di *di)
 {
 	WARN_ON(IS_ERR(di->clk_di_pixel));
 
+	dev_dbg(di->ipu->dev, "DI%d disable\n", di->id);
 	ipu_module_disable(di->ipu, di->module);
 
 	clk_disable_unprepare(di->clk_di_pixel);
diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 042c395..9ab9c87 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -127,8 +127,10 @@ int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
 	struct ipu_dmfc_priv *priv = dmfc->priv;
 	mutex_lock(&priv->mutex);
 
-	if (!priv->use_count)
+	if (!priv->use_count) {
+		dev_dbg(priv->dev, "DMFC enable\n");
 		ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
+	}
 
 	priv->use_count++;
 
@@ -162,6 +164,7 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
 
 	if (!priv->use_count) {
 		ipu_dmfc_wait_fifos(priv);
+		dev_dbg(priv->dev, "DMFC disable\n");
 		ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
 	}
 
diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 89173e5..d918596 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -369,8 +369,10 @@ int ipu_dp_enable(struct ipu_dp *dp)
 
 	mutex_lock(&priv->mutex);
 
-	if (!priv->use_count)
+	if (!priv->use_count) {
+		dev_dbg(priv->dev, "DP enable\n");
 		ipu_module_enable(priv->ipu, IPU_CONF_DP_EN);
+	}
 
 	priv->use_count++;
 
@@ -441,8 +443,10 @@ void ipu_dp_disable(struct ipu_dp *dp)
 
 	priv->use_count--;
 
-	if (!priv->use_count)
+	if (!priv->use_count) {
+		dev_dbg(priv->dev, "DP disable\n");
 		ipu_module_disable(priv->ipu, IPU_CONF_DP_EN);
+	}
 
 	if (priv->use_count < 0)
 		priv->use_count = 0;
-- 
1.7.9.5

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[PATCH 17/72] gpu: ipu-v3: Add ipu_di_uninit_sync_panel()

[Steve Longerbeam]

Adds ipu_di_uninit_sync_panel() which tears down ipu_di_init_sync_panel().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c |   18 ++++++++++++++++++
 include/video/imx-ipu-v3.h  |    1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 35ee345..9841419 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -639,6 +639,24 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 }
 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
 
+void ipu_di_uninit_sync_panel(struct ipu_di *di)
+{
+	u32 reg, di_gen;
+
+	mutex_lock(&di_mutex);
+
+	di_gen = ipu_di_read(di, DI_GENERAL);
+	di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
+	ipu_di_write(di, di_gen, DI_GENERAL);
+
+	reg = ipu_di_read(di, DI_POL);
+	reg |= 0x3ffffff;
+	ipu_di_write(di, reg, DI_POL);
+
+	mutex_unlock(&di_mutex);
+}
+EXPORT_SYMBOL(ipu_di_uninit_sync_panel);
+
 int ipu_di_enable(struct ipu_di *di)
 {
 	int ret;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 1665a17..01ab5e0 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -260,6 +260,7 @@ int ipu_di_disable(struct ipu_di *);
 int ipu_di_enable(struct ipu_di *);
 int ipu_di_get_num(struct ipu_di *);
 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
+void ipu_di_uninit_sync_panel(struct ipu_di *di);
 
 /*
  * IPU Display Multi FIFO Controller (dmfc) functions
-- 
1.7.9.5

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[PATCH 18/72] gpu: ipu-v3: Split out DI clock enable/disable

[Steve Longerbeam]

DI clock enable/disable is moved out of ipu_di_enable() and ipu_di_disable()
and into (new) ipu_di_enable_clock() and ipu_di_disable_clock(). So
ipu_di_enable() and ipu_di_disable() are now pure module enable/disable.

The purpose of this change is to more closely emulate the display mode
setting sequence in FSL kernels, which enable and disable the DI
clock as the very last steps during legacy fbdev set_par().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c          |   20 +++++++++++++-------
 drivers/staging/imx-drm/ipuv3-crtc.c |    2 ++
 include/video/imx-ipu-v3.h           |    2 ++
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 9841419..7ab19a3 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -659,14 +659,8 @@ EXPORT_SYMBOL(ipu_di_uninit_sync_panel);
 
 int ipu_di_enable(struct ipu_di *di)
 {
-	int ret;
-
 	WARN_ON(IS_ERR(di->clk_di_pixel));
 
-	ret = clk_prepare_enable(di->clk_di_pixel);
-	if (ret)
-		return ret;
-
 	dev_dbg(di->ipu->dev, "DI%d enable\n", di->id);
 	ipu_module_enable(di->ipu, di->module);
 
@@ -674,6 +668,12 @@ int ipu_di_enable(struct ipu_di *di)
 }
 EXPORT_SYMBOL_GPL(ipu_di_enable);
 
+int ipu_di_enable_clock(struct ipu_di *di)
+{
+	return clk_prepare_enable(di->clk_di_pixel);
+}
+EXPORT_SYMBOL_GPL(ipu_di_enable_clock);
+
 int ipu_di_disable(struct ipu_di *di)
 {
 	WARN_ON(IS_ERR(di->clk_di_pixel));
@@ -681,11 +681,17 @@ int ipu_di_disable(struct ipu_di *di)
 	dev_dbg(di->ipu->dev, "DI%d disable\n", di->id);
 	ipu_module_disable(di->ipu, di->module);
 
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ipu_di_disable);
+
+int ipu_di_disable_clock(struct ipu_di *di)
+{
 	clk_disable_unprepare(di->clk_di_pixel);
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(ipu_di_disable);
+EXPORT_SYMBOL_GPL(ipu_di_disable_clock);
 
 int ipu_di_get_num(struct ipu_di *di)
 {
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 7053619..be24cb9 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -68,6 +68,7 @@ static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
 	/* Start DC channel and DI after IDMAC */
 	ipu_dc_enable_channel(ipu_crtc->dc);
 	ipu_di_enable(ipu_crtc->di);
+	ipu_di_enable_clock(ipu_crtc->di);
 
 	ipu_crtc->enabled = 1;
 }
@@ -82,6 +83,7 @@ static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
 	ipu_di_disable(ipu_crtc->di);
 	ipu_plane_disable(ipu_crtc->plane[0]);
 	ipu_dc_disable(ipu_crtc->dc);
+	ipu_di_disable_clock(ipu_crtc->di);
 
 	ipu_crtc->enabled = 0;
 }
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 01ab5e0..31b6fde 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -257,7 +257,9 @@ void ipu_dc_disable(struct ipu_dc *dc);
 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
 void ipu_di_put(struct ipu_di *);
 int ipu_di_disable(struct ipu_di *);
+int ipu_di_disable_clock(struct ipu_di *di);
 int ipu_di_enable(struct ipu_di *);
+int ipu_di_enable_clock(struct ipu_di *di);
 int ipu_di_get_num(struct ipu_di *);
 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
 void ipu_di_uninit_sync_panel(struct ipu_di *di);
-- 
1.7.9.5

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[PATCH 19/72] gpu: ipu-v3: Protect more CM reg access with IPU lock

[Steve Longerbeam]

Some cm_reg accesses were not being protected by the IPU spin lock.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |   22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index f707d25..d3af206 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -46,11 +46,16 @@ static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
 
 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
 {
+	unsigned long flags;
 	u32 val;
 
+	spin_lock_irqsave(&ipu->lock, flags);
+
 	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
 	val |= 0x8;
 	ipu_cm_write(ipu, val, IPU_SRM_PRI2);
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
 }
 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
 
@@ -451,8 +456,17 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 {
 	struct ipu_soc *ipu = channel->ipu;
 	unsigned int chno = channel->num;
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&ipu->lock, flags);
 
-	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
+	ret = (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ?
+		1 : 0;
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 
@@ -569,10 +583,14 @@ EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 
 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 {
-	unsigned long timeout;
+	unsigned long flags, timeout;
 
 	timeout = jiffies + msecs_to_jiffies(ms);
+
+	spin_lock_irqsave(&ipu->lock, flags);
 	ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
+	spin_unlock_irqrestore(&ipu->lock, flags);
+
 	while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 		if (time_after(jiffies, timeout))
 			return -ETIMEDOUT;
-- 
1.7.9.5

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[PATCH 20/72] gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di

[Steve Longerbeam]

Move the DI waveform counter enable/disable out of
ipu_module_enable()/disable(). This should be carried out
when enabling/disabling the DI pixel clock.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |   37 +++++++++++++++++++------------------
 drivers/gpu/ipu-v3/ipu-di.c     |   13 ++++++++++++-
 drivers/gpu/ipu-v3/ipu-prv.h    |    1 +
 3 files changed, 32 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index d3af206..5004f71 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -59,6 +59,25 @@ void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
 }
 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
 
+void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable)
+{
+	unsigned long flags;
+	u32 val, mask;
+
+	mask = di ? IPU_DI1_COUNTER_RELEASE : IPU_DI0_COUNTER_RELEASE;
+
+	spin_lock_irqsave(&ipu->lock, flags);
+
+	val = ipu_cm_read(ipu, IPU_DISP_GEN);
+	if (enable)
+		val |= mask;
+	else
+		val &= ~mask;
+	ipu_cm_write(ipu, val, IPU_DISP_GEN);
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
+}
+
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
 {
 	switch (drm_fourcc) {
@@ -407,15 +426,6 @@ int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 
 	spin_lock_irqsave(&ipu->lock, lock_flags);
 
-	val = ipu_cm_read(ipu, IPU_DISP_GEN);
-
-	if (mask & IPU_CONF_DI0_EN)
-		val |= IPU_DI0_COUNTER_RELEASE;
-	if (mask & IPU_CONF_DI1_EN)
-		val |= IPU_DI1_COUNTER_RELEASE;
-
-	ipu_cm_write(ipu, val, IPU_DISP_GEN);
-
 	val = ipu_cm_read(ipu, IPU_CONF);
 	val |= mask;
 	ipu_cm_write(ipu, val, IPU_CONF);
@@ -437,15 +447,6 @@ int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 	val &= ~mask;
 	ipu_cm_write(ipu, val, IPU_CONF);
 
-	val = ipu_cm_read(ipu, IPU_DISP_GEN);
-
-	if (mask & IPU_CONF_DI0_EN)
-		val &= ~IPU_DI0_COUNTER_RELEASE;
-	if (mask & IPU_CONF_DI1_EN)
-		val &= ~IPU_DI1_COUNTER_RELEASE;
-
-	ipu_cm_write(ipu, val, IPU_DISP_GEN);
-
 	spin_unlock_irqrestore(&ipu->lock, lock_flags);
 
 	return 0;
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 7ab19a3..5686969 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -670,7 +670,16 @@ EXPORT_SYMBOL_GPL(ipu_di_enable);
 
 int ipu_di_enable_clock(struct ipu_di *di)
 {
-	return clk_prepare_enable(di->clk_di_pixel);
+	int ret;
+
+	ret = clk_prepare_enable(di->clk_di_pixel);
+	if (ret)
+		return ret;
+
+	ipu_enable_di_counter(di->ipu, di->id, true);
+
+	return 0;
+
 }
 EXPORT_SYMBOL_GPL(ipu_di_enable_clock);
 
@@ -687,6 +696,8 @@ EXPORT_SYMBOL_GPL(ipu_di_disable);
 
 int ipu_di_disable_clock(struct ipu_di *di)
 {
+	ipu_enable_di_counter(di->ipu, di->id, false);
+
 	clk_disable_unprepare(di->clk_di_pixel);
 
 	return 0;
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index bfb1e8a..7797894 100644
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -184,6 +184,7 @@ static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
 }
 
 void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
+void ipu_enable_di_counter(struct ipu_soc *ipu, int di, bool enable);
 
 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
-- 
1.7.9.5

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[PATCH 21/72] gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()

[Steve Longerbeam]

In Freescale kernels, when a DP channel is enabled, the DP sync
SRM is updated for both background and foreground DP channels. Do
the same.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dp.c |   11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index d918596..a31b4a5 100644
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -388,14 +388,13 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
 	struct ipu_dp_priv *priv = flow->priv;
 	u32 reg;
 
-	if (!dp->foreground)
-		return 0;
-
 	mutex_lock(&priv->mutex);
 
-	reg = readl(flow->base + DP_COM_CONF);
-	reg |= DP_COM_CONF_FG_EN;
-	writel(reg, flow->base + DP_COM_CONF);
+	if (dp->foreground) {
+		reg = readl(flow->base + DP_COM_CONF);
+		reg |= DP_COM_CONF_FG_EN;
+		writel(reg, flow->base + DP_COM_CONF);
+	}
 
 	ipu_srm_dp_sync_update(priv->ipu);
 
-- 
1.7.9.5

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[PATCH 22/72] gpu: ipu-v3: Fix indent/ws in ipu-dmfc

[Steve Longerbeam]

Cleanup indentation and whitespace in ipu-dmfc.c. No functional
changes.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dmfc.c |   30 ++++++++++++++++--------------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 9ab9c87..307020e 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -125,6 +125,7 @@ struct ipu_dmfc_priv {
 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
 {
 	struct ipu_dmfc_priv *priv = dmfc->priv;
+
 	mutex_lock(&priv->mutex);
 
 	if (!priv->use_count) {
@@ -176,14 +177,14 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
 EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
 
 static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
-		int segment, int burstsize)
+				  int segment, int burstsize)
 {
 	struct ipu_dmfc_priv *priv = dmfc->priv;
 	u32 val, field;
 
 	dev_dbg(priv->dev,
-			"dmfc: using %d slots starting from segment %d for IPU channel %d\n",
-			slots, segment, dmfc->data->ipu_channel);
+		"dmfc: using %d slots starting from segment %d for IPU channel %d\n",
+		slots, segment, dmfc->data->ipu_channel);
 
 	switch (slots) {
 	case 1:
@@ -235,7 +236,7 @@ static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
 }
 
 static int dmfc_bandwidth_to_slots(struct ipu_dmfc_priv *priv,
-		unsigned long bandwidth)
+				   unsigned long bandwidth)
 {
 	int slots = 1;
 
@@ -272,7 +273,7 @@ void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
 	int i;
 
 	dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
-			dmfc->slots, dmfc->segment);
+		dmfc->slots, dmfc->segment);
 
 	mutex_lock(&priv->mutex);
 
@@ -299,9 +300,9 @@ void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
 	for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
 		if (priv->channels[i].slots > 0)
 			ipu_dmfc_setup_channel(&priv->channels[i],
-					priv->channels[i].slots,
-					priv->channels[i].segment,
-					priv->channels[i].burstsize);
+					       priv->channels[i].slots,
+					       priv->channels[i].segment,
+					       priv->channels[i].burstsize);
 	}
 out:
 	mutex_unlock(&priv->mutex);
@@ -309,15 +310,16 @@ out:
 EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
 
 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
-		unsigned long bandwidth_pixel_per_second, int burstsize)
+			     unsigned long bandwidth_pixel_per_second,
+			     int burstsize)
 {
 	struct ipu_dmfc_priv *priv = dmfc->priv;
 	int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
 	int segment = -1, ret = 0;
 
-	dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
-			bandwidth_pixel_per_second / 1000000,
-			dmfc->data->ipu_channel);
+	dev_dbg(priv->dev,
+		"dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
+		bandwidth_pixel_per_second / 1000000, dmfc->data->ipu_channel);
 
 	ipu_dmfc_free_bandwidth(dmfc);
 
@@ -390,7 +392,7 @@ void ipu_dmfc_put(struct dmfc_channel *dmfc)
 EXPORT_SYMBOL_GPL(ipu_dmfc_put);
 
 int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
-		struct clk *ipu_clk)
+		  struct clk *ipu_clk)
 {
 	struct ipu_dmfc_priv *priv;
 	int i;
@@ -425,7 +427,7 @@ int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
 	priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;
 
 	dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
-			priv->bandwidth_per_slot / 1000000);
+		priv->bandwidth_per_slot / 1000000);
 
 	writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
 	writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
-- 
1.7.9.5

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[PATCH 23/72] gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()

[Steve Longerbeam]

IDMAC channels can have a burtsize of 20 pixels, so allow for that in
ipu_dmfc_setup_channel().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dmfc.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 307020e..37a0e41 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -207,6 +207,7 @@ static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
 	case 16:
 		field |= DMFC_BURSTSIZE_16;
 		break;
+	case 20:
 	case 32:
 		field |= DMFC_BURSTSIZE_32;
 		break;
-- 
1.7.9.5

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[PATCH 24/72] gpu: ipu-v3: Remove ipu_dmfc_init_channel()

[Steve Longerbeam]

The function ipu_dmfc_init_channel() sets the "WAIT4EOT" mode according
to the line width and the DMFC channel's FIFO size (the slots parameter).
But this can only happen after slots has been calculated in
ipu_dmfc_alloc_bandwidth().

Fix by renaming ipu_dmfc_init_channel() to a static dmfc_set_wait_eot()
which is called at the end of ipu_dmfc_alloc_bandwidth(), after slots
has been calculated.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dmfc.c         |   41 +++++++++++++++++----------------
 drivers/staging/imx-drm/ipuv3-plane.c |    8 +------
 include/video/imx-ipu-v3.h            |    3 +--
 3 files changed, 23 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 37a0e41..6ef4932 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -176,6 +176,21 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
 }
 EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
 
+static void dmfc_set_wait_eot(struct dmfc_channel *dmfc, int width)
+{
+	struct ipu_dmfc_priv *priv = dmfc->priv;
+	u32 dmfc_gen1;
+
+	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
+
+	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
+		dmfc_gen1 |= 1 << dmfc->data->eot_shift;
+	else
+		dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
+
+	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
+}
+
 static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
 				  int segment, int burstsize)
 {
@@ -312,7 +327,7 @@ EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
 
 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
 			     unsigned long bandwidth_pixel_per_second,
-			     int burstsize)
+			     int width, int burstsize)
 {
 	struct ipu_dmfc_priv *priv = dmfc->priv;
 	int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
@@ -347,7 +362,11 @@ int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
 		goto out;
 	}
 
-	ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);
+	ret = ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);
+	if (ret)
+		goto out;
+
+	dmfc_set_wait_eot(dmfc, width);
 
 out:
 	mutex_unlock(&priv->mutex);
@@ -356,24 +375,6 @@ out:
 }
 EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
 
-int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
-{
-	struct ipu_dmfc_priv *priv = dmfc->priv;
-	u32 dmfc_gen1;
-
-	dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
-
-	if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
-		dmfc_gen1 |= 1 << dmfc->data->eot_shift;
-	else
-		dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
-
-	writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
-
-	return 0;
-}
-EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);
-
 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
 {
 	struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 798125e..365cdfe 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -158,15 +158,9 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		break;
 	}
 
-	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
-	if (ret) {
-		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
-		return ret;
-	}
-
 	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
 			calc_bandwidth(crtc_w, crtc_h,
-				       calc_vref(mode)), 64);
+				       calc_vref(mode)), crtc_w, 64);
 	if (ret) {
 		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
 		return ret;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 31b6fde..0eb7468 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -271,9 +271,8 @@ struct dmfc_channel;
 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
-		unsigned long bandwidth_mbs, int burstsize);
+		unsigned long bandwidth, int width, int burstsize);
 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
-int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
 void ipu_dmfc_put(struct dmfc_channel *dmfc);
 
-- 
1.7.9.5

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[PATCH 25/72] gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()

[Steve Longerbeam]

The dmfc mutex was being acquired in ipu_dmfc_free_bandwidth(), freed,
then immediately re-acquired in ipu_dmfc_alloc_bandwidth(). Acquire
the lock once at the beginning of ipu_dmfc_alloc_bandwidth().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dmfc.c |   19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 6ef4932..1823004 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -283,7 +283,7 @@ static int dmfc_find_slots(struct ipu_dmfc_priv *priv, int slots)
 	return -EBUSY;
 }
 
-void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
+static void dmfc_free_bandwidth(struct dmfc_channel *dmfc)
 {
 	struct ipu_dmfc_priv *priv = dmfc->priv;
 	int i;
@@ -291,10 +291,8 @@ void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
 	dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
 		dmfc->slots, dmfc->segment);
 
-	mutex_lock(&priv->mutex);
-
 	if (!dmfc->slots)
-		goto out;
+		return;
 
 	dmfc->slotmask = 0;
 	dmfc->slots = 0;
@@ -320,7 +318,14 @@ void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
 					       priv->channels[i].segment,
 					       priv->channels[i].burstsize);
 	}
-out:
+}
+
+void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
+{
+	struct ipu_dmfc_priv *priv = dmfc->priv;
+
+	mutex_lock(&priv->mutex);
+	dmfc_free_bandwidth(dmfc);
 	mutex_unlock(&priv->mutex);
 }
 EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
@@ -337,10 +342,10 @@ int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
 		"dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
 		bandwidth_pixel_per_second / 1000000, dmfc->data->ipu_channel);
 
-	ipu_dmfc_free_bandwidth(dmfc);
-
 	mutex_lock(&priv->mutex);
 
+	dmfc_free_bandwidth(dmfc);
+
 	if (slots > 8) {
 		ret = -EBUSY;
 		goto out;
-- 
1.7.9.5

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[PATCH 26/72] gpu: ipu-v3: Enumerate the DC channel names

[Steve Longerbeam]

Define the names of the DC channels, and reference them in ipu-dc.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c |    6 ++----
 include/video/imx-ipu-v3.h  |    7 +++++++
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 6a3e429..23b6e2c 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -83,8 +83,6 @@
 #define DC_WR_CH_CONF_PROG_DI_ID		(1 << 2)
 #define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)
 
-#define IPU_DC_NUM_CHANNELS	10
-
 struct ipu_dc_priv;
 
 /* some pre-defined maps */
@@ -394,9 +392,9 @@ void ipu_dc_disable_channel(struct ipu_dc *dc)
 	u32 val;
 
 	/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
-	if (dc->chno == 1)
+	if (dc->chno == IPU_DC_CHANNEL_SYNC)
 		irq = priv->dc_irq;
-	else if (dc->chno == 5)
+	else if (dc->chno == IPU_DC_CHANNEL_DP_SYNC)
 		irq = priv->dp_irq;
 	else
 		return;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 0eb7468..d2f621d 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -239,6 +239,13 @@ struct ipu_dc_if_map {
 	u32 v4l2_fmt;
 };
 
+#define IPU_DC_CHANNEL_DP_SYNC       5 /* sync main+aux planes */
+#define IPU_DC_CHANNEL_SYNC          1 /* sync single plane (no DP) */
+#define IPU_DC_CHANNEL_DP_ASYNC      6 /* async main+aux planes */
+#define IPU_DC_CHANNEL_ASYNC         2 /* async single plane (no DP) */
+#define IPU_DC_CHANNEL_READ          0 /* DC read channel */
+#define IPU_DC_NUM_CHANNELS         10
+
 struct ipu_dc;
 struct ipu_di;
 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
-- 
1.7.9.5

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[PATCH 27/72] gpu: ipu-di: Move ipu pointer init

[Steve Longerbeam]

Move the init of di->ipu pointer to near top of ipu_di_init().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 5686969..70bf594 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -765,6 +765,7 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
 	if (IS_ERR(di->clk_di))
 		return PTR_ERR(di->clk_di);
 
+	di->ipu = ipu;
 	di->module = module;
 	di->id = id;
 	di->clk_ipu = clk_ipu;
@@ -777,7 +778,6 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
 	dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
 			id, base, di->base);
 	di->inuse = false;
-	di->ipu = ipu;
 
 	return 0;
 }
-- 
1.7.9.5

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[PATCH 28/72] gpu: ipu-di: Add and improve debug/error messages

[Steve Longerbeam]

Add a couple error messages to ipu_di_init() for better IPU
load/unload debug. Add more debug messages.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c |   30 ++++++++++++++++++++----------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 70bf594..47615ce 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -172,7 +172,7 @@ static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
 				(c->repeat_count >= 0x1000) ||
 				(c->cnt_up >= 0x400) ||
 				(c->cnt_down >= 0x400)) {
-			dev_err(di->ipu->dev, "DI%d counters out of range.\n",
+			dev_err(di->ipu->dev, "di%d counters out of range.\n",
 					di->id);
 			return;
 		}
@@ -459,8 +459,10 @@ static void ipu_di_config_clock(struct ipu_di *di,
 
 		error = rate / (sig->pixelclock / 1000);
 
-		dev_dbg(di->ipu->dev, "  IPU clock can give %lu with divider %u, error %d.%u%%\n",
-			rate, div, (signed)(error - 1000) / 10, error % 10);
+		dev_dbg(di->ipu->dev,
+			"di%d: IPU clock can give %lu with divider %u, error %d.%u%%\n",
+			di->id, rate, div, (signed)(error - 1000) / 10,
+			error % 10);
 
 		/* Allow a 1% error */
 		if (error < 1010 && error >= 990) {
@@ -503,7 +505,9 @@ static void ipu_di_config_clock(struct ipu_di *di,
 		val |= DI_GEN_DI_CLK_EXT;
 	ipu_di_write(di, val, DI_GENERAL);
 
-	dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
+	dev_dbg(di->ipu->dev,
+		"di%d: Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
+		di->id,
 		sig->pixelclock,
 		clk_get_rate(di->clk_ipu),
 		clk_get_rate(di->clk_di),
@@ -528,10 +532,12 @@ static void adapt_panel_to_ipu_restricitions(struct ipu_di *di,
 			sig->v_end_width = 2;
 			sig->v_sync_width = sig->v_sync_width - diff;
 		} else
-			dev_warn(di->ipu->dev, "failed to adapt timing\n");
+			dev_warn(di->ipu->dev,
+				 "di%d: failed to adapt timing\n", di->id);
 
 		dev_warn(di->ipu->dev,
-			 "timing adapted due to IPU restrictions\n");
+			 "di%d: timing adapted due to IPU restrictions\n",
+			 di->id);
 	}
 }
 
@@ -541,7 +547,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 	u32 di_gen, vsync_cnt;
 	u32 div;
 
-	dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
+	dev_dbg(di->ipu->dev, "di%d: panel size = %d x %d\n",
 		di->id, sig->width, sig->height);
 
 	if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
@@ -549,7 +555,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 	adapt_panel_to_ipu_restricitions(di, sig);
 
-	dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
+	dev_dbg(di->ipu->dev,
+		"di%d: Clocks: IPU %luHz DI %luHz Needed %luHz\n",
+		di->id,
 		clk_get_rate(di->clk_ipu),
 		clk_get_rate(di->clk_di),
 		sig->pixelclock);
@@ -762,8 +770,10 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
 	ipu->di_priv[id] = di;
 
 	di->clk_di = devm_clk_get(dev, id ? "di1" : "di0");
-	if (IS_ERR(di->clk_di))
+	if (IS_ERR(di->clk_di)) {
+		dev_err(dev, "di%d: could not get clock\n", id);
 		return PTR_ERR(di->clk_di);
+	}
 
 	di->ipu = ipu;
 	di->module = module;
@@ -775,7 +785,7 @@ int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
 
 	ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
 
-	dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
+	dev_dbg(dev, "di%d: base: 0x%08lx remapped to %p\n",
 			id, base, di->base);
 	di->inuse = false;
 
-- 
1.7.9.5

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[PATCH 29/72] gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg

[Steve Longerbeam]

This patch changes signal names in struct ipu_di_signal_cfg
as per the industry standard names, and renames fields that
were using CamelCase.

Signed-off-by: Deepak Das <deepak_das@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c          |   68 +++++++++++++++++-----------------
 drivers/staging/imx-drm/ipuv3-crtc.c |   16 ++++----
 include/video/imx-ipu-v3.h           |   16 ++++----
 3 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index 47615ce..b306f07 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -207,10 +207,10 @@ static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
 static void ipu_di_sync_config_interlaced(struct ipu_di *di,
 		struct ipu_di_signal_cfg *sig)
 {
-	u32 h_total = sig->width + sig->h_sync_width +
-		sig->h_start_width + sig->h_end_width;
-	u32 v_total = sig->height + sig->v_sync_width +
-		sig->v_start_width + sig->v_end_width;
+	u32 h_total = sig->width + sig->h_sync_len +
+		sig->h_back_porch + sig->h_front_porch;
+	u32 v_total = sig->height + sig->v_sync_len +
+		sig->v_back_porch + sig->v_front_porch;
 	u32 reg;
 	struct di_sync_config cfg[] = {
 		{
@@ -229,7 +229,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
 		}, {
 			.run_count = v_total / 2 - 1,
 			.run_src = DI_SYNC_HSYNC,
-			.offset_count = sig->v_start_width,
+			.offset_count = sig->v_back_porch,
 			.offset_src = DI_SYNC_HSYNC,
 			.repeat_count = 2,
 			.cnt_clr_src = DI_SYNC_VSYNC,
@@ -249,7 +249,7 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
 			.cnt_clr_src = DI_SYNC_VSYNC,
 		}, {
 			.run_src = DI_SYNC_CLK,
-			.offset_count = sig->h_start_width,
+			.offset_count = sig->h_back_porch,
 			.offset_src = DI_SYNC_CLK,
 			.repeat_count = sig->width,
 			.cnt_clr_src = 5,
@@ -277,10 +277,10 @@ static void ipu_di_sync_config_interlaced(struct ipu_di *di,
 static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 		struct ipu_di_signal_cfg *sig, int div)
 {
-	u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
-		sig->h_end_width;
-	u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
-		sig->v_end_width;
+	u32 h_total = sig->width + sig->h_sync_len + sig->h_back_porch +
+		sig->h_front_porch;
+	u32 v_total = sig->height + sig->v_sync_len + sig->v_back_porch +
+		sig->v_front_porch;
 	struct di_sync_config cfg[] = {
 		{
 			/* 1: INT_HSYNC */
@@ -294,25 +294,25 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 			.offset_src = DI_SYNC_CLK,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
-			.cnt_down = sig->h_sync_width * 2,
+			.cnt_down = sig->h_sync_len * 2,
 		} , {
 			/* PIN3: VSYNC */
 			.run_count = v_total - 1,
 			.run_src = DI_SYNC_INT_HSYNC,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
-			.cnt_down = sig->v_sync_width * 2,
+			.cnt_down = sig->v_sync_len * 2,
 		} , {
 			/* 4: Line Active */
 			.run_src = DI_SYNC_HSYNC,
-			.offset_count = sig->v_sync_width + sig->v_start_width,
+			.offset_count = sig->v_sync_len + sig->v_back_porch,
 			.offset_src = DI_SYNC_HSYNC,
 			.repeat_count = sig->height,
 			.cnt_clr_src = DI_SYNC_VSYNC,
 		} , {
 			/* 5: Pixel Active, referenced by DC */
 			.run_src = DI_SYNC_CLK,
-			.offset_count = sig->h_sync_width + sig->h_start_width,
+			.offset_count = sig->h_sync_len + sig->h_back_porch,
 			.offset_src = DI_SYNC_CLK,
 			.repeat_count = sig->width,
 			.cnt_clr_src = 5, /* Line Active */
@@ -339,7 +339,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 		} , {
 			/* 3: Line Active */
 			.run_src = DI_SYNC_INT_HSYNC,
-			.offset_count = sig->v_sync_width + sig->v_start_width,
+			.offset_count = sig->v_sync_len + sig->v_back_porch,
 			.offset_src = DI_SYNC_INT_HSYNC,
 			.repeat_count = sig->height,
 			.cnt_clr_src = 3 /* VSYNC */,
@@ -351,11 +351,11 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 			.offset_src = DI_SYNC_CLK,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
-			.cnt_down = sig->h_sync_width * 2,
+			.cnt_down = sig->h_sync_len * 2,
 		} , {
 			/* 5: Pixel Active signal to DC */
 			.run_src = DI_SYNC_CLK,
-			.offset_count = sig->h_sync_width + sig->h_start_width,
+			.offset_count = sig->h_sync_len + sig->h_back_porch,
 			.offset_src = DI_SYNC_CLK,
 			.repeat_count = sig->width,
 			.cnt_clr_src = 4, /* Line Active */
@@ -367,7 +367,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 			.offset_src = DI_SYNC_INT_HSYNC,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
-			.cnt_down = sig->v_sync_width * 2,
+			.cnt_down = sig->v_sync_len * 2,
 		} , {
 			/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */
 			.run_count = h_total - 1,
@@ -376,7 +376,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 			.offset_src = DI_SYNC_CLK,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_CLK,
-			.cnt_down = sig->h_sync_width * 2,
+			.cnt_down = sig->h_sync_len * 2,
 		} , {
 			/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */
 			.run_count = v_total - 1,
@@ -385,7 +385,7 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 			.offset_src = DI_SYNC_INT_HSYNC,
 			.cnt_polarity_gen_en = 1,
 			.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
-			.cnt_down = sig->v_sync_width * 2,
+			.cnt_down = sig->v_sync_len * 2,
 		} , {
 			/* unused */
 		},
@@ -522,15 +522,15 @@ static void ipu_di_config_clock(struct ipu_di *di,
 static void adapt_panel_to_ipu_restricitions(struct ipu_di *di,
 					     struct ipu_di_signal_cfg *sig)
 {
-	if (sig->v_end_width < 2) {
-		uint16_t diff = 2 - sig->v_end_width;
-
-		if (sig->v_start_width >= diff) {
-			sig->v_end_width = 2;
-			sig->v_start_width -= diff;
-		} else if (sig->v_sync_width > diff) {
-			sig->v_end_width = 2;
-			sig->v_sync_width = sig->v_sync_width - diff;
+	if (sig->v_front_porch < 2) {
+		uint16_t diff = 2 - sig->v_front_porch;
+
+		if (sig->v_back_porch >= diff) {
+			sig->v_front_porch = 2;
+			sig->v_back_porch -= diff;
+		} else if (sig->v_sync_len > diff) {
+			sig->v_front_porch = 2;
+			sig->v_sync_len = sig->v_sync_len - diff;
 		} else
 			dev_warn(di->ipu->dev,
 				 "di%d: failed to adapt timing\n", di->id);
@@ -550,7 +550,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 	dev_dbg(di->ipu->dev, "di%d: panel size = %d x %d\n",
 		di->id, sig->width, sig->height);
 
-	if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
+	if ((sig->v_sync_len == 0) || (sig->h_sync_len == 0))
 		return -EINVAL;
 
 	adapt_panel_to_ipu_restricitions(di, sig);
@@ -589,9 +589,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 		vsync_cnt = 7;
 
-		if (sig->Hsync_pol)
+		if (sig->hsync_pol)
 			di_gen |= DI_GEN_POLARITY_3;
-		if (sig->Vsync_pol)
+		if (sig->vsync_pol)
 			di_gen |= DI_GEN_POLARITY_2;
 	} else {
 		ipu_di_sync_config_noninterlaced(di, sig, div);
@@ -605,7 +605,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 			if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
 				vsync_cnt = 6;
 
-		if (sig->Hsync_pol) {
+		if (sig->hsync_pol) {
 			if (sig->hsync_pin == 2)
 				di_gen |= DI_GEN_POLARITY_2;
 			else if (sig->hsync_pin == 4)
@@ -613,7 +613,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 			else if (sig->hsync_pin == 7)
 				di_gen |= DI_GEN_POLARITY_7;
 		}
-		if (sig->Vsync_pol) {
+		if (sig->vsync_pol) {
 			if (sig->vsync_pin == 3)
 				di_gen |= DI_GEN_POLARITY_3;
 			else if (sig->vsync_pin == 6)
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index be24cb9..8b4440a 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -159,22 +159,22 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		sig_cfg.interlaced = 1;
 	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
-		sig_cfg.Hsync_pol = 1;
+		sig_cfg.hsync_pol = 1;
 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
-		sig_cfg.Vsync_pol = 1;
+		sig_cfg.vsync_pol = 1;
 
 	sig_cfg.enable_pol = 1;
 	sig_cfg.clk_pol = 0;
 	sig_cfg.width = mode->hdisplay;
 	sig_cfg.height = mode->vdisplay;
 	sig_cfg.pixel_fmt = out_pixel_fmt;
-	sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
-	sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
-	sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
+	sig_cfg.h_back_porch = mode->htotal - mode->hsync_end;
+	sig_cfg.h_sync_len = mode->hsync_end - mode->hsync_start;
+	sig_cfg.h_front_porch = mode->hsync_start - mode->hdisplay;
 
-	sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
-	sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
-	sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
+	sig_cfg.v_back_porch = mode->vtotal - mode->vsync_end;
+	sig_cfg.v_sync_len = mode->vsync_end - mode->vsync_start;
+	sig_cfg.v_front_porch = mode->vsync_start - mode->vdisplay;
 	sig_cfg.pixelclock = mode->clock * 1000;
 	sig_cfg.clkflags = ipu_crtc->di_clkflags;
 
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index d2f621d..7e1bc61 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -40,18 +40,18 @@ struct ipu_di_signal_cfg {
 	unsigned data_pol:1;	/* true = inverted */
 	unsigned clk_pol:1;	/* true = rising edge */
 	unsigned enable_pol:1;
-	unsigned Hsync_pol:1;	/* true = active high */
-	unsigned Vsync_pol:1;
+	unsigned hsync_pol:1;	/* true = active high */
+	unsigned vsync_pol:1;
 
 	u16 width;
 	u16 height;
 	u32 pixel_fmt;
-	u16 h_start_width;
-	u16 h_sync_width;
-	u16 h_end_width;
-	u16 v_start_width;
-	u16 v_sync_width;
-	u16 v_end_width;
+	u16 h_back_porch;
+	u16 h_sync_len;
+	u16 h_front_porch;
+	u16 v_back_porch;
+	u16 v_sync_len;
+	u16 v_front_porch;
 	u32 v_to_h_sync;
 	unsigned long pixelclock;
 #define IPU_DI_CLKMODE_SYNC	(1 << 0)
-- 
1.7.9.5

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[PATCH 30/72] gpu: ipu-v3: Remove IPU client registration

[Steve Longerbeam]

The IPU client devices have been moved to the device tree, so
remove platform registration of those devices. As a result,
platform data (struct ipu_client_platformdata) is no longer
needed, the client data is retrieved from the device nodes.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |  114 ---------------------------------------
 include/video/imx-ipu-v3.h      |    9 ----
 2 files changed, 123 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 5004f71..ebafcf2 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -990,110 +990,6 @@ static void ipu_submodules_exit(struct ipu_soc *ipu)
 	ipu_cpmem_exit(ipu);
 }
 
-static int platform_remove_devices_fn(struct device *dev, void *unused)
-{
-	struct platform_device *pdev = to_platform_device(dev);
-
-	platform_device_unregister(pdev);
-
-	return 0;
-}
-
-static void platform_device_unregister_children(struct platform_device *pdev)
-{
-	device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
-}
-
-struct ipu_platform_reg {
-	struct ipu_client_platformdata pdata;
-	const char *name;
-	int reg_offset;
-};
-
-static const struct ipu_platform_reg client_reg[] = {
-	{
-		.pdata = {
-			.di = 0,
-			.dc = 5,
-			.dp = IPU_DP_FLOW_SYNC_BG,
-			.dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
-			.dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
-		},
-		.name = "imx-ipuv3-crtc",
-	}, {
-		.pdata = {
-			.di = 1,
-			.dc = 1,
-			.dp = -EINVAL,
-			.dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
-			.dma[1] = -EINVAL,
-		},
-		.name = "imx-ipuv3-crtc",
-	}, {
-		.pdata = {
-			.csi = 0,
-			.dma[0] = IPUV3_CHANNEL_CSI0,
-			.dma[1] = -EINVAL,
-		},
-		.reg_offset = IPU_CM_CSI0_REG_OFS,
-		.name = "imx-ipuv3-camera",
-	}, {
-		.pdata = {
-			.csi = 1,
-			.dma[0] = IPUV3_CHANNEL_CSI1,
-			.dma[1] = -EINVAL,
-		},
-		.reg_offset = IPU_CM_CSI1_REG_OFS,
-		.name = "imx-ipuv3-camera",
-	},
-};
-
-static DEFINE_MUTEX(ipu_client_id_mutex);
-static int ipu_client_id;
-
-static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
-{
-	struct device *dev = ipu->dev;
-	unsigned i;
-	int id, ret;
-
-	mutex_lock(&ipu_client_id_mutex);
-	id = ipu_client_id;
-	ipu_client_id += ARRAY_SIZE(client_reg);
-	mutex_unlock(&ipu_client_id_mutex);
-
-	for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
-		const struct ipu_platform_reg *reg = &client_reg[i];
-		struct platform_device *pdev;
-		struct resource res;
-
-		if (reg->reg_offset) {
-			memset(&res, 0, sizeof(res));
-			res.flags = IORESOURCE_MEM;
-			res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
-			res.end = res.start + PAGE_SIZE - 1;
-			pdev = platform_device_register_resndata(dev, reg->name,
-				id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
-		} else {
-			pdev = platform_device_register_data(dev, reg->name,
-				id++, &reg->pdata, sizeof(reg->pdata));
-		}
-
-		if (IS_ERR(pdev)) {
-			ret = PTR_ERR(pdev);
-			goto err_register;
-		}
-	}
-
-	return 0;
-
-err_register:
-	platform_device_unregister_children(to_platform_device(dev));
-
-	return ret;
-}
-
-
 static int ipu_irq_init(struct ipu_soc *ipu)
 {
 	struct irq_chip_generic *gc;
@@ -1318,19 +1214,10 @@ static int ipu_probe(struct platform_device *pdev)
 	if (ret)
 		goto failed_submodules_init;
 
-	ret = ipu_add_client_devices(ipu, ipu_base);
-	if (ret) {
-		dev_err(&pdev->dev, "adding client devices failed with %d\n",
-				ret);
-		goto failed_add_clients;
-	}
-
 	dev_info(&pdev->dev, "%s probed\n", devtype->name);
 
 	return 0;
 
-failed_add_clients:
-	ipu_submodules_exit(ipu);
 failed_submodules_init:
 out_failed_reset:
 	ipu_irq_exit(ipu);
@@ -1343,7 +1230,6 @@ static int ipu_remove(struct platform_device *pdev)
 {
 	struct ipu_soc *ipu = platform_get_drvdata(pdev);
 
-	platform_device_unregister_children(pdev);
 	ipu_submodules_exit(ipu);
 	ipu_irq_exit(ipu);
 
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 7e1bc61..7ff0d99 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -385,13 +385,4 @@ int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 			    bool hflip, bool vflip);
 
-struct ipu_client_platformdata {
-	int csi;
-	int di;
-	int dc;
-	int dp;
-	int dmfc;
-	int dma[2];
-};
-
 #endif /* __DRM_IPU_H__ */
-- 
1.7.9.5

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[PATCH 31/72] gpu: ipu-di: Set rate of DI pre clock

[Steve Longerbeam]

This patch sets the rate of the DI pre clock to support a much wider
range of pixel clock frequencies.

It does this by calculating two values for the pre-clk rate: a
rate that is a whole integer multiple of the pixel clock, and a rate
that is a half-integer multiple. It then programs whichever rate
comes closest to generating the desired pixel clock, and uses the
corresponding integer or half-integer divider.

The reason only whole or half integer DI dividers are used is because
of a chip bug in the fractional part of DI Base Sync Clock Gen 0 register
(see discussion in FSL community site at
https://community.freescale.com/thread/308577).

Quoting from that thread:

"Pixel IPU clock for Display has high jitter and does not have 50% duty cycle.
This is expected behavior, when the clock divider is set to a value that is not
an integer. When the divider is set to a non-integer value, the average
frequency of the clock will be correct, but the clock will jitter."

According to our experimentation, only 0x8 for the fractional part seems
to generate clock waveforms that are tolerated by most displays (this
hasn't been proved officially).

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-di.c |  145 +++++++++++++++++++++++++++++++++----------
 1 file changed, 111 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index b306f07..8da9c9f 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -398,12 +398,105 @@ static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
 		ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
 }
 
-static void ipu_di_config_clock(struct ipu_di *di,
-	const struct ipu_di_signal_cfg *sig)
+
+/*
+ * We need to use the DI divider. We should really have a flag here
+ * indicating whether the bridge can cope with a fractional divider
+ * or not.
+ *
+ * For now, assume the chip bug exists in the fractional divider
+ * which causes bad DI pixel clock waveforms for all values of the
+ * fractional part other than 0 (no fraction) or 0x8 (0.5). So this
+ * function returns a divider with only 0x0 or 0x8 in the fractional
+ * part.
+ *
+ * This function reprograms the clock rate of the parent-parent of
+ * the DI clock in order to get as close as possible to the requested
+ * pixel clock. It calculates two values for the parent-parent rate: a
+ * rate that is a whole integer multiple of the pixel clock, and a rate
+ * that is a half-integer multiple. It then programs whichever rate
+ * comes closest to generating the desired rate, and returns the
+ * corresponding integer or half-integer divider (times 16).
+ */
+static int set_di_pre_clk_rate(struct ipu_di *di,
+			       const struct ipu_di_signal_cfg *sig)
+{
+	struct clk *di_pre_clk;
+	unsigned long pre_clk_N_round, pre_clk_N_0_5_round;
+	unsigned long pre_clk_N, pre_clk_N_0_5;
+	unsigned long pixclk_N, pixclk_N_0_5;
+	unsigned div_N, div_N_0_5, error_N, error_N_0_5;
+	int ret;
+
+	di_pre_clk = clk_get_parent(clk_get_parent(di->clk_di));
+	if (IS_ERR(di_pre_clk)) {
+		dev_err(di->ipu->dev, "failed to get di_pre clock\n");
+		return PTR_ERR(di_pre_clk);
+	}
+
+	/*
+	 * calc pre_clk_N and pre_clk_N_0_5, which are an integer multiple
+	 * and half-integer multiple of sig->pixelclock, respectively.
+	 */
+	pre_clk_N = sig->pixelclock;
+	pre_clk_N_round = clk_round_rate(di_pre_clk, pre_clk_N);
+	pre_clk_N *= (pre_clk_N_round / pre_clk_N);
+	pre_clk_N_0_5 = pre_clk_N + sig->pixelclock / 2;
+
+	if (pre_clk_N < pre_clk_N_round)
+		pre_clk_N += sig->pixelclock;
+	if (pre_clk_N_0_5 < pre_clk_N_round)
+		pre_clk_N_0_5 += sig->pixelclock;
+
+	/*
+	 * now get the rounded pre_clk_N and pre_clk_N_0_5, i.e. what the
+	 * pre-clk can actually generate.
+	 */
+	pre_clk_N_round = clk_round_rate(di_pre_clk, pre_clk_N);
+	pre_clk_N_0_5_round = clk_round_rate(di_pre_clk, pre_clk_N_0_5);
+
+	/*
+	 * finally we can determine whether the integer multiple or
+	 * half-integer multiple pre-clk comes closest to generating
+	 * the desired pixel clock. Set pre-clk rate to whichever comes
+	 * closest.
+	 */
+	div_N = (pre_clk_N_round << 4) / sig->pixelclock;
+	div_N = (div_N + 0x8) & ~0xf; /* round to nearest int */
+	pixclk_N = (pre_clk_N_round << 4) / div_N;
+
+	div_N_0_5 = (pre_clk_N_0_5_round << 4) / sig->pixelclock;
+	div_N_0_5 = (div_N_0_5 + 0x4) & ~0x7; /* round to nearest half-int */
+	pixclk_N_0_5 = (pre_clk_N_0_5_round << 4) / div_N_0_5;
+
+	error_N = pixclk_N / (sig->pixelclock / 1000);
+	error_N_0_5 = pixclk_N_0_5 / (sig->pixelclock / 1000);
+
+	if (abs(error_N - 1000) < abs(error_N_0_5 - 1000)) {
+		ret = div_N;
+		clk_set_rate(di_pre_clk, pre_clk_N_round);
+	} else {
+		ret = div_N_0_5;
+		clk_set_rate(di_pre_clk, pre_clk_N_0_5_round);
+	}
+
+	dev_dbg(di->ipu->dev,
+		"di%d: pixclk want %lu, can do %lu / %lu, div 0x%02x / 0x%02x, error %d.%u%% / %d.%u%%\n",
+		di->id, sig->pixelclock, pixclk_N, pixclk_N_0_5,
+		div_N, div_N_0_5,
+		(signed)(error_N - 1000) / 10, error_N % 10,
+		(signed)(error_N_0_5 - 1000) / 10, error_N_0_5 % 10);
+
+	return ret;
+}
+
+static int ipu_di_config_clock(struct ipu_di *di,
+			       const struct ipu_di_signal_cfg *sig)
 {
 	struct clk *clk;
 	unsigned clkgen0;
 	uint32_t val;
+	int ret;
 
 	if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
 		/*
@@ -423,24 +516,10 @@ static void ipu_di_config_clock(struct ipu_di *di,
 			 */
 			clkgen0 = 1 << 4;
 		} else {
-			/*
-			 * We can use the divider.  We should really have
-			 * a flag here indicating whether the bridge can
-			 * cope with a fractional divider or not.  For the
-			 * time being, let's go for simplicitly and
-			 * reliability.
-			 */
-			unsigned long in_rate;
-			unsigned div;
-
-			clk_set_rate(clk, sig->pixelclock);
-
-			in_rate = clk_get_rate(clk);
-			div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
-			if (div == 0)
-				div = 1;
-
-			clkgen0 = div << 4;
+			ret = set_di_pre_clk_rate(di, sig);
+			if (ret < 0)
+				return ret;
+			clkgen0 = ret;
 		}
 	} else {
 		/*
@@ -470,19 +549,12 @@ static void ipu_di_config_clock(struct ipu_di *di,
 
 			clkgen0 = div << 4;
 		} else {
-			unsigned long in_rate;
-			unsigned div;
-
 			clk = di->clk_di;
 
-			clk_set_rate(clk, sig->pixelclock);
-
-			in_rate = clk_get_rate(clk);
-			div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
-			if (div == 0)
-				div = 1;
-
-			clkgen0 = div << 4;
+			ret = set_di_pre_clk_rate(di, sig);
+			if (ret < 0)
+				return ret;
+			clkgen0 = ret;
 		}
 	}
 
@@ -513,6 +585,8 @@ static void ipu_di_config_clock(struct ipu_di *di,
 		clk_get_rate(di->clk_di),
 		clk == di->clk_di ? "DI" : "IPU",
 		clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
+
+	return 0;
 }
 
 /*
@@ -546,6 +620,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 	u32 reg;
 	u32 di_gen, vsync_cnt;
 	u32 div;
+	int ret = 0;
 
 	dev_dbg(di->ipu->dev, "di%d: panel size = %d x %d\n",
 		di->id, sig->width, sig->height);
@@ -564,7 +639,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 	mutex_lock(&di_mutex);
 
-	ipu_di_config_clock(di, sig);
+	ret = ipu_di_config_clock(di, sig);
+	if (ret)
+		goto unlock;
 
 	div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
 	div = div / 16;		/* Now divider is integer portion */
@@ -641,9 +718,9 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
 
 	ipu_di_write(di, reg, DI_POL);
 
+unlock:
 	mutex_unlock(&di_mutex);
-
-	return 0;
+	return ret;
 }
 EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
 
-- 
1.7.9.5

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[PATCH 32/72] gpu: ipu-v3: Add RGB666 interface pixel map

[Steve Longerbeam]

Adds RGB666 to the pre-loaded interface pixel maps.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-dc.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 23b6e2c..955adab 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -102,6 +102,10 @@ static struct ipu_dc_if_map predef_maps[] = {
 		.v4l2_fmt = v4l2_fourcc('G', 'B', 'R', '3'),
 	}, {
 		.src_mask = {0xfc, 0xfc, 0xfc},
+		.dest_msb = {5, 11, 17},
+		.v4l2_fmt = v4l2_fourcc('R', 'G', 'B', 'H'),
+	}, {
+		.src_mask = {0xfc, 0xfc, 0xfc},
 		.dest_msb = {17, 11, 5},
 		.v4l2_fmt = V4L2_PIX_FMT_BGR666,
 	}, {
-- 
1.7.9.5

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[PATCH 33/72] gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*

[Steve Longerbeam]

Pass a drm pixel format fourcc to ipu_cpmem_set_yuv_interleaved(),
ipu_cpmem_set_yuv_planar_full(), and ipu_cpmem_set_yuv_planar(),
instead of a v4l2 pixel format. The remaining cpmem API that still
accepts a v4l2 format is now only ipu_cpmem_set_image(), since this
function is called by v4l2 drivers.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-cpmem.c |   83 +++++++++++++++++++++-------------------
 include/video/imx-ipu-v3.h     |    6 +--
 2 files changed, 46 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 2c93e9c..a53b242 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -384,15 +384,15 @@ int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
 
-void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
+void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 drm_fourcc)
 {
-	switch (pixel_format) {
-	case V4L2_PIX_FMT_UYVY:
+	switch (drm_fourcc) {
+	case DRM_FORMAT_UYVY:
 		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
 		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
 		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
 		break;
-	case V4L2_PIX_FMT_YUYV:
+	case DRM_FORMAT_YUYV:
 		ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
 		ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
 		ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
@@ -402,23 +402,23 @@ void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
 
 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
-				   u32 pixel_format, int stride,
+				   u32 drm_fourcc, int stride,
 				   int u_offset, int v_offset)
 {
-	switch (pixel_format) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YUV422P:
+	switch (drm_fourcc) {
+	case DRM_FORMAT_YUV420:
+	case DRM_FORMAT_YUV422:
 		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
 		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
 		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
 		break;
-	case V4L2_PIX_FMT_YVU420:
+	case DRM_FORMAT_YVU420:
 		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
 		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
 		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
 		break;
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_NV16:
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV16:
 		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1);
 		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
 		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
@@ -427,32 +427,32 @@ void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
 
-void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
-			      u32 pixel_format, int stride, int height)
+void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, u32 drm_fourcc,
+			      int stride, int height)
 {
 	int u_offset, v_offset;
 	int uv_stride = 0;
 
-	switch (pixel_format) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YVU420:
+	switch (drm_fourcc) {
+	case DRM_FORMAT_YUV420:
+	case DRM_FORMAT_YVU420:
 		uv_stride = stride / 2;
 		u_offset = stride * height;
 		v_offset = u_offset + (uv_stride * height / 2);
-		ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc, stride,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_YUV422P:
+	case DRM_FORMAT_YUV422:
 		uv_stride = stride / 2;
 		u_offset = stride * height;
 		v_offset = u_offset + (uv_stride * height);
-		ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc, stride,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_NV16:
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV16:
 		u_offset = stride * height;
-		ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc, stride,
 					      u_offset, 0);
 		break;
 	}
@@ -600,73 +600,76 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
 {
 	struct v4l2_pix_format *pix = &image->pix;
 	int offset, u_offset, v_offset;
+	u32 drm_fourcc;
 
 	pr_debug("%s: resolution: %dx%d stride: %d\n",
 		 __func__, pix->width, pix->height,
 		 pix->bytesperline);
 
+	drm_fourcc = v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat);
+
 	ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
 	ipu_cpmem_set_stride(ch, pix->bytesperline);
 
-	ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
+	ipu_cpmem_set_fmt(ch, drm_fourcc);
 
-	switch (pix->pixelformat) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YVU420:
+	switch (drm_fourcc) {
+	case DRM_FORMAT_YUV420:
+	case DRM_FORMAT_YVU420:
 		offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 		u_offset = U_OFFSET(pix, image->rect.left,
 				    image->rect.top) - offset;
 		v_offset = V_OFFSET(pix, image->rect.left,
 				    image->rect.top) - offset;
 
-		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc,
 					      pix->bytesperline,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_YUV422P:
+	case DRM_FORMAT_YUV422:
 		offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 		u_offset = U2_OFFSET(pix, image->rect.left,
 				     image->rect.top) - offset;
 		v_offset = V2_OFFSET(pix, image->rect.left,
 				     image->rect.top) - offset;
 
-		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc,
 					      pix->bytesperline,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_NV12:
+	case DRM_FORMAT_NV12:
 		offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 		u_offset = UV_OFFSET(pix, image->rect.left,
 				     image->rect.top) - offset;
 		v_offset = 0;
 
-		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc,
 					      pix->bytesperline,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_NV16:
+	case DRM_FORMAT_NV16:
 		offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 		u_offset = UV2_OFFSET(pix, image->rect.left,
 				      image->rect.top) - offset;
 		v_offset = 0;
 
-		ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat,
+		ipu_cpmem_set_yuv_planar_full(ch, drm_fourcc,
 					      pix->bytesperline,
 					      u_offset, v_offset);
 		break;
-	case V4L2_PIX_FMT_UYVY:
-	case V4L2_PIX_FMT_YUYV:
-	case V4L2_PIX_FMT_RGB565:
+	case DRM_FORMAT_UYVY:
+	case DRM_FORMAT_YUYV:
+	case DRM_FORMAT_RGB565:
 		offset = image->rect.left * 2 +
 			image->rect.top * pix->bytesperline;
 		break;
-	case V4L2_PIX_FMT_RGB32:
-	case V4L2_PIX_FMT_BGR32:
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_XRGB8888:
 		offset = image->rect.left * 4 +
 			image->rect.top * pix->bytesperline;
 		break;
-	case V4L2_PIX_FMT_RGB24:
-	case V4L2_PIX_FMT_BGR24:
+	case DRM_FORMAT_BGR888:
+	case DRM_FORMAT_RGB888:
 		offset = image->rect.left * 3 +
 			image->rect.top * pix->bytesperline;
 		break;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 7ff0d99..5aaa08d 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -205,12 +205,12 @@ void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
 			     const struct ipu_rgb *rgb);
 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
-void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
+void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 drm_fourcc);
 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
-				   u32 pixel_format, int stride,
+				   u32 drm_fourcc, int stride,
 				   int u_offset, int v_offset);
 void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
-			      u32 pixel_format, int stride, int height);
+			      u32 drm_fourcc, int stride, int height);
 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
 void ipu_cpmem_dump(struct ipuv3_channel *ch);
-- 
1.7.9.5

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[PATCH 34/72] gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()

[Steve Longerbeam]

Adds ipu_drm_fourcc_is_planar(), which is equivalent to
ipu_pixelformat_is_planar() but accepts a drm fourcc format.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |   18 ++++++++++++++++++
 include/video/imx-ipu-v3.h      |    1 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index ebafcf2..b1f0feb 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -153,6 +153,24 @@ bool ipu_pixelformat_is_planar(u32 pixelformat)
 }
 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 
+bool ipu_drm_fourcc_is_planar(u32 drm_fourcc)
+{
+	switch (drm_fourcc) {
+	case DRM_FORMAT_YUV420:
+	case DRM_FORMAT_YVU420:
+	case DRM_FORMAT_YUV422:
+	case DRM_FORMAT_YVU422:
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV21:
+	case DRM_FORMAT_NV16:
+	case DRM_FORMAT_NV61:
+		return true;
+	}
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(ipu_drm_fourcc_is_planar);
+
 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 {
 	switch (mbus_code & 0xf000) {
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 5aaa08d..f48ded6 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -380,6 +380,7 @@ enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
 bool ipu_pixelformat_is_planar(u32 pixelformat);
+bool ipu_drm_fourcc_is_planar(u32 drm_fourcc);
 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 			    bool hflip, bool vflip);
 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
-- 
1.7.9.5

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[PATCH 35/72] gpu: ipu-v3: Add IDMA channel linking support

[Steve Longerbeam]

Adds functions to link and unlink IDMAC source channels to sink
channels.

So far the following links are supported:

IPUV3_CHANNEL_IC_PRP_ENC_MEM -> IPUV3_CHANNEL_MEM_ROT_ENC
PUV3_CHANNEL_IC_PRP_VF_MEM   -> IPUV3_CHANNEL_MEM_ROT_VF
IPUV3_CHANNEL_IC_PP_MEM      -> IPUV3_CHANNEL_MEM_ROT_PP

More links can be added to the idmac_link_info[] array.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-common.c |  112 +++++++++++++++++++++++++++++++++++++++
 include/video/imx-ipu-v3.h      |    3 ++
 2 files changed, 115 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index b1f0feb..ce1de54 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -755,6 +755,118 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 }
 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 
+
+/* IDMAC Channel Linking */
+
+struct idmac_link_reg_info {
+	int chno;
+	u32 reg;
+	int shift;
+	int bits;
+	u32 sel;
+};
+
+struct idmac_link_info {
+	struct idmac_link_reg_info src;
+	struct idmac_link_reg_info sink;
+};
+
+static const struct idmac_link_info idmac_link_info[] = {
+	{
+		.src  = { 20, IPU_FS_PROC_FLOW1,  0, 4, 7 },
+		.sink = { 45, IPU_FS_PROC_FLOW2,  0, 4, 1 },
+	}, {
+		.src =  { 21, IPU_FS_PROC_FLOW1,  8, 4, 8 },
+		.sink = { 46, IPU_FS_PROC_FLOW2,  4, 4, 1 },
+	}, {
+		.src =  { 22, IPU_FS_PROC_FLOW1, 16, 4, 5 },
+		.sink = { 47, IPU_FS_PROC_FLOW2, 12, 4, 3 },
+	},
+};
+
+static const struct idmac_link_info *find_idmac_link_info(
+	struct ipuv3_channel *src, struct ipuv3_channel *sink)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(idmac_link_info); i++) {
+		if (src->num == idmac_link_info[i].src.chno &&
+		    sink->num == idmac_link_info[i].sink.chno)
+			return &idmac_link_info[i];
+	}
+
+	return NULL;
+}
+
+/*
+ * Links an IDMAC source channel to a sink channel.
+ */
+int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
+{
+	struct ipu_soc *ipu = src->ipu;
+	const struct idmac_link_info *link;
+	u32 src_reg, sink_reg, src_mask, sink_mask;
+	unsigned long flags;
+
+	link = find_idmac_link_info(src, sink);
+	if (!link)
+		return -EINVAL;
+
+	src_mask = ((1 << link->src.bits) - 1) << link->src.shift;
+	sink_mask = ((1 << link->sink.bits) - 1) << link->sink.shift;
+
+	spin_lock_irqsave(&ipu->lock, flags);
+
+	src_reg = ipu_cm_read(ipu, link->src.reg);
+	sink_reg = ipu_cm_read(ipu, link->sink.reg);
+
+	src_reg &= ~src_mask;
+	src_reg |= (link->src.sel << link->src.shift);
+
+	sink_reg &= ~sink_mask;
+	sink_reg |= (link->sink.sel << link->sink.shift);
+
+	ipu_cm_write(ipu, src_reg, link->src.reg);
+	ipu_cm_write(ipu, sink_reg, link->sink.reg);
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ipu_idmac_link);
+
+/*
+ * Unlinks IDMAC source and sink channels.
+ */
+int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
+{
+	struct ipu_soc *ipu = src->ipu;
+	const struct idmac_link_info *link;
+	u32 src_reg, sink_reg, src_mask, sink_mask;
+	unsigned long flags;
+
+	link = find_idmac_link_info(src, sink);
+	if (!link)
+		return -EINVAL;
+
+	src_mask = ((1 << link->src.bits) - 1) << link->src.shift;
+	sink_mask = ((1 << link->sink.bits) - 1) << link->sink.shift;
+
+	spin_lock_irqsave(&ipu->lock, flags);
+
+	src_reg = ipu_cm_read(ipu, link->src.reg);
+	sink_reg = ipu_cm_read(ipu, link->sink.reg);
+
+	src_reg &= ~src_mask;
+	sink_reg &= ~sink_mask;
+
+	ipu_cm_write(ipu, src_reg, link->src.reg);
+	ipu_cm_write(ipu, sink_reg, link->sink.reg);
+
+	spin_unlock_irqrestore(&ipu->lock, flags);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
+
 struct ipu_devtype {
 	const char *name;
 	unsigned long cm_ofs;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index f48ded6..df4cc5d 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -129,6 +129,7 @@ enum ipu_channel_irq {
 #define IPUV3_CHANNEL_ROT_VF_MEM		49
 #define IPUV3_CHANNEL_ROT_PP_MEM		50
 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA		51
+#define IPUV3_NUM_CHANNELS			64
 
 int ipu_map_irq(struct ipu_soc *ipu, int irq);
 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
@@ -171,6 +172,8 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
+int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
+int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
 
 /*
  * IPU Channel Parameter Memory (cpmem) functions
-- 
1.7.9.5

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[PATCH 36/72] gpu: ipu-cpmem: Support YVU422

[Steve Longerbeam]

Add simple hooks to support YVU422 in cpmem.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-cpmem.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index a53b242..b05a5e8 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -413,6 +413,7 @@ void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
 		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
 		break;
 	case DRM_FORMAT_YVU420:
+	case DRM_FORMAT_YVU422:
 		ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
 		ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
 		ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
@@ -443,6 +444,7 @@ void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, u32 drm_fourcc,
 					      u_offset, v_offset);
 		break;
 	case DRM_FORMAT_YUV422:
+	case DRM_FORMAT_YVU422:
 		uv_stride = stride / 2;
 		u_offset = stride * height;
 		v_offset = u_offset + (uv_stride * height);
@@ -627,6 +629,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
 					      u_offset, v_offset);
 		break;
 	case DRM_FORMAT_YUV422:
+	case DRM_FORMAT_YVU422:
 		offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 		u_offset = U2_OFFSET(pix, image->rect.left,
 				     image->rect.top) - offset;
-- 
1.7.9.5

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[PATCH 37/72] gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()

[Steve Longerbeam]

Adds ipu_cpmem_get_burstsize().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/ipu-v3/ipu-cpmem.c |    6 ++++++
 include/video/imx-ipu-v3.h     |    1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index b05a5e8..7afea0a 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -275,6 +275,12 @@ void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
 
+int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch)
+{
+	return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1;
+}
+EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize);
+
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
 {
 	ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index df4cc5d..3c7f6f3 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -201,6 +201,7 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
+int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
-- 
1.7.9.5

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[PATCH 38/72] imx-drm: Crtcs moved to device tree

[Steve Longerbeam]

The crtcs are now nodes in the device tree, and the encoder endpoints
fall under the crtc port.

ipu_client_platformdata is no longer needed and is gone. The crtc
retrieves the following required parameters from its node:

- ipu phandle.
- di number.
- the port endpoints.

Optionally, "dual-plane" can be specified to configure the crtc device
with a foreground plane. If not given, the crtc will have only a
single plane.

The DC and IDMAC channels can be inferred from the dual-plane parameter.
In table form, the channel usage is:

                 Background Plane   Foreground Plane     Single Plane
                 ----------------   ----------------     ------------
    Flow Type    IDMAC   DC   DP     IDMAC   DP           IDMAC   DC
    ---------    -----  ---  ---     -----  ---           -----  ---
    Sync          23     5    0       27     1             28     1
    Async         24     6    2       29     3             41     2

Async flows are included in the above table but async displays are
not yet supported by the crtc and plane drivers.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |   28 +++--
 drivers/staging/imx-drm/ipuv3-crtc.c   |  204 +++++++++++++++++++++++---------
 2 files changed, 162 insertions(+), 70 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 9cb222e..e5ec010 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -591,37 +591,43 @@ static const struct component_master_ops imx_drm_ops = {
 
 static int imx_drm_platform_probe(struct platform_device *pdev)
 {
-	struct device_node *ep, *port, *remote;
+	struct device_node *ep, *crtc, *port, *remote;
 	struct component_match *match = NULL;
 	int ret;
 	int i;
 
 	/*
-	 * Bind the IPU display interface ports first, so that
-	 * imx_drm_encoder_parse_of called from encoder .bind callbacks
-	 * works as expected.
+	 * Bind the crtcs first, so that imx_drm_encoder_parse_of called
+	 * from encoder .bind callbacks works as expected.
 	 */
 	for (i = 0; ; i++) {
-		port = of_parse_phandle(pdev->dev.of_node, "ports", i);
-		if (!port)
+		crtc = of_parse_phandle(pdev->dev.of_node, "crtcs", i);
+		if (!crtc)
 			break;
 
-		component_match_add(&pdev->dev, &match, compare_of, port);
+		component_match_add(&pdev->dev, &match, compare_of, crtc);
 	}
 
 	if (i == 0) {
-		dev_err(&pdev->dev, "missing 'ports' property\n");
+		dev_err(&pdev->dev, "missing 'crtcs' property\n");
 		return -ENODEV;
 	}
 
 	/* Then bind all encoders */
 	for (i = 0; ; i++) {
-		port = of_parse_phandle(pdev->dev.of_node, "ports", i);
-		if (!port)
+		crtc = of_parse_phandle(pdev->dev.of_node, "crtcs", i);
+		if (!crtc)
 			break;
 
+		port = of_get_child_by_name(crtc, "port");
+		if (!port) {
+			dev_warn(&pdev->dev, "%s has no port\n", crtc->name);
+			continue;
+		}
+
 		for_each_child_of_node(port, ep) {
 			remote = of_graph_get_remote_port_parent(ep);
+
 			if (!remote || !of_device_is_available(remote)) {
 				of_node_put(remote);
 				continue;
@@ -635,7 +641,7 @@ static int imx_drm_platform_probe(struct platform_device *pdev)
 			component_match_add(&pdev->dev, &match, compare_of, remote);
 			of_node_put(remote);
 		}
-		of_node_put(port);
+		of_node_put(crtc);
 	}
 
 	ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 8b4440a..5a60017 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -36,10 +36,52 @@
 
 #define DRIVER_DESC		"i.MX IPUv3 Graphics"
 
+struct ipu_channels {
+	int dma[2]; /* BG, FG */
+	int dp[2];  /* BG, FG */
+	int dc;
+};
+
+#define NO_DP -1
+
+static const struct ipu_channels sync_dual_plane = {
+	.dma = { IPUV3_CHANNEL_MEM_BG_SYNC, IPUV3_CHANNEL_MEM_FG_SYNC },
+	.dp  = { IPU_DP_FLOW_SYNC_BG, IPU_DP_FLOW_SYNC_FG },
+	.dc  = IPU_DC_CHANNEL_DP_SYNC,
+};
+static const struct ipu_channels sync_single_plane = {
+	.dma = { IPUV3_CHANNEL_MEM_DC_SYNC, },
+	.dp  = { NO_DP, NO_DP },
+	.dc  = IPU_DC_CHANNEL_SYNC,
+};
+
+/*
+ * This driver does not yet support async flows for "smart" displays,
+ * but keep this around for future reference. The crtc nodes could in
+ * future add an "async" property.
+ */
+#if 0
+static const struct ipu_channels async_dual_plane = {
+	.dma = { IPUV3_CHANNEL_MEM_BG_ASYNC, IPUV3_CHANNEL_MEM_FG_ASYNC },
+	.dp  = { IPU_DP_FLOW_ASYNC0_BG, IPU_DP_FLOW_ASYNC0_FG },
+	.dc  = IPU_DC_CHANNEL_DP_ASYNC,
+};
+static const struct ipu_channels async_single_plane = {
+	.dma = { IPUV3_CHANNEL_MEM_DC_ASYNC, },
+	.dp  = { NO_DP, NO_DP },
+	.dc    = IPU_DC_CHANNEL_ASYNC,
+};
+#endif
+
 struct ipu_crtc {
 	struct device		*dev;
 	struct drm_crtc		base;
 	struct imx_drm_crtc	*imx_crtc;
+	struct device           *ipu_dev; /* our ipu */
+	struct ipu_soc          *ipu;
+	struct device_node      *port;    /* our port */
+
+	const struct ipu_channels *ch;
 
 	/* plane[0] is the full plane, plane[1] is the partial plane */
 	struct ipu_plane	*plane[2];
@@ -311,32 +353,106 @@ static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
 	.crtc_helper_funcs = &ipu_helper_funcs,
 };
 
+static int of_dev_node_match(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static int get_ipu(struct ipu_crtc *ipu_crtc, struct device_node *node)
+{
+	struct device_node *ipu_node;
+	struct device *ipu_dev;
+	int ret;
+
+	ipu_node = of_parse_phandle(node, "ipu", 0);
+	if (!ipu_node) {
+		dev_err(ipu_crtc->dev, "missing ipu phandle!\n");
+		return -ENODEV;
+	}
+
+	ipu_dev = bus_find_device(&platform_bus_type, NULL,
+				  ipu_node, of_dev_node_match);
+	of_node_put(ipu_node);
+
+	if (!ipu_dev) {
+		dev_err(ipu_crtc->dev, "failed to find ipu device!\n");
+		return -ENODEV;
+	}
+
+	device_lock(ipu_dev);
+
+	if (!ipu_dev->driver || !try_module_get(ipu_dev->driver->owner)) {
+		ret = -EPROBE_DEFER;
+		dev_warn(ipu_crtc->dev, "IPU driver not loaded\n");
+		device_unlock(ipu_dev);
+		goto dev_put;
+	}
+
+	ipu_crtc->ipu_dev = ipu_dev;
+	ipu_crtc->ipu = dev_get_drvdata(ipu_dev);
+
+	device_unlock(ipu_dev);
+	return 0;
+dev_put:
+	put_device(ipu_dev);
+	return ret;
+}
+
 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
 {
 	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
 		ipu_dc_put(ipu_crtc->dc);
 	if (!IS_ERR_OR_NULL(ipu_crtc->di))
 		ipu_di_put(ipu_crtc->di);
+	if (!IS_ERR_OR_NULL(ipu_crtc->ipu_dev)) {
+		module_put(ipu_crtc->ipu_dev->driver->owner);
+		put_device(ipu_crtc->ipu_dev);
+	}
 }
 
 static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
-		struct ipu_client_platformdata *pdata)
+			     struct device_node *np)
 {
-	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
+	u32 di;
 	int ret;
 
-	ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
-	if (IS_ERR(ipu_crtc->dc)) {
-		ret = PTR_ERR(ipu_crtc->dc);
-		goto err_out;
+	ret = get_ipu(ipu_crtc, np);
+	if (ret) {
+		dev_warn(ipu_crtc->dev, "could not get ipu\n");
+		return ret;
+	}
+
+	/* get our port */
+	ipu_crtc->port = of_get_child_by_name(np, "port");
+	if (!ipu_crtc->port) {
+		dev_err(ipu_crtc->dev, "could not get port\n");
+		return -ENODEV;
 	}
 
-	ipu_crtc->di = ipu_di_get(ipu, pdata->di);
+	ret = of_property_read_u32(np, "di", &di);
+	if (ret < 0)
+		goto err_out;
+
+	ipu_crtc->di = ipu_di_get(ipu_crtc->ipu, di);
 	if (IS_ERR(ipu_crtc->di)) {
 		ret = PTR_ERR(ipu_crtc->di);
 		goto err_out;
 	}
 
+	if (!of_find_property(np, "dual-plane", NULL)) {
+		dev_info(ipu_crtc->dev, "single plane mode\n");
+		ipu_crtc->ch = &sync_single_plane;
+	} else {
+		dev_info(ipu_crtc->dev, "dual plane mode\n");
+		ipu_crtc->ch = &sync_dual_plane;
+	}
+
+	ipu_crtc->dc = ipu_dc_get(ipu_crtc->ipu, ipu_crtc->ch->dc);
+	if (IS_ERR(ipu_crtc->dc)) {
+		ret = PTR_ERR(ipu_crtc->dc);
+		goto err_out;
+	}
+
 	return 0;
 err_out:
 	ipu_put_resources(ipu_crtc);
@@ -345,14 +461,13 @@ err_out:
 }
 
 static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
-	struct ipu_client_platformdata *pdata, struct drm_device *drm)
+			 struct drm_device *drm)
 {
-	struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
-	int dp = -EINVAL;
+	struct device_node *np = ipu_crtc->dev->of_node;
 	int ret;
 	int id;
 
-	ret = ipu_get_resources(ipu_crtc, pdata);
+	ret = ipu_get_resources(ipu_crtc, np);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
 				ret);
@@ -360,17 +475,18 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 	}
 
 	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
-			&ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
+			       &ipu_crtc_helper_funcs, ipu_crtc->port);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
 		goto err_put_resources;
 	}
 
-	if (pdata->dp >= 0)
-		dp = IPU_DP_FLOW_SYNC_BG;
 	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
-	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
-					    pdata->dma[0], dp, BIT(id), true);
+	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev,
+					    ipu_crtc->ipu,
+					    ipu_crtc->ch->dma[0],
+					    ipu_crtc->ch->dp[0],
+					    BIT(id), true);
 	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
@@ -379,10 +495,11 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 	}
 
 	/* If this crtc is using the DP, add an overlay plane */
-	if (pdata->dp >= 0 && pdata->dma[1] > 0) {
-		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
-						    pdata->dma[1],
-						    IPU_DP_FLOW_SYNC_FG,
+	if (ipu_crtc->ch->dp[1] >= 0) {
+		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev,
+						    ipu_crtc->ipu,
+						    ipu_crtc->ch->dma[1],
+						    ipu_crtc->ch->dp[1],
 						    BIT(id), false);
 		if (IS_ERR(ipu_crtc->plane[1]))
 			ipu_crtc->plane[1] = NULL;
@@ -408,31 +525,8 @@ err_put_resources:
 	return ret;
 }
 
-static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent,
-						  int port_id)
-{
-	struct device_node *port;
-	int id, ret;
-
-	port = of_get_child_by_name(parent, "port");
-	while (port) {
-		ret = of_property_read_u32(port, "reg", &id);
-		if (!ret && id == port_id)
-			return port;
-
-		do {
-			port = of_get_next_child(parent, port);
-			if (!port)
-				return NULL;
-		} while (of_node_cmp(port->name, "port"));
-	}
-
-	return NULL;
-}
-
 static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
 {
-	struct ipu_client_platformdata *pdata = dev->platform_data;
 	struct drm_device *drm = data;
 	struct ipu_crtc *ipu_crtc;
 	int ret;
@@ -443,7 +537,7 @@ static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
 
 	ipu_crtc->dev = dev;
 
-	ret = ipu_crtc_init(ipu_crtc, pdata, drm);
+	ret = ipu_crtc_init(ipu_crtc, drm);
 	if (ret)
 		return ret;
 
@@ -471,23 +565,8 @@ static const struct component_ops ipu_crtc_ops = {
 static int ipu_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct ipu_client_platformdata *pdata = dev->platform_data;
 	int ret;
 
-	if (!dev->platform_data)
-		return -EINVAL;
-
-	if (!dev->of_node) {
-		/* Associate crtc device with the corresponding DI port node */
-		dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
-						      pdata->di + 2);
-		if (!dev->of_node) {
-			dev_err(dev, "missing port@%d node in %s\n",
-				pdata->di + 2, dev->parent->of_node->full_name);
-			return -ENODEV;
-		}
-	}
-
 	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
 	if (ret)
 		return ret;
@@ -501,9 +580,16 @@ static int ipu_drm_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static struct of_device_id ipu_drm_dt_ids[] = {
+	{ .compatible = "fsl,imx-ipuv3-crtc" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ipu_drm_dt_ids);
+
 static struct platform_driver ipu_drm_driver = {
 	.driver = {
 		.name = "imx-ipuv3-crtc",
+		.of_match_table = ipu_drm_dt_ids,
 	},
 	.probe = ipu_drm_probe,
 	.remove = ipu_drm_remove,
-- 
1.7.9.5

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[PATCH 39/72] imx-drm: hdmi: optimize i2c write wait

[Steve Longerbeam]

A wait of around 50 ~ 100 micro seconds seems to be enough to allow
I2C Master PHY done, so instead of wait 1000 usec at each time
of register check, wait 100 usec is more appropriate.

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-hdmi.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index aaec6b2..801a3eb 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -655,12 +655,12 @@ static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
 	hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 }
 
-static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
+static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int husec)
 {
 	while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
-		if (msec-- == 0)
+		if (husec-- == 0)
 			return false;
-		udelay(1000);
+		udelay(100);
 	}
 	return true;
 }
-- 
1.7.9.5

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[PATCH 40/72] imx-drm: parallel-display: Support RGB666 pixel fmt

[Steve Longerbeam]

Add a clause to imx-pd driver to use 18-bit output if driver is told so.

Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/parallel-display.c |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index 015a454..5f7d4ee 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -230,6 +230,13 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 		else if (!strcmp(fmt, "lvds666"))
 			imxpd->interface_pix_fmt =
 					v4l2_fourcc('L', 'V', 'D', '6');
+		else if (!strcmp(fmt, "rgb18"))
+			imxpd->interface_pix_fmt =
+					v4l2_fourcc('R', 'G', 'B', 'H');
+		else {
+			dev_err(dev, "Unsupported interface pix_fmt!\n");
+			return -EINVAL;
+		}
 	}
 
 	panel_node = of_parse_phandle(np, "fsl,panel", 0);
-- 
1.7.9.5

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[PATCH 41/72] imx-drm: imx-ldb: Add debug to connector/encoder entry points

[Steve Longerbeam]

Add some debug macros for the important encoder and connector
callbacks.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-ldb.c |   36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 4662e00..73ff379 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -85,6 +85,11 @@ struct imx_ldb {
 	const struct bus_mux *lvds_mux;
 };
 
+#define imx_ldb_dbg(ch, fmt, args...)					\
+	dev_dbg((ch)->ldb->dev, "lvds%d: " fmt, (ch)->chno, ##args)
+#define imx_ldb_entry_dbg(ch)			\
+	imx_ldb_dbg((ch), "%s\n", __func__)
+
 static enum drm_connector_status imx_ldb_connector_detect(
 		struct drm_connector *connector, bool force)
 {
@@ -96,6 +101,8 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
 	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
 	int num_modes = 0;
 
+	imx_ldb_entry_dbg(imx_ldb_ch);
+
 	if (imx_ldb_ch->edid) {
 		drm_mode_connector_update_edid_property(connector,
 							imx_ldb_ch->edid);
@@ -127,6 +134,9 @@ static struct drm_encoder *imx_ldb_connector_best_encoder(
 
 static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
 {
+	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+
+	imx_ldb_dbg(imx_ldb_ch, "%s: %s\n", __func__, mode ? "OFF" : "ON");
 }
 
 static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
@@ -139,22 +149,22 @@ static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
 		unsigned long serial_clk, unsigned long di_clk)
 {
+	struct imx_ldb_channel *imx_ldb_ch = &ldb->channel[chno];
 	int ret;
 
-	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
-			clk_get_rate(ldb->clk_pll[chno]), serial_clk);
+	imx_ldb_dbg(imx_ldb_ch, "%s: now: %ld want: %ld\n", __func__,
+		    clk_get_rate(ldb->clk_pll[chno]), serial_clk);
 	clk_set_rate(ldb->clk_pll[chno], serial_clk);
 
-	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
-			clk_get_rate(ldb->clk_pll[chno]));
+	imx_ldb_dbg(imx_ldb_ch, "%s after: %ld\n", __func__,
+		    clk_get_rate(ldb->clk_pll[chno]));
 
-	dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
-			clk_get_rate(ldb->clk[chno]),
-			(long int)di_clk);
+	imx_ldb_dbg(imx_ldb_ch, "%s: now: %ld want: %ld\n", __func__,
+		    clk_get_rate(ldb->clk[chno]), (long int)di_clk);
 	clk_set_rate(ldb->clk[chno], di_clk);
 
-	dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
-			clk_get_rate(ldb->clk[chno]));
+	imx_ldb_dbg(imx_ldb_ch, "%s after: %ld\n", __func__,
+		    clk_get_rate(ldb->clk[chno]));
 
 	/* set display clock mux to LDB input clock */
 	ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
@@ -174,6 +184,8 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
 	unsigned long di_clk = mode->clock * 1000;
 	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
 
+	imx_ldb_entry_dbg(imx_ldb_ch);
+
 	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 		/* dual channel LVDS mode */
 		serial_clk = 3500UL * mode->clock;
@@ -210,6 +222,8 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
 	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
 
+	imx_ldb_entry_dbg(imx_ldb_ch);
+
 	if (dual) {
 		clk_prepare_enable(ldb->clk[0]);
 		clk_prepare_enable(ldb->clk[1]);
@@ -253,6 +267,8 @@ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
 	struct imx_ldb *ldb = imx_ldb_ch->ldb;
 	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
 
+	imx_ldb_entry_dbg(imx_ldb_ch);
+
 	if (mode->clock > 170000) {
 		dev_warn(ldb->dev,
 			 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
@@ -282,6 +298,8 @@ static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
 	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 	struct imx_ldb *ldb = imx_ldb_ch->ldb;
 
+	imx_ldb_entry_dbg(imx_ldb_ch);
+
 	/*
 	 * imx_ldb_encoder_disable is called by
 	 * drm_helper_disable_unused_functions without
-- 
1.7.9.5

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[PATCH 42/72] imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()

[Steve Longerbeam]

Implement imx_ldb_encoder_dpms(). Two new functions are created
to share poweroff and poweron code. imx_ldb_poweroff() is called
by encoder dpms, prepare, and disable. imx_ldb_poweron() is called
by encoder dpms and commit.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-ldb.c |  139 +++++++++++++++++++++----------------
 1 file changed, 79 insertions(+), 60 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 73ff379..1eb632f 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -132,11 +132,86 @@ static struct drm_encoder *imx_ldb_connector_best_encoder(
 	return &imx_ldb_ch->encoder;
 }
 
+static void imx_ldb_poweroff(struct imx_ldb_channel *imx_ldb_ch)
+{
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+	int chno = imx_ldb_ch->chno;
+
+	if ((chno == 0 && (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) ||
+	    (chno == 1 && (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0))
+		return;
+
+	ldb->ldb_ctrl &= (chno == 0) ?
+		~LDB_CH0_MODE_EN_MASK : ~LDB_CH1_MODE_EN_MASK;
+
+	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+
+	if (dual) {
+		clk_disable_unprepare(ldb->clk[0]);
+		clk_disable_unprepare(ldb->clk[1]);
+	} else
+		clk_disable_unprepare(ldb->clk[chno]);
+}
+
+static void imx_ldb_poweron(struct imx_ldb_channel *imx_ldb_ch)
+{
+	struct imx_ldb *ldb = imx_ldb_ch->ldb;
+	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+	int chno = imx_ldb_ch->chno;
+	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child,
+					     &imx_ldb_ch->encoder);
+
+	if ((chno == 0 && (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK)) ||
+	    (chno == 1 && (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK)))
+		return;
+
+	if (dual) {
+		clk_prepare_enable(ldb->clk[0]);
+		clk_prepare_enable(ldb->clk[1]);
+	} else
+		clk_prepare_enable(ldb->clk[chno]);
+
+	if (chno == 0 || dual) {
+		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+		if (mux == 0 || ldb->lvds_mux)
+			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+		else if (mux == 1)
+			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
+	}
+	if (chno == 1 || dual) {
+		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+		if (mux == 1 || ldb->lvds_mux)
+			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
+		else if (mux == 0)
+			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+	}
+
+	if (ldb->lvds_mux) {
+		const struct bus_mux *lvds_mux = NULL;
+
+		if (chno == 0)
+			lvds_mux = &ldb->lvds_mux[0];
+		else if (chno == 1)
+			lvds_mux = &ldb->lvds_mux[1];
+
+		regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
+				   mux << lvds_mux->shift);
+	}
+
+	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+}
+
 static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
 {
 	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
 
 	imx_ldb_dbg(imx_ldb_ch, "%s: %s\n", __func__, mode ? "OFF" : "ON");
+
+	if (mode)
+		imx_ldb_poweroff(imx_ldb_ch);
+	else
+		imx_ldb_poweron(imx_ldb_ch);
 }
 
 static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
@@ -186,6 +261,8 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
 
 	imx_ldb_entry_dbg(imx_ldb_ch);
 
+	imx_ldb_poweroff(imx_ldb_ch);
+
 	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
 		/* dual channel LVDS mode */
 		serial_clk = 3500UL * mode->clock;
@@ -218,45 +295,10 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
 static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
 {
 	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
-	struct imx_ldb *ldb = imx_ldb_ch->ldb;
-	int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
-	int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
 
 	imx_ldb_entry_dbg(imx_ldb_ch);
 
-	if (dual) {
-		clk_prepare_enable(ldb->clk[0]);
-		clk_prepare_enable(ldb->clk[1]);
-	}
-
-	if (imx_ldb_ch == &ldb->channel[0] || dual) {
-		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
-		if (mux == 0 || ldb->lvds_mux)
-			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
-		else if (mux == 1)
-			ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
-	}
-	if (imx_ldb_ch == &ldb->channel[1] || dual) {
-		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
-		if (mux == 1 || ldb->lvds_mux)
-			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
-		else if (mux == 0)
-			ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
-	}
-
-	if (ldb->lvds_mux) {
-		const struct bus_mux *lvds_mux = NULL;
-
-		if (imx_ldb_ch == &ldb->channel[0])
-			lvds_mux = &ldb->lvds_mux[0];
-		else if (imx_ldb_ch == &ldb->channel[1])
-			lvds_mux = &ldb->lvds_mux[1];
-
-		regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
-				   mux << lvds_mux->shift);
-	}
-
-	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+	imx_ldb_poweron(imx_ldb_ch);
 }
 
 static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
@@ -296,33 +338,10 @@ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
 static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
 {
 	struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
-	struct imx_ldb *ldb = imx_ldb_ch->ldb;
 
 	imx_ldb_entry_dbg(imx_ldb_ch);
 
-	/*
-	 * imx_ldb_encoder_disable is called by
-	 * drm_helper_disable_unused_functions without
-	 * the encoder being enabled before.
-	 */
-	if (imx_ldb_ch == &ldb->channel[0] &&
-	    (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
-		return;
-	else if (imx_ldb_ch == &ldb->channel[1] &&
-		 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
-		return;
-
-	if (imx_ldb_ch == &ldb->channel[0])
-		ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
-	else if (imx_ldb_ch == &ldb->channel[1])
-		ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
-
-	regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
-
-	if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
-		clk_disable_unprepare(ldb->clk[0]);
-		clk_disable_unprepare(ldb->clk[1]);
-	}
+	imx_ldb_poweroff(imx_ldb_ch);
 }
 
 static struct drm_connector_funcs imx_ldb_connector_funcs = {
-- 
1.7.9.5

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[PATCH 43/72] imx-drm: parallel-display: Fix typo when setting mode type

[Steve Longerbeam]

Comma expression is used to set mode type
"mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,"
which is a typo, replace it with ";".

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/parallel-display.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index 5f7d4ee..49f8308 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -74,7 +74,7 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
 		if (!mode)
 			return -EINVAL;
 		drm_mode_copy(mode, &imxpd->mode);
-		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 		drm_mode_probed_add(connector, mode);
 		num_modes++;
 	}
@@ -86,7 +86,7 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
 			return -EINVAL;
 		of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE);
 		drm_mode_copy(mode, &imxpd->mode);
-		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 		drm_mode_probed_add(connector, mode);
 		num_modes++;
 	}
-- 
1.7.9.5

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[PATCH 44/72] imx-drm: ipuv3-plane: Fix planar formats

[Steve Longerbeam]

During a mode set the U/V plane strides and buffer offsets
for planar pixel formats were not being configured in cpmem.
Fix by calling ipu_cpmem_set_yuv_planar() for planar formats.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 365cdfe..edfa72a 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -174,6 +174,10 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 			fb->pixel_format);
 		return ret;
 	}
+	if (ipu_drm_fourcc_is_planar(fb->pixel_format))
+		ipu_cpmem_set_yuv_planar(ipu_plane->ipu_ch, fb->pixel_format,
+					 fb->pitches[0], crtc_h);
+
 	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
 
 	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
-- 
1.7.9.5

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[PATCH 45/72] imx-drm: ipuv3-plane: Allow YUV space for background plane

[Steve Longerbeam]

A background plane was assuming the framebuffer pixel format was
RGB by passing IPUV3_COLORSPACE_RGB to ipu_dp_setup_channel(). Fix
by passing the actual colorspace of the framebuffer's pixel format.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index edfa72a..cbd300b 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -140,7 +140,7 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 	switch (ipu_plane->dp_flow) {
 	case IPU_DP_FLOW_SYNC_BG:
 		ret = ipu_dp_setup_channel(ipu_plane->dp,
-				IPUV3_COLORSPACE_RGB,
+				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
 				IPUV3_COLORSPACE_RGB);
 		if (ret) {
 			dev_err(dev,
-- 
1.7.9.5

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[PATCH 46/72] imx-drm: ipuv3-plane: Add more supported pixel formats

[Steve Longerbeam]

Report more supported formats to drm core via ipu_plane_formats[].

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index cbd300b..5818249 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -29,10 +29,18 @@ static const uint32_t ipu_plane_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_RGB888,
+	DRM_FORMAT_BGR888,
 	DRM_FORMAT_YUYV,
+	DRM_FORMAT_UYVY,
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_YUV420,
 	DRM_FORMAT_YVU420,
+	DRM_FORMAT_YUV422,
+	DRM_FORMAT_YVU422,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_NV16,
 };
 
 int ipu_plane_irq(struct ipu_plane *ipu_plane)
-- 
1.7.9.5

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[PATCH 47/72] imx-drm: ipuv3-plane: Implement global alpha and colorkey properties

[Steve Longerbeam]

Add support for setting global alpha and colorkey in foreground planes
using plane properties. Background planes can also support these
properties if the background plane is initialized as not private.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |  144 +++++++++++++++++++++++++++++++--
 drivers/staging/imx-drm/ipuv3-plane.h |    7 ++
 2 files changed, 146 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 5818249..1572c80 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -104,6 +104,7 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		       uint32_t src_w, uint32_t src_h)
 {
 	struct device *dev = ipu_plane->base.dev->dev;
+	bool is_bg = (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG);
 	int ret;
 
 	/* no scaling */
@@ -156,7 +157,6 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 				ret);
 			return ret;
 		}
-		ipu_dp_set_global_alpha(ipu_plane->dp, 1, 0, 1);
 		break;
 	case IPU_DP_FLOW_SYNC_FG:
 		ipu_dp_setup_channel(ipu_plane->dp,
@@ -166,6 +166,24 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		break;
 	}
 
+	if (ipu_plane->dp) {
+		ret = ipu_dp_set_global_alpha(ipu_plane->dp,
+					      ipu_plane->global_alpha_en,
+					      ipu_plane->global_alpha, is_bg);
+		if (ret) {
+			dev_err(dev, "set global alpha failed with %d\n", ret);
+			return ret;
+		}
+
+		ret = ipu_dp_set_chroma_key(ipu_plane->dp,
+					    ipu_plane->colorkey_en,
+					    ipu_plane->colorkey);
+		if (ret) {
+			dev_err(dev, "set colorkey failed with %d\n", ret);
+			return ret;
+		}
+	}
+
 	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
 			calc_bandwidth(crtc_w, crtc_h,
 				       calc_vref(mode)), crtc_w, 64);
@@ -329,13 +347,86 @@ static void ipu_plane_destroy(struct drm_plane *plane)
 	kfree(ipu_plane);
 }
 
+static int ipu_plane_set_global_alpha(struct ipu_plane *ipu_plane,
+				      u32 global_alpha)
+{
+	bool is_bg = (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG);
+	bool global_alpha_en;
+
+	if (!ipu_plane->dp)
+		return -EINVAL;
+
+	global_alpha_en = ((global_alpha & (1 << 8)) != 0);
+	global_alpha &= ~(1 << 8);
+
+	if (ipu_plane->global_alpha_en == global_alpha_en &&
+	    ipu_plane->global_alpha == global_alpha)
+		return 0;
+
+	ipu_plane->global_alpha_en = global_alpha_en;
+	ipu_plane->global_alpha = global_alpha;
+
+	if (!ipu_plane->enabled)
+		return 0;
+
+	return ipu_dp_set_global_alpha(ipu_plane->dp,
+				       ipu_plane->global_alpha_en,
+				       ipu_plane->global_alpha, is_bg);
+}
+
+static int ipu_plane_set_colorkey(struct ipu_plane *ipu_plane,
+				  u32 colorkey)
+{
+	bool colorkey_en;
+
+	if (!ipu_plane->dp)
+		return -EINVAL;
+
+	colorkey_en = ((colorkey & (1 << 24)) != 0);
+	colorkey &= ~(1 << 24);
+
+	if (ipu_plane->colorkey_en == colorkey_en &&
+	    ipu_plane->colorkey == colorkey)
+		return 0;
+
+	ipu_plane->colorkey_en = colorkey_en;
+	ipu_plane->colorkey = colorkey;
+
+	if (!ipu_plane->enabled)
+		return 0;
+
+	return ipu_dp_set_chroma_key(ipu_plane->dp,
+				     ipu_plane->colorkey_en,
+				     ipu_plane->colorkey);
+}
+
+static int ipu_plane_set_property(struct drm_plane *plane,
+				  struct drm_property *property,
+				  uint64_t value)
+{
+	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+	int ret;
+
+	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
+
+	if (property == ipu_plane->global_alpha_prop)
+		ret = ipu_plane_set_global_alpha(ipu_plane, value);
+	else if (property == ipu_plane->colorkey_prop)
+		ret = ipu_plane_set_colorkey(ipu_plane, value);
+	else
+		ret = -EINVAL;
+
+	return ret;
+}
+
 static struct drm_plane_funcs ipu_plane_funcs = {
 	.update_plane	= ipu_update_plane,
 	.disable_plane	= ipu_disable_plane,
 	.destroy	= ipu_plane_destroy,
+	.set_property	= ipu_plane_set_property,
 };
 
-struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
+struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 				 int dma, int dp, unsigned int possible_crtcs,
 				 bool priv)
 {
@@ -355,15 +446,58 @@ struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
 	ipu_plane->dma = dma;
 	ipu_plane->dp_flow = dp;
 
-	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
+	ret = drm_plane_init(drm, &ipu_plane->base, possible_crtcs,
 			     &ipu_plane_funcs, ipu_plane_formats,
 			     ARRAY_SIZE(ipu_plane_formats),
 			     priv);
 	if (ret) {
 		DRM_ERROR("failed to initialize plane\n");
-		kfree(ipu_plane);
-		return ERR_PTR(ret);
+		goto err_free;
 	}
 
+	/* default global alpha is enabled and completely opaque */
+	ipu_plane->global_alpha_en = true;
+	ipu_plane->global_alpha = 255;
+
+	/* for private planes, skip setting up properties */
+	if (priv)
+		return ipu_plane;
+
+	/*
+	 * global alpha range is 0 - 255. Bit 8 is used as a
+	 * flag to disable or enable global alpha.
+	 */
+	ipu_plane->global_alpha_prop = drm_property_create_range(drm, 0,
+								 "alpha",
+								 0, 0x1ff);
+	if (!ipu_plane->global_alpha_prop) {
+		DRM_ERROR("failed to create global alpha property\n");
+		ret = -ENOMEM;
+		goto err_free;
+	}
+
+	/*
+	 * The color key is an RGB24 value. Bit 24 is used as a
+	 * flag to disable or enable color keying.
+	 */
+	ipu_plane->colorkey_prop = drm_property_create_range(drm, 0,
+							     "colorkey",
+							     0, 0x01ffffff);
+	if (!ipu_plane->colorkey_prop) {
+		DRM_ERROR("failed to create colorkey property\n");
+		ret = -ENOMEM;
+		goto err_free;
+	}
+
+	drm_object_attach_property(&ipu_plane->base.base,
+				   ipu_plane->global_alpha_prop,
+				   0x1ff);
+	drm_object_attach_property(&ipu_plane->base.base,
+				   ipu_plane->colorkey_prop,
+				   0);
 	return ipu_plane;
+
+err_free:
+	kfree(ipu_plane);
+	return ERR_PTR(ret);
 }
diff --git a/drivers/staging/imx-drm/ipuv3-plane.h b/drivers/staging/imx-drm/ipuv3-plane.h
index c0aae5b..b4daee5 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.h
+++ b/drivers/staging/imx-drm/ipuv3-plane.h
@@ -27,6 +27,13 @@ struct ipu_plane {
 	int			x;
 	int			y;
 
+	struct drm_property	*global_alpha_prop;
+	struct drm_property	*colorkey_prop;
+	bool			global_alpha_en;
+	u32			global_alpha;
+	bool			colorkey_en;
+	u32			colorkey;
+
 	bool			enabled;
 };
 
-- 
1.7.9.5

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[PATCH 48/72] imx-drm: hdmi: rework irq request/free

[Steve Longerbeam]

Rearrange how HDMI driver requests and frees irq. Currently the driver
has two problems:

1) if imx_hdmi_register() fails, irq still can trigger and cause oops
2) irq is enabled too early, before all fields are initialized, so
triggered irq can cause oops.

Fix by moving irq request and activation to very end of imx_hdmi_bind(),
especially after imx_hdmi_register(). Then there's no possible way there
could be a (spurious) interrupt after a failed imx_hdmi_register() but
before the irq is freed.

Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-hdmi.c |   33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index 801a3eb..db3906f 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -122,6 +122,7 @@ struct imx_hdmi {
 
 	struct hdmi_data_info hdmi_data;
 	int vic;
+	int irq;
 
 	u8 edid[HDMI_EDID_LEN];
 	bool cable_plugin;
@@ -1593,7 +1594,7 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 	struct device_node *ddc_node;
 	struct imx_hdmi *hdmi;
 	struct resource *iores;
-	int ret, irq;
+	int ret;
 
 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 	if (!hdmi)
@@ -1620,16 +1621,6 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 		dev_dbg(hdmi->dev, "no ddc property found\n");
 	}
 
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-
-	ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
-					imx_hdmi_irq, IRQF_SHARED,
-					dev_name(dev), hdmi);
-	if (ret)
-		return ret;
-
 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	hdmi->regs = devm_ioremap_resource(dev, iores);
 	if (IS_ERR(hdmi->regs))
@@ -1685,6 +1676,10 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 	 */
 	hdmi_init_clk_regenerator(hdmi);
 
+	ret = imx_hdmi_register(drm, hdmi);
+	if (ret)
+		goto err_isfr;
+
 	/*
 	 * Configure registers related to HDMI interrupt
 	 * generation before registering IRQ.
@@ -1694,14 +1689,21 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 	/* Clear Hotplug interrupts */
 	hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
 
-	ret = imx_hdmi_fb_registered(hdmi);
-	if (ret)
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0)
 		goto err_iahb;
+	hdmi->irq = ret;
 
-	ret = imx_hdmi_register(drm, hdmi);
+	ret = devm_request_threaded_irq(dev, hdmi->irq, imx_hdmi_hardirq,
+					imx_hdmi_irq, IRQF_SHARED,
+					dev_name(dev), hdmi);
 	if (ret)
 		goto err_iahb;
 
+	ret = imx_hdmi_fb_registered(hdmi);
+	if (ret)
+		goto err_irq;
+
 	/* Unmute interrupts */
 	hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
 
@@ -1709,6 +1711,8 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 
 	return 0;
 
+err_irq:
+	devm_free_irq(dev, hdmi->irq, hdmi);
 err_iahb:
 	clk_disable_unprepare(hdmi->iahb_clk);
 err_isfr:
@@ -1724,6 +1728,7 @@ static void imx_hdmi_unbind(struct device *dev, struct device *master,
 
 	/* Disable all interrupts */
 	hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
+	devm_free_irq(dev, hdmi->irq, hdmi);
 
 	hdmi->connector.funcs->destroy(&hdmi->connector);
 	hdmi->encoder.funcs->destroy(&hdmi->encoder);
-- 
1.7.9.5

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[PATCH 49/72] imx-drm: imx-ldb: Add DDC support

[Steve Longerbeam]

Add support for reading EDID over Display Data Channel. If no DDC
adapter is available, falls back to hardcoded EDID or display-timings
node as before.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-ldb.c |   39 +++++++++++++++++++++++++++++--------
 1 file changed, 31 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 1eb632f..6c16cf2 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -61,6 +61,7 @@ struct imx_ldb_channel {
 	struct drm_connector connector;
 	struct drm_encoder encoder;
 	struct device_node *child;
+	struct i2c_adapter *ddc;
 	int chno;
 	void *edid;
 	int edid_len;
@@ -103,6 +104,9 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
 
 	imx_ldb_entry_dbg(imx_ldb_ch);
 
+	if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
+		imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
+
 	if (imx_ldb_ch->edid) {
 		drm_mode_connector_update_edid_property(connector,
 							imx_ldb_ch->edid);
@@ -529,6 +533,7 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 
 	for_each_child_of_node(np, child) {
 		struct imx_ldb_channel *channel;
+		struct device_node *ddc_node;
 
 		ret = of_property_read_u32(child, "reg", &i);
 		if (ret || i < 0 || i > 1)
@@ -547,14 +552,30 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 		channel->chno = i;
 		channel->child = child;
 
-		edidp = of_get_property(child, "edid", &channel->edid_len);
-		if (edidp) {
-			channel->edid = kmemdup(edidp, channel->edid_len,
-						GFP_KERNEL);
-		} else {
-			ret = of_get_drm_display_mode(child, &channel->mode, 0);
-			if (!ret)
-				channel->mode_valid = 1;
+		ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
+		if (ddc_node) {
+			channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
+			of_node_put(ddc_node);
+		}
+
+		if (!channel->ddc) {
+			/* if no DDC available, fallback to hardcoded EDID */
+			dev_dbg(dev, "no ddc available\n");
+
+			edidp = of_get_property(child, "edid",
+						&channel->edid_len);
+			if (edidp) {
+				channel->edid = kmemdup(edidp,
+							channel->edid_len,
+							GFP_KERNEL);
+			} else {
+				/* fallback to display-timings node */
+				ret = of_get_drm_display_mode(child,
+							      &channel->mode,
+							      0);
+				if (!ret)
+					channel->mode_valid = 1;
+			}
 		}
 
 		ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
@@ -616,6 +637,8 @@ static void imx_ldb_unbind(struct device *dev, struct device *master,
 
 		channel->connector.funcs->destroy(&channel->connector);
 		channel->encoder.funcs->destroy(&channel->encoder);
+
+		i2c_put_adapter(channel->ddc);
 	}
 }
 
-- 
1.7.9.5

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[PATCH 50/72] imx-drm: Fix separate primary plane objects

[Steve Longerbeam]

drm_crtc_init() will create a primary plane object, while imx-drm also
creates its own, thus two primary planes are separately created, and
can cause difficult bugs to track down in the future.

Fix by using drm_crtc_init_with_planes() instead of drm_crtc_init(),
so that we can hand drm our own primary plane object, thus crtc->primary
and ipu_crtc->plane[0].base now are the same object.

To do this we need to statically declare the primary and overlay
planes in the crtc driver, to avoid a chicken-before-the-egg problem,
the primary plane must exist when imx_drm_add_crtc() is called but
before ipu_plane_init().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |    3 +-
 drivers/staging/imx-drm/imx-drm.h      |    1 +
 drivers/staging/imx-drm/ipuv3-crtc.c   |   54 ++++++++++++++++++--------------
 drivers/staging/imx-drm/ipuv3-plane.c  |   32 +++++--------------
 drivers/staging/imx-drm/ipuv3-plane.h  |    6 ++--
 5 files changed, 45 insertions(+), 51 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index e5ec010..59200ff 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -342,6 +342,7 @@ err_kms:
  * imx_drm_add_crtc - add a new crtc
  */
 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
+		struct drm_plane *primary,
 		struct imx_drm_crtc **new_crtc,
 		const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs,
 		struct device_node *port)
@@ -380,7 +381,7 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 	drm_crtc_helper_add(crtc,
 			imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
 
-	drm_crtc_init(drm, crtc,
+	drm_crtc_init_with_planes(drm, crtc, primary, NULL,
 			imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
 
 	return 0;
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index 7453ae0..3a30f16 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -24,6 +24,7 @@ struct imx_drm_crtc_helper_funcs {
 };
 
 int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
+		struct drm_plane *primary,
 		struct imx_drm_crtc **new_crtc,
 		const struct imx_drm_crtc_helper_funcs *imx_helper_funcs,
 		struct device_node *port);
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 5a60017..593261f 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -84,7 +84,8 @@ struct ipu_crtc {
 	const struct ipu_channels *ch;
 
 	/* plane[0] is the full plane, plane[1] is the partial plane */
-	struct ipu_plane	*plane[2];
+	struct ipu_plane	plane[2];
+	bool			have_overlay; /* we have a partial plane */
 
 	struct ipu_dc		*dc;
 	struct ipu_di		*di;
@@ -106,7 +107,7 @@ static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
 		return;
 
 	ipu_dc_enable(ipu_crtc->dc);
-	ipu_plane_enable(ipu_crtc->plane[0]);
+	ipu_plane_enable(&ipu_crtc->plane[0]);
 	/* Start DC channel and DI after IDMAC */
 	ipu_dc_enable_channel(ipu_crtc->dc);
 	ipu_di_enable(ipu_crtc->di);
@@ -123,7 +124,7 @@ static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
 	/* Stop DC channel and DI before IDMAC */
 	ipu_dc_disable_channel(ipu_crtc->dc);
 	ipu_di_disable(ipu_crtc->di);
-	ipu_plane_disable(ipu_crtc->plane[0]);
+	ipu_plane_disable(&ipu_crtc->plane[0]);
 	ipu_dc_disable(ipu_crtc->dc);
 	ipu_di_disable_clock(ipu_crtc->di);
 
@@ -241,7 +242,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 		return ret;
 	}
 
-	return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
+	return ipu_plane_mode_set(&ipu_crtc->plane[0], crtc, mode,
 				  crtc->primary->fb,
 				  0, 0, mode->hdisplay, mode->vdisplay,
 				  x, y, mode->hdisplay, mode->vdisplay);
@@ -267,7 +268,7 @@ static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
 	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
 
 	if (ipu_crtc->newfb) {
-		struct ipu_plane *plane = ipu_crtc->plane[0];
+		struct ipu_plane *plane = &ipu_crtc->plane[0];
 
 		ipu_crtc->newfb = NULL;
 		ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
@@ -474,20 +475,27 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 		return ret;
 	}
 
-	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
-			       &ipu_crtc_helper_funcs, ipu_crtc->port);
+	ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->plane[0].base,
+			       &ipu_crtc->imx_crtc, &ipu_crtc_helper_funcs,
+			       ipu_crtc->port);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
 		goto err_put_resources;
 	}
 
 	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
-	ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev,
-					    ipu_crtc->ipu,
-					    ipu_crtc->ch->dma[0],
-					    ipu_crtc->ch->dp[0],
-					    BIT(id), true);
-	ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
+	ret = ipu_plane_init(&ipu_crtc->plane[0], drm,
+			     ipu_crtc->ipu,
+			     ipu_crtc->ch->dma[0],
+			     ipu_crtc->ch->dp[0],
+			     BIT(id), true);
+	if (ret) {
+		dev_err(ipu_crtc->dev, "init primary plane failed with %d\n",
+			ret);
+		goto err_remove_crtc;
+	}
+
+	ret = ipu_plane_get_resources(&ipu_crtc->plane[0]);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
 			ret);
@@ -496,16 +504,16 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 
 	/* If this crtc is using the DP, add an overlay plane */
 	if (ipu_crtc->ch->dp[1] >= 0) {
-		ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev,
-						    ipu_crtc->ipu,
-						    ipu_crtc->ch->dma[1],
-						    ipu_crtc->ch->dp[1],
-						    BIT(id), false);
-		if (IS_ERR(ipu_crtc->plane[1]))
-			ipu_crtc->plane[1] = NULL;
+		ret = ipu_plane_init(&ipu_crtc->plane[1], drm,
+				     ipu_crtc->ipu,
+				     ipu_crtc->ch->dma[1],
+				     ipu_crtc->ch->dp[1],
+				     BIT(id), false);
+
+		ipu_crtc->have_overlay = ret ? false : true;
 	}
 
-	ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
+	ipu_crtc->irq = ipu_plane_irq(&ipu_crtc->plane[0]);
 	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
 			"imx_drm", ipu_crtc);
 	if (ret < 0) {
@@ -516,7 +524,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 	return 0;
 
 err_put_plane_res:
-	ipu_plane_put_resources(ipu_crtc->plane[0]);
+	ipu_plane_put_resources(&ipu_crtc->plane[0]);
 err_remove_crtc:
 	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
 err_put_resources:
@@ -553,7 +561,7 @@ static void ipu_drm_unbind(struct device *dev, struct device *master,
 
 	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
 
-	ipu_plane_put_resources(ipu_crtc->plane[0]);
+	ipu_plane_put_resources(&ipu_crtc->plane[0]);
 	ipu_put_resources(ipu_crtc);
 }
 
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 1572c80..51a257a 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -338,13 +338,10 @@ static int ipu_disable_plane(struct drm_plane *plane)
 
 static void ipu_plane_destroy(struct drm_plane *plane)
 {
-	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
-
 	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 
 	ipu_disable_plane(plane);
 	drm_plane_cleanup(plane);
-	kfree(ipu_plane);
 }
 
 static int ipu_plane_set_global_alpha(struct ipu_plane *ipu_plane,
@@ -426,22 +423,15 @@ static struct drm_plane_funcs ipu_plane_funcs = {
 	.set_property	= ipu_plane_set_property,
 };
 
-struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
-				 int dma, int dp, unsigned int possible_crtcs,
-				 bool priv)
+int ipu_plane_init(struct ipu_plane *ipu_plane, struct drm_device *drm,
+		   struct ipu_soc *ipu, int dma, int dp,
+		   unsigned int possible_crtcs, bool priv)
 {
-	struct ipu_plane *ipu_plane;
 	int ret;
 
 	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
 		      dma, dp, possible_crtcs);
 
-	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
-	if (!ipu_plane) {
-		DRM_ERROR("failed to allocate plane\n");
-		return ERR_PTR(-ENOMEM);
-	}
-
 	ipu_plane->ipu = ipu;
 	ipu_plane->dma = dma;
 	ipu_plane->dp_flow = dp;
@@ -452,7 +442,7 @@ struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 			     priv);
 	if (ret) {
 		DRM_ERROR("failed to initialize plane\n");
-		goto err_free;
+		return ret;
 	}
 
 	/* default global alpha is enabled and completely opaque */
@@ -461,7 +451,7 @@ struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 
 	/* for private planes, skip setting up properties */
 	if (priv)
-		return ipu_plane;
+		return 0;
 
 	/*
 	 * global alpha range is 0 - 255. Bit 8 is used as a
@@ -472,8 +462,7 @@ struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 								 0, 0x1ff);
 	if (!ipu_plane->global_alpha_prop) {
 		DRM_ERROR("failed to create global alpha property\n");
-		ret = -ENOMEM;
-		goto err_free;
+		return -ENOMEM;
 	}
 
 	/*
@@ -485,8 +474,7 @@ struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 							     0, 0x01ffffff);
 	if (!ipu_plane->colorkey_prop) {
 		DRM_ERROR("failed to create colorkey property\n");
-		ret = -ENOMEM;
-		goto err_free;
+		return -ENOMEM;
 	}
 
 	drm_object_attach_property(&ipu_plane->base.base,
@@ -495,9 +483,5 @@ struct ipu_plane *ipu_plane_init(struct drm_device *drm, struct ipu_soc *ipu,
 	drm_object_attach_property(&ipu_plane->base.base,
 				   ipu_plane->colorkey_prop,
 				   0);
-	return ipu_plane;
-
-err_free:
-	kfree(ipu_plane);
-	return ERR_PTR(ret);
+	return 0;
 }
diff --git a/drivers/staging/imx-drm/ipuv3-plane.h b/drivers/staging/imx-drm/ipuv3-plane.h
index b4daee5..1487a08 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.h
+++ b/drivers/staging/imx-drm/ipuv3-plane.h
@@ -37,9 +37,9 @@ struct ipu_plane {
 	bool			enabled;
 };
 
-struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
-				 int dma, int dp, unsigned int possible_crtcs,
-				 bool priv);
+int ipu_plane_init(struct ipu_plane *ipu_plane, struct drm_device *drm,
+		   struct ipu_soc *ipu, int dma, int dp,
+		   unsigned int possible_crtcs, bool priv);
 
 /* Init IDMAC, DMFC, DP */
 int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
-- 
1.7.9.5

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 51/72] imx-drm: Move page flip handling to plane driver

[Steve Longerbeam]

Move page flip handling and associated vblank handling to the
plane driver. This paves the way to allow page flipping in not
just the primary plane but the overlay plane as well.

To do this the primary and overlay planes are assigned a pipe value
suitable for passing to the drm core vblank methods (drm_vblank_get,
put,handle).

We modify imx-drm core slightly to make room for primary and overlay
pipe id's when assigning the crtc pipe. So crtc 0 has a primary pipe
value of 0 and overlay pipe value 1, crtc 1 has primary pipe value 2
and overlay pipe value 3, etc. imx_drm_crtc_id() returns the primary
pipe divided by 2 as an id value to form possible crtc masks.

The drm core vblank sees these planes as additional crtcs (pipes) and
does not need significant changes.

The plane driver implements page flip using idmac double-buffering.
Without double-buffering, a page flip operation changes the idmac
channel buffer base address while the buffer is still active. This
is not recommended according to the reference manual.

With double-buffering, a page-flip can set the base of the inactive
buffer before switching to it using buffer-ready control.

Note that for the synchronous display channels, the buffer ready signal can
be driven either by the ARM core writing to the buffer ready registers,
or by the DI.

When the ARM core does not drive ping-pong buffer ready selection at
every EOF, the DI will drive buffer ready, triggered by a timer located
in the DI. The IPU's FSU unit will quickly settle on a single buffer and
then remain at that buffer, the DI driving buffer ready at that buffer.

If the ARM core (the plane driver) then selects the other (inactive)
buffer, the FSU switches to it and then remains at this buffer, the DI
again taking over buffer ready signalling at the new buffer, until the
ARM core makes the next buffer selection.

So we take advantage of this behaviour and use buffer selection to
switch to the other buffer when we want to flip to another DRM
framebuffer for page-flip.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |   86 +++++++++--------
 drivers/staging/imx-drm/imx-drm.h      |   10 +-
 drivers/staging/imx-drm/ipuv3-crtc.c   |  111 ++++++++--------------
 drivers/staging/imx-drm/ipuv3-plane.c  |  158 ++++++++++++++++++++++++++++----
 drivers/staging/imx-drm/ipuv3-plane.h  |   21 ++++-
 5 files changed, 252 insertions(+), 134 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 59200ff..e0178d6 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -28,6 +28,7 @@
 #include "imx-drm.h"
 
 #define MAX_CRTC	4
+#define MAX_PIPES	(2 * MAX_CRTC)
 
 struct imx_drm_crtc;
 
@@ -53,12 +54,29 @@ struct imx_drm_crtc {
 static int legacyfb_depth = 16;
 module_param(legacyfb_depth, int, 0444);
 
+static inline int pipe_to_crtc_id(int pipe)
+{
+	return pipe >> 1;
+}
+
 int imx_drm_crtc_id(struct imx_drm_crtc *crtc)
 {
-	return crtc->pipe;
+	return pipe_to_crtc_id(crtc->pipe);
 }
 EXPORT_SYMBOL_GPL(imx_drm_crtc_id);
 
+int imx_drm_primary_plane_pipe(struct imx_drm_crtc *crtc)
+{
+	return crtc->pipe;
+}
+EXPORT_SYMBOL_GPL(imx_drm_primary_plane_pipe);
+
+int imx_drm_overlay_plane_pipe(struct imx_drm_crtc *crtc)
+{
+	return crtc->pipe + 1;
+}
+EXPORT_SYMBOL_GPL(imx_drm_overlay_plane_pipe);
+
 static void imx_drm_driver_lastclose(struct drm_device *drm)
 {
 #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
@@ -129,30 +147,16 @@ int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt)
 }
 EXPORT_SYMBOL_GPL(imx_drm_panel_format);
 
-int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc)
-{
-	return drm_vblank_get(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
-}
-EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_get);
-
-void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc)
-{
-	drm_vblank_put(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
-}
-EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_put);
-
-void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc)
-{
-	drm_handle_vblank(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
-}
-EXPORT_SYMBOL_GPL(imx_drm_handle_vblank);
-
-static int imx_drm_enable_vblank(struct drm_device *drm, int crtc)
+static int imx_drm_enable_vblank(struct drm_device *drm, int pipe)
 {
 	struct imx_drm_device *imxdrm = drm->dev_private;
-	struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+	struct imx_drm_crtc *imx_drm_crtc;
 	int ret;
 
+	if (pipe >= MAX_PIPES)
+		return -EINVAL;
+
+	imx_drm_crtc = imxdrm->crtc[pipe_to_crtc_id(pipe)];
 	if (!imx_drm_crtc)
 		return -EINVAL;
 
@@ -160,35 +164,40 @@ static int imx_drm_enable_vblank(struct drm_device *drm, int crtc)
 		return -ENOSYS;
 
 	ret = imx_drm_crtc->imx_drm_helper_funcs.enable_vblank(
-			imx_drm_crtc->crtc);
+		imx_drm_crtc->crtc, pipe);
 
 	return ret;
 }
 
-static void imx_drm_disable_vblank(struct drm_device *drm, int crtc)
+static void imx_drm_disable_vblank(struct drm_device *drm, int pipe)
 {
 	struct imx_drm_device *imxdrm = drm->dev_private;
-	struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+	struct imx_drm_crtc *imx_drm_crtc;
 
+	if (pipe >= MAX_PIPES)
+		return;
+
+	imx_drm_crtc = imxdrm->crtc[pipe_to_crtc_id(pipe)];
 	if (!imx_drm_crtc)
 		return;
 
 	if (!imx_drm_crtc->imx_drm_helper_funcs.disable_vblank)
 		return;
 
-	imx_drm_crtc->imx_drm_helper_funcs.disable_vblank(imx_drm_crtc->crtc);
+	imx_drm_crtc->imx_drm_helper_funcs.disable_vblank(
+		imx_drm_crtc->crtc, pipe);
 }
 
 static void imx_drm_driver_preclose(struct drm_device *drm,
 		struct drm_file *file)
 {
-	int i;
+	int pipe;
 
 	if (!file->is_master)
 		return;
 
-	for (i = 0; i < MAX_CRTC; i++)
-		imx_drm_disable_vblank(drm, i);
+	for (pipe = 0; pipe < MAX_PIPES; pipe++)
+		imx_drm_disable_vblank(drm, pipe);
 }
 
 static const struct file_operations imx_drm_driver_fops = {
@@ -271,7 +280,7 @@ static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags)
 
 	drm_mode_config_init(drm);
 
-	ret = drm_vblank_init(drm, MAX_CRTC);
+	ret = drm_vblank_init(drm, MAX_PIPES);
 	if (ret)
 		goto err_kms;
 
@@ -349,13 +358,13 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 {
 	struct imx_drm_device *imxdrm = drm->dev_private;
 	struct imx_drm_crtc *imx_drm_crtc;
-	int ret;
+	int id, ret;
 
 	/*
-	 * The vblank arrays are dimensioned by MAX_CRTC - we can't
+	 * The vblank arrays are dimensioned by MAX_PIPES - we can't
 	 * pass IDs greater than this to those functions.
 	 */
-	if (imxdrm->pipes >= MAX_CRTC)
+	if (imxdrm->pipes >= MAX_PIPES)
 		return -EINVAL;
 
 	if (imxdrm->drm->open_count)
@@ -366,11 +375,15 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 		return -ENOMEM;
 
 	imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs;
-	imx_drm_crtc->pipe = imxdrm->pipes++;
+	imx_drm_crtc->pipe = imxdrm->pipes;
 	imx_drm_crtc->port = port;
 	imx_drm_crtc->crtc = crtc;
 
-	imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc;
+	imxdrm->pipes += 2;
+
+	id = pipe_to_crtc_id(imx_drm_crtc->pipe);
+
+	imxdrm->crtc[id] = imx_drm_crtc;
 
 	*new_crtc = imx_drm_crtc;
 
@@ -387,7 +400,7 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 	return 0;
 
 err_register:
-	imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+	imxdrm->crtc[id] = NULL;
 	kfree(imx_drm_crtc);
 	return ret;
 }
@@ -399,10 +412,11 @@ EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
 int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc)
 {
 	struct imx_drm_device *imxdrm = imx_drm_crtc->crtc->dev->dev_private;
+	int id = pipe_to_crtc_id(imx_drm_crtc->pipe);
 
 	drm_crtc_cleanup(imx_drm_crtc->crtc);
 
-	imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+	imxdrm->crtc[id] = NULL;
 
 	kfree(imx_drm_crtc);
 
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index 3a30f16..ec084fe 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -13,10 +13,12 @@ struct imx_drm_crtc;
 struct platform_device;
 
 int imx_drm_crtc_id(struct imx_drm_crtc *crtc);
+int imx_drm_primary_plane_pipe(struct imx_drm_crtc *crtc);
+int imx_drm_overlay_plane_pipe(struct imx_drm_crtc *crtc);
 
 struct imx_drm_crtc_helper_funcs {
-	int (*enable_vblank)(struct drm_crtc *crtc);
-	void (*disable_vblank)(struct drm_crtc *crtc);
+	int (*enable_vblank)(struct drm_crtc *crtc, int pipe);
+	void (*disable_vblank)(struct drm_crtc *crtc, int pipe);
 	int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 encoder_type,
 			u32 pix_fmt, int hsync_pin, int vsync_pin);
 	const struct drm_crtc_helper_funcs *crtc_helper_funcs;
@@ -33,10 +35,6 @@ int imx_drm_init_drm(struct platform_device *pdev,
 		int preferred_bpp);
 int imx_drm_exit_drm(void);
 
-int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc);
-void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc);
-void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc);
-
 void imx_drm_mode_config_init(struct drm_device *drm);
 
 struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 593261f..423b004 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -90,9 +90,7 @@ struct ipu_crtc {
 	struct ipu_dc		*dc;
 	struct ipu_di		*di;
 	int			enabled;
-	struct drm_pending_vblank_event *page_flip_event;
-	struct drm_framebuffer	*newfb;
-	int			irq;
+
 	u32			interface_pix_fmt;
 	unsigned long		di_clkflags;
 	int			di_hsync_pin;
@@ -101,6 +99,22 @@ struct ipu_crtc {
 
 #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
 
+static struct ipu_plane *pipe_to_plane(struct ipu_crtc *ipu_crtc,
+				       int pipe)
+{
+	struct ipu_plane *plane;
+
+	plane = &ipu_crtc->plane[0];
+	if (pipe == plane->pipe)
+		return plane;
+
+	plane = &ipu_crtc->plane[1];
+	if (ipu_crtc->have_overlay && pipe == plane->pipe)
+		return plane;
+
+	return NULL;
+}
+
 static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
 {
 	if (ipu_crtc->enabled)
@@ -149,36 +163,18 @@ static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
 	}
 }
 
-static int ipu_page_flip(struct drm_crtc *crtc,
+static int ipu_crtc_page_flip(struct drm_crtc *crtc,
 		struct drm_framebuffer *fb,
 		struct drm_pending_vblank_event *event,
 		uint32_t page_flip_flags)
 {
-	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
-	int ret;
-
-	if (ipu_crtc->newfb)
-		return -EBUSY;
-
-	ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
-	if (ret) {
-		dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
-		list_del(&event->base.link);
-
-		return ret;
-	}
-
-	ipu_crtc->newfb = fb;
-	ipu_crtc->page_flip_event = event;
-	crtc->primary->fb = fb;
-
-	return 0;
+	return ipu_plane_page_flip(crtc->primary, fb, event, page_flip_flags);
 }
 
 static const struct drm_crtc_funcs ipu_crtc_funcs = {
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = drm_crtc_cleanup,
-	.page_flip = ipu_page_flip,
+	.page_flip = ipu_crtc_page_flip,
 };
 
 static int ipu_crtc_mode_set(struct drm_crtc *crtc,
@@ -248,37 +244,6 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 				  x, y, mode->hdisplay, mode->vdisplay);
 }
 
-static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
-{
-	unsigned long flags;
-	struct drm_device *drm = ipu_crtc->base.dev;
-
-	spin_lock_irqsave(&drm->event_lock, flags);
-	if (ipu_crtc->page_flip_event)
-		drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
-	ipu_crtc->page_flip_event = NULL;
-	imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
-	spin_unlock_irqrestore(&drm->event_lock, flags);
-}
-
-static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
-{
-	struct ipu_crtc *ipu_crtc = dev_id;
-
-	imx_drm_handle_vblank(ipu_crtc->imx_crtc);
-
-	if (ipu_crtc->newfb) {
-		struct ipu_plane *plane = &ipu_crtc->plane[0];
-
-		ipu_crtc->newfb = NULL;
-		ipu_plane_set_base(plane, ipu_crtc->base.primary->fb,
-				   plane->x, plane->y);
-		ipu_crtc_handle_pageflip(ipu_crtc);
-	}
-
-	return IRQ_HANDLED;
-}
-
 static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
 				  const struct drm_display_mode *mode,
 				  struct drm_display_mode *adjusted_mode)
@@ -308,17 +273,26 @@ static struct drm_crtc_helper_funcs ipu_helper_funcs = {
 	.commit = ipu_crtc_commit,
 };
 
-static int ipu_enable_vblank(struct drm_crtc *crtc)
+static int ipu_enable_vblank(struct drm_crtc *crtc, int pipe)
 {
-	return 0;
+	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+	struct ipu_plane *ipu_plane = pipe_to_plane(ipu_crtc, pipe);
+
+	if (!ipu_plane)
+		return -EINVAL;
+
+	return ipu_plane_enable_vblank(ipu_plane);
 }
 
-static void ipu_disable_vblank(struct drm_crtc *crtc)
+static void ipu_disable_vblank(struct drm_crtc *crtc, int pipe)
 {
 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+	struct ipu_plane *ipu_plane = pipe_to_plane(ipu_crtc, pipe);
+
+	if (!ipu_plane)
+		return;
 
-	ipu_crtc->page_flip_event = NULL;
-	ipu_crtc->newfb = NULL;
+	ipu_plane_disable_vblank(ipu_plane);
 }
 
 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
@@ -465,8 +439,8 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 			 struct drm_device *drm)
 {
 	struct device_node *np = ipu_crtc->dev->of_node;
+	int id, primary_pipe, overlay_pipe;
 	int ret;
-	int id;
 
 	ret = ipu_get_resources(ipu_crtc, np);
 	if (ret) {
@@ -484,8 +458,11 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 	}
 
 	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
+	primary_pipe = imx_drm_primary_plane_pipe(ipu_crtc->imx_crtc);
+
 	ret = ipu_plane_init(&ipu_crtc->plane[0], drm,
 			     ipu_crtc->ipu,
+			     primary_pipe,
 			     ipu_crtc->ch->dma[0],
 			     ipu_crtc->ch->dp[0],
 			     BIT(id), true);
@@ -504,8 +481,10 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 
 	/* If this crtc is using the DP, add an overlay plane */
 	if (ipu_crtc->ch->dp[1] >= 0) {
+		overlay_pipe = imx_drm_overlay_plane_pipe(ipu_crtc->imx_crtc);
 		ret = ipu_plane_init(&ipu_crtc->plane[1], drm,
 				     ipu_crtc->ipu,
+				     overlay_pipe,
 				     ipu_crtc->ch->dma[1],
 				     ipu_crtc->ch->dp[1],
 				     BIT(id), false);
@@ -513,18 +492,8 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 		ipu_crtc->have_overlay = ret ? false : true;
 	}
 
-	ipu_crtc->irq = ipu_plane_irq(&ipu_crtc->plane[0]);
-	ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
-			"imx_drm", ipu_crtc);
-	if (ret < 0) {
-		dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
-		goto err_put_plane_res;
-	}
-
 	return 0;
 
-err_put_plane_res:
-	ipu_plane_put_resources(&ipu_crtc->plane[0]);
 err_remove_crtc:
 	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
 err_put_resources:
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 51a257a..76ac178 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -43,12 +43,6 @@ static const uint32_t ipu_plane_formats[] = {
 	DRM_FORMAT_NV16,
 };
 
-int ipu_plane_irq(struct ipu_plane *ipu_plane)
-{
-	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
-				     IPU_IRQ_EOF);
-}
-
 static int calc_vref(struct drm_display_mode *mode)
 {
 	unsigned long htotal, vtotal;
@@ -67,8 +61,8 @@ static inline int calc_bandwidth(int width, int height, unsigned int vref)
 	return width * height * vref;
 }
 
-int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
-		       int x, int y)
+static int set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
+		    int bufnum, int x, int y)
 {
 	struct drm_gem_cma_object *cma_obj;
 	unsigned long eba;
@@ -79,15 +73,19 @@ int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
 		return -EFAULT;
 	}
 
-	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
-		&cma_obj->paddr, x, y);
+	DRM_DEBUG_KMS("phys = %pad, x = %d, y = %d", &cma_obj->paddr, x, y);
 
 	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
 
 	eba = cma_obj->paddr + fb->offsets[0] +
 	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
-	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
-	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
+
+	/* bufnum < 0 means set both buffer addresses */
+	if (bufnum < 0) {
+		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
+		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
+	} else
+		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, bufnum, eba);
 
 	/* cache offsets for subsequent pageflips */
 	ipu_plane->x = x;
@@ -96,6 +94,62 @@ int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
 	return 0;
 }
 
+static int page_flip(struct ipu_plane *ipu_plane,
+		     struct drm_framebuffer *fb)
+{
+	int curbuf, ret;
+
+	curbuf = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
+	curbuf ^= 1;
+
+	DRM_DEBUG_KMS("pipe %d: page flip to %d\n", ipu_plane->pipe, curbuf);
+
+	ret = set_base(ipu_plane, fb, curbuf, ipu_plane->x, ipu_plane->y);
+	if (!ret)
+		ipu_idmac_select_buffer(ipu_plane->ipu_ch, curbuf);
+
+	return ret;
+}
+
+static void handle_page_flip_event(struct ipu_plane *ipu_plane)
+{
+	struct drm_device *drm = ipu_plane->base.dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&drm->event_lock, flags);
+	if (ipu_plane->page_flip_event)
+		drm_send_vblank_event(drm, -1, ipu_plane->page_flip_event);
+	ipu_plane->page_flip_event = NULL;
+	drm_vblank_put(drm, ipu_plane->pipe);
+	spin_unlock_irqrestore(&drm->event_lock, flags);
+}
+
+static irqreturn_t ipu_plane_irq_handler(int irq, void *dev_id)
+{
+	struct ipu_plane *ipu_plane = dev_id;
+
+	drm_handle_vblank(ipu_plane->base.dev, ipu_plane->pipe);
+
+	if (ipu_plane->newfb) {
+		page_flip(ipu_plane, ipu_plane->newfb);
+		ipu_plane->newfb = NULL;
+		handle_page_flip_event(ipu_plane);
+	}
+
+	return IRQ_HANDLED;
+}
+
+int ipu_plane_enable_vblank(struct ipu_plane *ipu_plane)
+{
+	return 0;
+}
+
+void ipu_plane_disable_vblank(struct ipu_plane *ipu_plane)
+{
+	ipu_plane->page_flip_event = NULL;
+	ipu_plane->newfb = NULL;
+}
+
 int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		       struct drm_display_mode *mode,
 		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
@@ -206,15 +260,31 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 
 	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
 
-	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
+	/* enable double-buffering */
+	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, true);
+
+	ret = set_base(ipu_plane, fb, -1, src_x, src_y);
 	if (ret < 0)
 		return ret;
 
+	/* cache width/height for subsequent pageflips */
+	ipu_plane->width = src_w;
+	ipu_plane->height = src_h;
+
+	/* set buffers ready */
+	ipu_idmac_select_buffer(ipu_plane->ipu_ch, 0);
+	ipu_idmac_select_buffer(ipu_plane->ipu_ch, 1);
+
 	return 0;
 }
 
 void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
 {
+	if (ipu_plane->irq) {
+		devm_free_irq(ipu_plane->base.dev->dev,
+			      ipu_plane->irq, ipu_plane);
+		ipu_plane->irq = 0;
+	}
 	if (!IS_ERR_OR_NULL(ipu_plane->dp))
 		ipu_dp_put(ipu_plane->dp);
 	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
@@ -250,6 +320,18 @@ int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
 		}
 	}
 
+	ipu_plane->irq = ipu_idmac_channel_irq(ipu_plane->ipu,
+					       ipu_plane->ipu_ch,
+					       IPU_IRQ_EOF);
+	ret = devm_request_irq(ipu_plane->base.dev->dev,
+			       ipu_plane->irq, ipu_plane_irq_handler, 0,
+			       "imx_drm", ipu_plane);
+	if (ret < 0) {
+		DRM_ERROR("irq request failed with %d\n", ret);
+		ipu_plane->irq = 0;
+		goto err_out;
+	}
+
 	return 0;
 err_out:
 	ipu_plane_put_resources(ipu_plane);
@@ -267,6 +349,12 @@ void ipu_plane_enable(struct ipu_plane *ipu_plane)
 		ipu_dp_enable_channel(ipu_plane->dp);
 
 	ipu_plane->enabled = true;
+
+	/*
+	 * we need to wait up to one frame time after enabling
+	 * to allow the IPU's FSU to settle on an IDMAC buffer.
+	 */
+	usleep_range(50000, 50001);
 }
 
 void ipu_plane_disable(struct ipu_plane *ipu_plane)
@@ -416,6 +504,43 @@ static int ipu_plane_set_property(struct drm_plane *plane,
 	return ret;
 }
 
+int ipu_plane_page_flip(struct drm_plane *plane,
+			struct drm_framebuffer *fb,
+			struct drm_pending_vblank_event *event,
+			uint32_t flags)
+{
+	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
+	int ret;
+
+	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
+
+	if (ipu_plane->newfb)
+		return -EBUSY;
+
+	if (ipu_plane->width > fb->width ||
+	    ipu_plane->height > fb->height ||
+	    ipu_plane->x > fb->width - ipu_plane->width ||
+	    ipu_plane->y > fb->height - ipu_plane->height) {
+		DRM_DEBUG_KMS("Invalid fb size %ux%u for plane %ux%u+%d+%d.\n",
+			      fb->width, fb->height,
+			      ipu_plane->width, ipu_plane->height,
+			      ipu_plane->x, ipu_plane->y);
+		return -ENOSPC;
+	}
+
+	ret = drm_vblank_get(ipu_plane->base.dev, ipu_plane->pipe);
+	if (ret) {
+		DRM_DEBUG_KMS("failed to acquire vblank counter\n");
+		return ret;
+	}
+
+	ipu_plane->newfb = fb;
+	ipu_plane->page_flip_event = event;
+	plane->fb = fb;
+
+	return 0;
+}
+
 static struct drm_plane_funcs ipu_plane_funcs = {
 	.update_plane	= ipu_update_plane,
 	.disable_plane	= ipu_disable_plane,
@@ -424,15 +549,16 @@ static struct drm_plane_funcs ipu_plane_funcs = {
 };
 
 int ipu_plane_init(struct ipu_plane *ipu_plane, struct drm_device *drm,
-		   struct ipu_soc *ipu, int dma, int dp,
+		   struct ipu_soc *ipu, int pipe, int dma, int dp,
 		   unsigned int possible_crtcs, bool priv)
 {
 	int ret;
 
-	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
-		      dma, dp, possible_crtcs);
+	DRM_DEBUG_KMS("channel %d, dp flow %d, pipe %d, possible_crtcs=0x%x\n",
+		      dma, dp, pipe, possible_crtcs);
 
 	ipu_plane->ipu = ipu;
+	ipu_plane->pipe = pipe;
 	ipu_plane->dma = dma;
 	ipu_plane->dp_flow = dp;
 
diff --git a/drivers/staging/imx-drm/ipuv3-plane.h b/drivers/staging/imx-drm/ipuv3-plane.h
index 1487a08..4d856e9 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.h
+++ b/drivers/staging/imx-drm/ipuv3-plane.h
@@ -15,6 +15,7 @@ struct ipu_dp;
 
 struct ipu_plane {
 	struct drm_plane	base;
+	int			pipe;
 
 	struct ipu_soc		*ipu;
 	struct ipuv3_channel	*ipu_ch;
@@ -24,6 +25,8 @@ struct ipu_plane {
 	int			dma;
 	int			dp_flow;
 
+	int			width;
+	int			height;
 	int			x;
 	int			y;
 
@@ -34,11 +37,15 @@ struct ipu_plane {
 	bool			colorkey_en;
 	u32			colorkey;
 
+	struct drm_pending_vblank_event *page_flip_event;
+	struct drm_framebuffer	*newfb;
+	int			irq;
+
 	bool			enabled;
 };
 
 int ipu_plane_init(struct ipu_plane *ipu_plane, struct drm_device *drm,
-		   struct ipu_soc *ipu, int dma, int dp,
+		   struct ipu_soc *ipu, int pipe, int dma, int dp,
 		   unsigned int possible_crtcs, bool priv);
 
 /* Init IDMAC, DMFC, DP */
@@ -49,14 +56,18 @@ int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
 		       uint32_t src_x, uint32_t src_y, uint32_t src_w,
 		       uint32_t src_h);
 
+int ipu_plane_page_flip(struct drm_plane *plane,
+			struct drm_framebuffer *fb,
+			struct drm_pending_vblank_event *event,
+			uint32_t flags);
+
+int ipu_plane_enable_vblank(struct ipu_plane *ipu_plane);
+void ipu_plane_disable_vblank(struct ipu_plane *ipu_plane);
+
 void ipu_plane_enable(struct ipu_plane *plane);
 void ipu_plane_disable(struct ipu_plane *plane);
-int ipu_plane_set_base(struct ipu_plane *plane, struct drm_framebuffer *fb,
-		       int x, int y);
 
 int ipu_plane_get_resources(struct ipu_plane *plane);
 void ipu_plane_put_resources(struct ipu_plane *plane);
 
-int ipu_plane_irq(struct ipu_plane *plane);
-
 #endif
-- 
1.7.9.5

_______________________________________________
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 52/72] imx-drm: Reset ipu unit pointers to NULL on errors

[Steve Longerbeam]

In the crtc and plane drivers it is possible the ipu unit pointers
could be left at error pointer values. Reset them to NULL on errors
to prevent this. Also ipu_put_resources() should reset the units to
NULL after releasing them.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c  |   11 +++++++++--
 drivers/staging/imx-drm/ipuv3-plane.c |   15 ++++++++++++---
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 423b004..3040f8e 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -375,13 +375,18 @@ dev_put:
 
 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
 {
-	if (!IS_ERR_OR_NULL(ipu_crtc->dc))
+	if (!IS_ERR_OR_NULL(ipu_crtc->dc)) {
 		ipu_dc_put(ipu_crtc->dc);
-	if (!IS_ERR_OR_NULL(ipu_crtc->di))
+		ipu_crtc->dc = NULL;
+	}
+	if (!IS_ERR_OR_NULL(ipu_crtc->di)) {
 		ipu_di_put(ipu_crtc->di);
+		ipu_crtc->di = NULL;
+	}
 	if (!IS_ERR_OR_NULL(ipu_crtc->ipu_dev)) {
 		module_put(ipu_crtc->ipu_dev->driver->owner);
 		put_device(ipu_crtc->ipu_dev);
+		ipu_crtc->ipu_dev = NULL;
 	}
 }
 
@@ -411,6 +416,7 @@ static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
 	ipu_crtc->di = ipu_di_get(ipu_crtc->ipu, di);
 	if (IS_ERR(ipu_crtc->di)) {
 		ret = PTR_ERR(ipu_crtc->di);
+		ipu_crtc->di = NULL;
 		goto err_out;
 	}
 
@@ -425,6 +431,7 @@ static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
 	ipu_crtc->dc = ipu_dc_get(ipu_crtc->ipu, ipu_crtc->ch->dc);
 	if (IS_ERR(ipu_crtc->dc)) {
 		ret = PTR_ERR(ipu_crtc->dc);
+		ipu_crtc->dc = NULL;
 		goto err_out;
 	}
 
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 76ac178..3a1ebfe 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -285,12 +285,18 @@ void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
 			      ipu_plane->irq, ipu_plane);
 		ipu_plane->irq = 0;
 	}
-	if (!IS_ERR_OR_NULL(ipu_plane->dp))
+	if (!IS_ERR_OR_NULL(ipu_plane->dp)) {
 		ipu_dp_put(ipu_plane->dp);
-	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
+		ipu_plane->dp = NULL;
+	}
+	if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) {
 		ipu_dmfc_put(ipu_plane->dmfc);
-	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
+		ipu_plane->dmfc = NULL;
+	}
+	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) {
 		ipu_idmac_put(ipu_plane->ipu_ch);
+		ipu_plane->ipu_ch = NULL;
+	}
 }
 
 int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
@@ -300,6 +306,7 @@ int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
 	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
 	if (IS_ERR(ipu_plane->ipu_ch)) {
 		ret = PTR_ERR(ipu_plane->ipu_ch);
+		ipu_plane->ipu_ch = NULL;
 		DRM_ERROR("failed to get idmac channel: %d\n", ret);
 		return ret;
 	}
@@ -307,6 +314,7 @@ int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
 	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
 	if (IS_ERR(ipu_plane->dmfc)) {
 		ret = PTR_ERR(ipu_plane->dmfc);
+		ipu_plane->dmfc = NULL;
 		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
 		goto err_out;
 	}
@@ -315,6 +323,7 @@ int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
 		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
 		if (IS_ERR(ipu_plane->dp)) {
 			ret = PTR_ERR(ipu_plane->dp);
+			ipu_plane->dp = NULL;
 			DRM_ERROR("failed to get dp flow: %d\n", ret);
 			goto err_out;
 		}
-- 
1.7.9.5

_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 53/72] drm: implement page flipping support for planes

[Steve Longerbeam]

Planes like crtcs would benefit from having page flip event support.
With planes page flip it is now possible to synchronize changing a
framebuffer used by an overlay (or even cursor) plane with vertical
sync events.

A page flip in the primary plane is equivalent to a crtc page flip,
which suggests this ioctl could deprecate the crtc page flip ioctl
at some point in the future.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
---
 drivers/gpu/drm/drm_crtc.c  |  241 +++++++++++++++++++++++++------------------
 drivers/gpu/drm/drm_ioctl.c |    1 +
 include/drm/drm_crtc.h      |   11 ++
 include/uapi/drm/drm.h      |    1 +
 include/uapi/drm/drm_mode.h |    8 ++
 5 files changed, 164 insertions(+), 98 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index e79c8d3..53b5f87 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2445,6 +2445,142 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
 				 plane_req->src_w, plane_req->src_h);
 }
 
+int drm_mode_plane_page_flip_ioctl(struct drm_device *dev,
+				   void *data, struct drm_file *file_priv)
+{
+	struct drm_mode_plane_page_flip *page_flip = data;
+	struct drm_plane *plane;
+	struct drm_crtc *crtc;
+	struct drm_framebuffer *fb = NULL;
+	struct drm_pending_vblank_event *e = NULL;
+	unsigned long flags;
+	bool is_primary;
+	int ret;
+
+	if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
+	    page_flip->reserved != 0)
+		return -EINVAL;
+
+	if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) &&
+	    !dev->mode_config.async_page_flip)
+		return -EINVAL;
+
+	plane = drm_plane_find(dev, page_flip->plane_id);
+	if (!plane)
+		return -ENOENT;
+
+	is_primary = (plane->type == DRM_PLANE_TYPE_PRIMARY);
+
+	drm_modeset_lock_all(dev);
+
+	if (plane->crtc == NULL || plane->fb == NULL) {
+		/* The crtc and/or framebuffer is currently unbound,
+		 * presumably due to a hotplug event, that userspace
+		 * has not yet discovered.
+		 */
+		ret = -EBUSY;
+		goto out;
+	}
+	crtc = plane->crtc;
+
+	if ((is_primary && crtc->funcs->page_flip == NULL) ||
+	    plane->funcs->page_flip == NULL) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
+	if (!fb) {
+		ret = -ENOENT;
+		goto out;
+	}
+
+	/*
+	 * If this is the primary plane (equivalent to a crtc page flip),
+	 * verify that the fb is valid for the bound crtc's viewport.
+	 * For overlay or cursor planes, the plane's page_flip op should
+	 * check that the fb is valid.
+	 */
+	if (is_primary) {
+		ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y,
+					      &crtc->mode, fb);
+		if (ret)
+			goto out;
+	}
+
+	if (plane->fb->pixel_format != fb->pixel_format) {
+		DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
+		ret = -ENOMEM;
+		spin_lock_irqsave(&dev->event_lock, flags);
+		if (file_priv->event_space < sizeof(e->event)) {
+			spin_unlock_irqrestore(&dev->event_lock, flags);
+			goto out;
+		}
+		file_priv->event_space -= sizeof(e->event);
+		spin_unlock_irqrestore(&dev->event_lock, flags);
+
+		e = kzalloc(sizeof(*e), GFP_KERNEL);
+		if (e == NULL) {
+			spin_lock_irqsave(&dev->event_lock, flags);
+			file_priv->event_space += sizeof(e->event);
+			spin_unlock_irqrestore(&dev->event_lock, flags);
+			goto out;
+		}
+
+		e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
+		e->event.base.length = sizeof(e->event);
+		e->event.user_data = page_flip->user_data;
+		e->base.event = &e->event.base;
+		e->base.file_priv = file_priv;
+		e->base.destroy =
+			(void (*) (struct drm_pending_event *)) kfree;
+	}
+
+	plane->old_fb = plane->fb;
+
+	/* for now use crtc page_flip op, if this is the primary plane */
+	if (is_primary)
+		ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags);
+	else
+		ret = plane->funcs->page_flip(plane, fb, e, page_flip->flags);
+
+	if (ret) {
+		if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
+			spin_lock_irqsave(&dev->event_lock, flags);
+			file_priv->event_space += sizeof(e->event);
+			spin_unlock_irqrestore(&dev->event_lock, flags);
+			kfree(e);
+		}
+		/* Keep the old fb, don't unref it. */
+		plane->old_fb = NULL;
+	} else {
+		/*
+		 * Warn if the driver hasn't properly updated the plane->fb
+		 * field to reflect that the new framebuffer is now used.
+		 * Failing to do so will screw with the reference counting
+		 * on framebuffers.
+		 */
+		WARN_ON(plane->fb != fb);
+		/* Unref only the old framebuffer. */
+		fb = NULL;
+	}
+
+out:
+	if (fb)
+		drm_framebuffer_unreference(fb);
+	if (plane->old_fb)
+		drm_framebuffer_unreference(plane->old_fb);
+	plane->old_fb = NULL;
+	drm_modeset_unlock_all(dev);
+
+	return ret;
+}
+
 /**
  * drm_mode_set_config_internal - helper to call ->set_config
  * @set: modeset config to set
@@ -4582,111 +4718,20 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
 			     void *data, struct drm_file *file_priv)
 {
 	struct drm_mode_crtc_page_flip *page_flip = data;
+	struct drm_mode_plane_page_flip primary_pf = {0};
 	struct drm_crtc *crtc;
-	struct drm_framebuffer *fb = NULL;
-	struct drm_pending_vblank_event *e = NULL;
-	unsigned long flags;
-	int ret = -EINVAL;
-
-	if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
-	    page_flip->reserved != 0)
-		return -EINVAL;
-
-	if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
-		return -EINVAL;
 
 	crtc = drm_crtc_find(dev, page_flip->crtc_id);
 	if (!crtc)
 		return -ENOENT;
 
-	drm_modeset_lock_crtc(crtc);
-	if (crtc->primary->fb == NULL) {
-		/* The framebuffer is currently unbound, presumably
-		 * due to a hotplug event, that userspace has not
-		 * yet discovered.
-		 */
-		ret = -EBUSY;
-		goto out;
-	}
-
-	if (crtc->funcs->page_flip == NULL)
-		goto out;
-
-	fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
-	if (!fb) {
-		ret = -ENOENT;
-		goto out;
-	}
-
-	ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y, &crtc->mode, fb);
-	if (ret)
-		goto out;
-
-	if (crtc->primary->fb->pixel_format != fb->pixel_format) {
-		DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
-		ret = -EINVAL;
-		goto out;
-	}
-
-	if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
-		ret = -ENOMEM;
-		spin_lock_irqsave(&dev->event_lock, flags);
-		if (file_priv->event_space < sizeof e->event) {
-			spin_unlock_irqrestore(&dev->event_lock, flags);
-			goto out;
-		}
-		file_priv->event_space -= sizeof e->event;
-		spin_unlock_irqrestore(&dev->event_lock, flags);
-
-		e = kzalloc(sizeof *e, GFP_KERNEL);
-		if (e == NULL) {
-			spin_lock_irqsave(&dev->event_lock, flags);
-			file_priv->event_space += sizeof e->event;
-			spin_unlock_irqrestore(&dev->event_lock, flags);
-			goto out;
-		}
-
-		e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
-		e->event.base.length = sizeof e->event;
-		e->event.user_data = page_flip->user_data;
-		e->base.event = &e->event.base;
-		e->base.file_priv = file_priv;
-		e->base.destroy =
-			(void (*) (struct drm_pending_event *)) kfree;
-	}
-
-	crtc->primary->old_fb = crtc->primary->fb;
-	ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags);
-	if (ret) {
-		if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
-			spin_lock_irqsave(&dev->event_lock, flags);
-			file_priv->event_space += sizeof e->event;
-			spin_unlock_irqrestore(&dev->event_lock, flags);
-			kfree(e);
-		}
-		/* Keep the old fb, don't unref it. */
-		crtc->primary->old_fb = NULL;
-	} else {
-		/*
-		 * Warn if the driver hasn't properly updated the crtc->fb
-		 * field to reflect that the new framebuffer is now used.
-		 * Failing to do so will screw with the reference counting
-		 * on framebuffers.
-		 */
-		WARN_ON(crtc->primary->fb != fb);
-		/* Unref only the old framebuffer. */
-		fb = NULL;
-	}
+	primary_pf.plane_id  = crtc->primary->base.id;
+	primary_pf.fb_id     = page_flip->fb_id;
+	primary_pf.flags     = page_flip->flags;
+	primary_pf.user_data = page_flip->user_data;
 
-out:
-	if (fb)
-		drm_framebuffer_unreference(fb);
-	if (crtc->primary->old_fb)
-		drm_framebuffer_unreference(crtc->primary->old_fb);
-	crtc->primary->old_fb = NULL;
-	drm_modeset_unlock_crtc(crtc);
-
-	return ret;
+	return drm_mode_plane_page_flip_ioctl(dev, (void *)&primary_pf,
+					      file_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 00587a1..2e60ee3 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -620,6 +620,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
 	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
 	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_PLANE_PAGE_FLIP, drm_mode_plane_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
 };
 
 #define DRM_CORE_IOCTL_COUNT	ARRAY_SIZE( drm_ioctls )
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c40070a..26d859b 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -571,6 +571,7 @@ struct drm_connector {
  * @disable_plane: shut down the plane
  * @destroy: clean up plane resources
  * @set_property: called when a property is changed
+ * @page_flip: initiate a page flip
  */
 struct drm_plane_funcs {
 	int (*update_plane)(struct drm_plane *plane,
@@ -585,6 +586,14 @@ struct drm_plane_funcs {
 
 	int (*set_property)(struct drm_plane *plane,
 			    struct drm_property *property, uint64_t val);
+
+	/*
+	 * See comment at drm_crtc_funcs.page_flip
+	 */
+	int (*page_flip)(struct drm_plane *plane,
+			 struct drm_framebuffer *fb,
+			 struct drm_pending_vblank_event *event,
+			 uint32_t flags);
 };
 
 enum drm_plane_type {
@@ -1105,6 +1114,8 @@ extern bool drm_detect_monitor_audio(struct edid *edid);
 extern bool drm_rgb_quant_range_selectable(struct edid *edid);
 extern int drm_mode_page_flip_ioctl(struct drm_device *dev,
 				    void *data, struct drm_file *file_priv);
+extern int drm_mode_plane_page_flip_ioctl(struct drm_device *dev,
+				    void *data, struct drm_file *file_priv);
 extern int drm_add_modes_noedid(struct drm_connector *connector,
 				int hdisplay, int vdisplay);
 extern void drm_set_preferred_mode(struct drm_connector *connector,
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index b0b8556..48d9da6 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -777,6 +777,7 @@ struct drm_prime_handle {
 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES	DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY	DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
 #define DRM_IOCTL_MODE_CURSOR2		DRM_IOWR(0xBB, struct drm_mode_cursor2)
+#define DRM_IOCTL_MODE_PLANE_PAGE_FLIP	DRM_IOWR(0xBC, struct drm_mode_plane_page_flip)
 
 /**
  * Device specific ioctls should only be in their respective headers
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a0db2d4a..8d98cd0 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -488,6 +488,14 @@ struct drm_mode_crtc_page_flip {
 	__u64 user_data;
 };
 
+struct drm_mode_plane_page_flip {
+	__u32 plane_id;
+	__u32 fb_id;
+	__u32 flags;
+	__u32 reserved;
+	__u64 user_data;
+};
+
 /* create a dumb scanout buffer */
 struct drm_mode_create_dumb {
 	uint32_t height;
-- 
1.7.9.5

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[PATCH 54/72] imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs

[Steve Longerbeam]

Assign ipu_plane_page_flip to new drm_plane_funcs->page_flip method.
This allows page flip operation in both the primary and overlay planes.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 3a1ebfe..3293e84 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -555,6 +555,7 @@ static struct drm_plane_funcs ipu_plane_funcs = {
 	.disable_plane	= ipu_disable_plane,
 	.destroy	= ipu_plane_destroy,
 	.set_property	= ipu_plane_set_property,
+	.page_flip	= ipu_plane_page_flip,
 };
 
 int ipu_plane_init(struct ipu_plane *ipu_plane, struct drm_device *drm,
-- 
1.7.9.5

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[PATCH 55/72] imx-drm: Implement DRM gamma set

[Steve Longerbeam]

Implement the DRM gamma set API. This API expects that the adapter
will use a gamma-corrected CLUT, but the CLUT on i.MX6 is insufficient
for that purpose.

But the i.MX6 does support gamma correction via a set of registers
that define a piecewise linear approximation to a luminance
gamma correction curve, which is what this implementation uses.

The input gamma-corrected luminance values to ipu_drm_gamma_set() must
be in a specific format defined in the i.MX6 reference manual.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |    3 +-
 drivers/staging/imx-drm/imx-drm.h      |    2 +
 drivers/staging/imx-drm/ipuv3-crtc.c   |   85 ++++++++++++++++++++++++++++++++
 drivers/staging/imx-drm/ipuv3-plane.c  |   10 ++++
 drivers/staging/imx-drm/ipuv3-plane.h  |    3 ++
 5 files changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index e0178d6..084ed53 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -387,7 +387,8 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
 
 	*new_crtc = imx_drm_crtc;
 
-	ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
+	ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc,
+					   DRM_IMX_GAMMA_SIZE);
 	if (ret)
 		goto err_register;
 
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index ec084fe..bf6b06b 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -52,4 +52,6 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
 void imx_drm_connector_destroy(struct drm_connector *connector);
 void imx_drm_encoder_destroy(struct drm_encoder *encoder);
 
+#define DRM_IMX_GAMMA_SIZE 16
+
 #endif /* _IMX_DRM_H_ */
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 3040f8e..4f2ba40 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -171,10 +171,95 @@ static int ipu_crtc_page_flip(struct drm_crtc *crtc,
 	return ipu_plane_page_flip(crtc->primary, fb, event, page_flip_flags);
 }
 
+/*
+ * Normally the DRM Gamma API is used to program a color LUT that contains
+ * gamma-corrected pixel values for red, green, and blue input pixel values
+ * (normally in the range 0 to 255).
+ *
+ * However the i.MX6 LUT is only 256 entries, so it only supports 8 bpp
+ * indexed pixel format. Therefore if the i.MX6 LUT were used to implement
+ * gamma correction, th DRM framebuffer would have to use 8 bpp indexed pixel
+ * format which is insufficient for most use cases. To support a gamma
+ * correcting LUT with full RGB24 or YUV444 pixel formats, there would have
+ * to be 3 separate 256-entry LUTs for each color component.
+ *
+ * But the i.MX6 does support gamma correction via a set of registers that
+ * define a piecewise linear approximation to a luminance gamma correction
+ * curve. This function uses this approach.
+ *
+ * The input pixel values to this function must be in a specific format
+ * according to the i.MX6 reference manual (see Table 37-28 in the
+ * Rev. 1 TRM, dated 04/2013). This info is reprinted here:
+ *
+ * "The required Gamma correction slope for a specific display should be
+ * provided by the display manufacture. This information can be provided
+ * in various forms, as graph or formula. The gamma correction input pixel
+ * level (Gin) should be normalized to a maximum of 383. The gamma correction
+ * output pixel level (Gout) should be normalized to a maximum of 255. Then
+ * the following data should be collected:
+ *
+ * Table 37-28. Gamma correction values
+ *   Gin   Gout
+ *   ---   -----
+ *     0   Gout0
+ *     2   Gout1
+ *     4   Gout2
+ *     8   Gout3
+ *    16   Gout4
+ *    32   Gout5
+ *    64   Gout6
+ *    96   Gout7
+ *   128   Gout8
+ *   160   Gout9
+ *   192   Gout10
+ *   224   Gout11
+ *   256   Gout12
+ *   288   Gout13
+ *   320   Gout14
+ *   352   Gout15"
+ *
+ *
+ * The 16 Gout values must be placed in the input lum[] array. The green
+ * and blue input arrays are ignored.
+ *
+ * The gamma register values are then computed according to Table 37-29
+ * in the Rev. 1 TRM.
+ */
+static void ipu_crtc_gamma_set(struct drm_crtc *crtc,
+			       u16 *lum, u16 *g_unused, u16 *b_unused,
+			       uint32_t start, uint32_t size)
+{
+	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+	u32 m[DRM_IMX_GAMMA_SIZE], b[DRM_IMX_GAMMA_SIZE];
+	int i;
+
+	if (size != DRM_IMX_GAMMA_SIZE)
+		return;
+
+	for (i = 0; i < size; i++) {
+		if (i == 0) {
+			b[0] = lum[0];
+			m[0] = 16 * (lum[1] - lum[0]);
+		} else if (i == 15) {
+			b[15] = lum[15];
+			m[15] = 255 - lum[15];
+		} else if (i < 5) {
+			b[i] = 2 * lum[i] - lum[i+1];
+			m[i] = (lum[i+1] - lum[i]) << (5 - i);
+		} else {
+			b[i] = lum[i];
+			m[i] = lum[i+1] - lum[i];
+		}
+	}
+
+	ipu_plane_gamma_set(&ipu_crtc->plane[0], true, m, b);
+}
+
 static const struct drm_crtc_funcs ipu_crtc_funcs = {
 	.set_config = drm_crtc_helper_set_config,
 	.destroy = drm_crtc_cleanup,
 	.page_flip = ipu_crtc_page_flip,
+	.gamma_set = ipu_crtc_gamma_set,
 };
 
 static int ipu_crtc_mode_set(struct drm_crtc *crtc,
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 3293e84..2912aa6 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -380,6 +380,16 @@ void ipu_plane_disable(struct ipu_plane *ipu_plane)
 		ipu_dp_disable(ipu_plane->dp);
 }
 
+int ipu_plane_gamma_set(struct ipu_plane *ipu_plane,
+			bool enable, u32 *m, u32 *b)
+{
+	if (!ipu_plane->dp)
+		return -EINVAL;
+
+	return ipu_dp_set_gamma_correction(ipu_plane->dp, enable, m, b);
+}
+
+
 /*
  * drm_plane API
  */
diff --git a/drivers/staging/imx-drm/ipuv3-plane.h b/drivers/staging/imx-drm/ipuv3-plane.h
index 4d856e9..912902a 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.h
+++ b/drivers/staging/imx-drm/ipuv3-plane.h
@@ -70,4 +70,7 @@ void ipu_plane_disable(struct ipu_plane *plane);
 int ipu_plane_get_resources(struct ipu_plane *plane);
 void ipu_plane_put_resources(struct ipu_plane *plane);
 
+int ipu_plane_gamma_set(struct ipu_plane *ipu_plane,
+			bool enable, u32 *m, u32 *b);
+
 #endif
-- 
1.7.9.5

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[PATCH 56/72] imx-drm: Implement custom ioctl to set gamma

[Steve Longerbeam]

Implement i.MX specific ioctl to set gamma directly using slope and
y-intercept values that define the piecewise linear gamma correction
curve.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |   40 +++++++++++++++++++++++++++++++-
 drivers/staging/imx-drm/imx-drm.h      |    3 +--
 drivers/staging/imx-drm/ipuv3-crtc.c   |    9 +++++++
 include/uapi/drm/imx_drm.h             |   30 ++++++++++++++++++++++++
 4 files changed, 79 insertions(+), 3 deletions(-)
 create mode 100644 include/uapi/drm/imx_drm.h

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 084ed53..4c85fd3 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -24,6 +24,7 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_fb_cma_helper.h>
+#include <drm/imx_drm.h>
 
 #include "imx-drm.h"
 
@@ -122,6 +123,18 @@ static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc)
 	return NULL;
 }
 
+static struct imx_drm_crtc *imx_drm_find_crtc_by_id(struct drm_device *drm,
+						    u32 crtc_id)
+{
+	struct drm_crtc *crtc;
+
+	crtc = drm_crtc_find(drm, crtc_id);
+	if (!crtc)
+		return NULL;
+
+	return imx_drm_find_crtc(crtc);
+}
+
 int imx_drm_panel_format_pins(struct drm_encoder *encoder,
 		u32 interface_pix_fmt, int hsync_pin, int vsync_pin)
 {
@@ -537,8 +550,33 @@ int imx_drm_encoder_get_mux_id(struct device_node *node,
 }
 EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
 
+static int drm_imx_set_gamma_ioctl(struct drm_device *drm, void *data,
+				   struct drm_file *file_priv)
+{
+	struct drm_imx_gamma *g = data;
+	struct imx_drm_crtc_helper_funcs *helper;
+	struct imx_drm_crtc *imx_crtc;
+	int ret = -EINVAL;
+
+	if (!drm_core_check_feature(drm, DRIVER_MODESET))
+		return -ENODEV;
+
+	drm_modeset_lock_all(drm);
+
+	imx_crtc = imx_drm_find_crtc_by_id(drm, g->crtc_id);
+	if (!imx_crtc)
+		goto out_unlock;
+
+	helper = &imx_crtc->imx_drm_helper_funcs;
+	ret = helper->gamma_set(imx_crtc->crtc, g->enable, g->m, g->b);
+
+out_unlock:
+	drm_modeset_unlock_all(drm);
+	return ret;
+}
+
 static const struct drm_ioctl_desc imx_drm_ioctls[] = {
-	/* none so far */
+	DRM_IOCTL_DEF_DRV(IMX_SET_GAMMA, drm_imx_set_gamma_ioctl, DRM_AUTH),
 };
 
 static struct drm_driver imx_drm_driver = {
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index bf6b06b..0bb4735 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -21,6 +21,7 @@ struct imx_drm_crtc_helper_funcs {
 	void (*disable_vblank)(struct drm_crtc *crtc, int pipe);
 	int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 encoder_type,
 			u32 pix_fmt, int hsync_pin, int vsync_pin);
+	int (*gamma_set)(struct drm_crtc *crtc, bool enable, u32 *m, u32 *b);
 	const struct drm_crtc_helper_funcs *crtc_helper_funcs;
 	const struct drm_crtc_funcs *crtc_funcs;
 };
@@ -52,6 +53,4 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
 void imx_drm_connector_destroy(struct drm_connector *connector);
 void imx_drm_encoder_destroy(struct drm_encoder *encoder);
 
-#define DRM_IMX_GAMMA_SIZE 16
-
 #endif /* _IMX_DRM_H_ */
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 4f2ba40..8d7c998 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -29,6 +29,7 @@
 #include <linux/errno.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_fb_cma_helper.h>
+#include <drm/imx_drm.h>
 
 #include <video/imx-ipu-v3.h>
 #include "imx-drm.h"
@@ -405,10 +406,18 @@ static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
 	return 0;
 }
 
+static int ipu_gamma_set(struct drm_crtc *crtc, bool enable, u32 *m, u32 *b)
+{
+	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+	return ipu_plane_gamma_set(&ipu_crtc->plane[0], true, m, b);
+}
+
 static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
 	.enable_vblank = ipu_enable_vblank,
 	.disable_vblank = ipu_disable_vblank,
 	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
+	.gamma_set = ipu_gamma_set,
 	.crtc_funcs = &ipu_crtc_funcs,
 	.crtc_helper_funcs = &ipu_helper_funcs,
 };
diff --git a/include/uapi/drm/imx_drm.h b/include/uapi/drm/imx_drm.h
new file mode 100644
index 0000000..b0a03d6
--- /dev/null
+++ b/include/uapi/drm/imx_drm.h
@@ -0,0 +1,30 @@
+/*
+ * include/uapi/drm/imx_drm.h
+ *
+ * Copyright (C) 2013-2014 Mentor Graphics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __IMX_DRM_H__
+#define __IMX_DRM_H__
+
+#include <drm/drm.h>
+
+#define DRM_IMX_GAMMA_SIZE         16
+struct drm_imx_gamma {
+	bool     enable;
+	uint32_t crtc_id;
+	uint32_t m[DRM_IMX_GAMMA_SIZE];
+	uint32_t b[DRM_IMX_GAMMA_SIZE];
+};
+
+#define DRM_IMX_SET_GAMMA    0x00
+
+#define DRM_IOCTL_IMX_SET_GAMMA                                         \
+	DRM_IOW(DRM_COMMAND_BASE + DRM_IMX_SET_GAMMA, struct drm_imx_gamma)
+
+#endif /* __IMX_DRM_H__ */
-- 
1.7.9.5

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[PATCH 57/72] imx-drm: Add support for interface pixel maps

[Steve Longerbeam]

Adds the framework that allows encoder/connector drivers to create
a new interface pixel mapping passed to imx_drm_panel_format(). The
crtc driver will then pass this pointer on to ipu_dc_init_sync() which
sets up the new mapping in the DC.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c     |   19 ++++++++++++++-----
 drivers/staging/imx-drm/imx-drm.h          |   12 +++++++++---
 drivers/staging/imx-drm/imx-hdmi.c         |    3 +--
 drivers/staging/imx-drm/imx-ldb.c          |    2 +-
 drivers/staging/imx-drm/imx-tve.c          |    5 ++---
 drivers/staging/imx-drm/ipuv3-crtc.c       |   11 ++++++++---
 drivers/staging/imx-drm/ipuv3-plane.c      |    2 +-
 drivers/staging/imx-drm/parallel-display.c |    2 +-
 8 files changed, 37 insertions(+), 19 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 4c85fd3..b31d291 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -136,7 +136,9 @@ static struct imx_drm_crtc *imx_drm_find_crtc_by_id(struct drm_device *drm,
 }
 
 int imx_drm_panel_format_pins(struct drm_encoder *encoder,
-		u32 interface_pix_fmt, int hsync_pin, int vsync_pin)
+			      u32 interface_pix_fmt,
+			      struct ipu_dc_if_map *interface_pix_map,
+			      int hsync_pin, int vsync_pin)
 {
 	struct imx_drm_crtc_helper_funcs *helper;
 	struct imx_drm_crtc *imx_crtc;
@@ -148,15 +150,22 @@ int imx_drm_panel_format_pins(struct drm_encoder *encoder,
 	helper = &imx_crtc->imx_drm_helper_funcs;
 	if (helper->set_interface_pix_fmt)
 		return helper->set_interface_pix_fmt(encoder->crtc,
-				encoder->encoder_type, interface_pix_fmt,
-				hsync_pin, vsync_pin);
+						     encoder->encoder_type,
+						     interface_pix_fmt,
+						     interface_pix_map,
+						     hsync_pin, vsync_pin);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins);
 
-int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt)
+int imx_drm_panel_format(struct drm_encoder *encoder,
+			 u32 interface_pix_fmt,
+			 struct ipu_dc_if_map *interface_pix_map)
 {
-	return imx_drm_panel_format_pins(encoder, interface_pix_fmt, 2, 3);
+	return imx_drm_panel_format_pins(encoder,
+					 interface_pix_fmt,
+					 interface_pix_map,
+					 2, 3);
 }
 EXPORT_SYMBOL_GPL(imx_drm_panel_format);
 
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index 0bb4735..24b889a 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -1,6 +1,8 @@
 #ifndef _IMX_DRM_H_
 #define _IMX_DRM_H_
 
+#include <video/imx-ipu-v3.h>
+
 struct device_node;
 struct drm_crtc;
 struct drm_connector;
@@ -20,7 +22,8 @@ struct imx_drm_crtc_helper_funcs {
 	int (*enable_vblank)(struct drm_crtc *crtc, int pipe);
 	void (*disable_vblank)(struct drm_crtc *crtc, int pipe);
 	int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 encoder_type,
-			u32 pix_fmt, int hsync_pin, int vsync_pin);
+				     u32 pix_fmt, struct ipu_dc_if_map *pix_map,
+				     int hsync_pin, int vsync_pin);
 	int (*gamma_set)(struct drm_crtc *crtc, bool enable, u32 *m, u32 *b);
 	const struct drm_crtc_helper_funcs *crtc_helper_funcs;
 	const struct drm_crtc_funcs *crtc_funcs;
@@ -41,9 +44,12 @@ void imx_drm_mode_config_init(struct drm_device *drm);
 struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
 
 int imx_drm_panel_format_pins(struct drm_encoder *encoder,
-		u32 interface_pix_fmt, int hsync_pin, int vsync_pin);
+			      u32 interface_pix_fmt,
+			      struct ipu_dc_if_map *interface_pix_map,
+			      int hsync_pin, int vsync_pin);
 int imx_drm_panel_format(struct drm_encoder *encoder,
-		u32 interface_pix_fmt);
+			 u32 interface_pix_fmt,
+			 struct ipu_dc_if_map *interface_pix_map);
 
 int imx_drm_encoder_get_mux_id(struct device_node *node,
 		struct drm_encoder *encoder);
diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index db3906f..4ef1c0a 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -27,7 +27,6 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_edid.h>
 #include <drm/drm_encoder_slave.h>
-#include <video/imx-ipu-v3.h>
 
 #include "imx-hdmi.h"
 #include "imx-drm.h"
@@ -1455,7 +1454,7 @@ static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
 	struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
 
 	imx_hdmi_poweroff(hdmi);
-	imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
+	imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24, NULL);
 }
 
 static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 6c16cf2..53d9d82 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -293,7 +293,7 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
 		pixel_fmt = V4L2_PIX_FMT_RGB24;
 	}
 
-	imx_drm_panel_format(encoder, pixel_fmt);
+	imx_drm_panel_format(encoder, pixel_fmt, NULL);
 }
 
 static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
diff --git a/drivers/staging/imx-drm/imx-tve.c b/drivers/staging/imx-drm/imx-tve.c
index 42c651b..49feb91 100644
--- a/drivers/staging/imx-drm/imx-tve.c
+++ b/drivers/staging/imx-drm/imx-tve.c
@@ -30,7 +30,6 @@
 #include <drm/drmP.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_crtc_helper.h>
-#include <video/imx-ipu-v3.h>
 
 #include "imx-drm.h"
 
@@ -302,11 +301,11 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
 
 	switch (tve->mode) {
 	case TVE_MODE_VGA:
-		imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
+		imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, NULL,
 				tve->hsync_pin, tve->vsync_pin);
 		break;
 	case TVE_MODE_TVOUT:
-		imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
+		imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444, NULL);
 		break;
 	}
 }
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 8d7c998..bd158d6 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -31,7 +31,6 @@
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/imx_drm.h>
 
-#include <video/imx-ipu-v3.h>
 #include "imx-drm.h"
 #include "ipuv3-plane.h"
 
@@ -93,6 +92,8 @@ struct ipu_crtc {
 	int			enabled;
 
 	u32			interface_pix_fmt;
+	struct ipu_dc_if_map    *interface_pix_map;
+
 	unsigned long		di_clkflags;
 	int			di_hsync_pin;
 	int			di_vsync_pin;
@@ -272,6 +273,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 	int ret;
 	struct ipu_di_signal_cfg sig_cfg = {};
+	struct ipu_dc_if_map *out_pixel_map;
 	u32 out_pixel_fmt;
 
 	dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
@@ -280,6 +282,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 			mode->vdisplay);
 
 	out_pixel_fmt = ipu_crtc->interface_pix_fmt;
+	out_pixel_map = ipu_crtc->interface_pix_map;
 
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 		sig_cfg.interlaced = 1;
@@ -309,7 +312,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 	sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
 
 	ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
-			out_pixel_fmt, NULL, mode->hdisplay);
+			out_pixel_fmt, out_pixel_map, mode->hdisplay);
 	if (ret) {
 		dev_err(ipu_crtc->dev,
 				"initializing display controller failed with %d\n",
@@ -382,11 +385,13 @@ static void ipu_disable_vblank(struct drm_crtc *crtc, int pipe)
 }
 
 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
-		u32 pixfmt, int hsync_pin, int vsync_pin)
+				     u32 pixfmt, struct ipu_dc_if_map *pixmap,
+				     int hsync_pin, int vsync_pin)
 {
 	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
 
 	ipu_crtc->interface_pix_fmt = pixfmt;
+	ipu_crtc->interface_pix_map = pixmap;
 	ipu_crtc->di_hsync_pin = hsync_pin;
 	ipu_crtc->di_vsync_pin = vsync_pin;
 
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 2912aa6..61d47e9 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -17,7 +17,7 @@
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 
-#include "video/imx-ipu-v3.h"
+#include "imx-drm.h"
 #include "ipuv3-plane.h"
 
 #define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)
diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index 49f8308..667a9b3 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -123,7 +123,7 @@ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
 
-	imx_drm_panel_format(encoder, imxpd->interface_pix_fmt);
+	imx_drm_panel_format(encoder, imxpd->interface_pix_fmt, NULL);
 }
 
 static void imx_pd_encoder_commit(struct drm_encoder *encoder)
-- 
1.7.9.5

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[PATCH 58/72] imx-drm: parallel-display: Add interface-pix-map DT property

[Steve Longerbeam]

Define a new devicetree property "interface-pix-map" for use by
i.MX DRM display drivers. This property defines a DI interface
pixel bus mapping. Implement the parsing of this property in the
parallel display driver, and pass on the mapping to
imx_drm_panel_format().

See Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
for a complete description of this property.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 .../bindings/staging/imx-drm/fsl-imx-drm.txt       |   43 ++++++++++++++++++--
 drivers/staging/imx-drm/parallel-display.c         |   25 +++++++++++-
 2 files changed, 63 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index e75f0e5..a9146f8 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -59,9 +59,26 @@ Parallel display support
 Required properties:
 - compatible: Should be "fsl,imx-parallel-display"
 Optional properties:
-- interface_pix_fmt: How this display is connected to the
-  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
-  and "lvds666".
+- interface-pix-map: Defines a pixel mapping onto the 24-bit IPU
+  Display Interface bus to the display. Internally the IPU represents
+  pixels in either RGB24 or YUV444 format. This property tells the IPU how
+  to map those RGB24 or YUV444 pixels onto the display interface bus.
+  The data format is as follows:
+
+  interface-pix-map = <c0-dest-msb c0-src-mask c1-dest-msb c1-src-mask
+  		       c2-dest-msb c2-src-mask>;
+
+  where:
+	c0, c1, c2: are the color components (c0 = B/V, c1 = G/U, c2 = R/Y)
+	src-mask: is the mask of component source bits to be forwarded
+	          to the DI bus
+	dest-msb: defines where to place those component bits on the
+	          24-bit DI bus, represented as the MSBit on the bus.
+
+- interface-pix-fmt: A name given to the pixel format sent to the display.
+  The following are names with pre-defined pixel mappings that do not
+  require an explicit interface-pix-map property: "rgb24", "rgb565", "rgb666"
+
 - edid: verbatim EDID data block describing attached display.
 - ddc: phandle describing the i2c bus handling the display data
   channel
@@ -81,3 +98,23 @@ display@di0 {
 		};
 	};
 };
+
+Pixel map examples:
+
+This example defines a new format named "bgr565" using a pixel map:
+
+display@di0 {
+	compatible = "fsl,imx-parallel-display";
+	edid = [edid-data];
+	interface-pix-fmt = "bgr565";
+	interface-pix-map = <15 0xf8 10 0xfc 4 0xf8>;
+};
+
+This example defines an unnamed format where an rgb666 format is shifted
+up by 6 bits on the DI bus:
+
+display@di0 {
+	compatible = "fsl,imx-parallel-display";
+	edid = [edid-data];
+	interface-pix-map = <11 0xfc 17 0xfc 23 0xfc>;
+};
diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index 667a9b3..e0b0b56 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -26,6 +26,7 @@
 #include <drm/drm_panel.h>
 #include <linux/videodev2.h>
 #include <video/of_display_timing.h>
+#include <video/imx-ipu-v3.h>
 
 #include "imx-drm.h"
 
@@ -39,6 +40,7 @@ struct imx_parallel_display {
 	void *edid;
 	int edid_len;
 	u32 interface_pix_fmt;
+	struct ipu_dc_if_map *interface_map;
 	int mode_valid;
 	struct drm_display_mode mode;
 	struct drm_panel *panel;
@@ -123,7 +125,8 @@ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
 
-	imx_drm_panel_format(encoder, imxpd->interface_pix_fmt, NULL);
+	imx_drm_panel_format(encoder, imxpd->interface_pix_fmt,
+			     imxpd->interface_map);
 }
 
 static void imx_pd_encoder_commit(struct drm_encoder *encoder)
@@ -208,8 +211,9 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 	struct device_node *panel_node;
 	const u8 *edidp;
 	struct imx_parallel_display *imxpd;
-	int ret;
+	struct ipu_dc_if_map interface_map;
 	const char *fmt;
+	int ret;
 
 	imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL);
 	if (!imxpd)
@@ -239,6 +243,23 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 		}
 	}
 
+	ret = of_property_read_u32_array(np, "interface-pix-map",
+					 (u32 *)&interface_map,
+					 sizeof(interface_map) / sizeof(u32));
+	if (!ret) {
+		imxpd->interface_map =
+			devm_kmalloc(dev, sizeof(imxpd->interface_map),
+				     GFP_KERNEL);
+		if (!imxpd->interface_map)
+			return -ENOMEM;
+		*imxpd->interface_map = interface_map;
+	}
+
+	if (!imxpd->interface_pix_fmt && !imxpd->interface_map) {
+		dev_err(imxpd->dev, "No interface pix fmt defined!\n");
+		return -EINVAL;
+	}
+
 	panel_node = of_parse_phandle(np, "fsl,panel", 0);
 	if (panel_node)
 		imxpd->panel = of_drm_find_panel(panel_node);
-- 
1.7.9.5

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[PATCH 59/72] imx-drm: hdmi: set DI clock source to DI pre clock

[Steve Longerbeam]

If DI is firstly bound to ldb and then re-bound to HDMI,
DI clock source will still be routed to LDB clock by ldb driver.
In HDMI driver's encoder_prepare, we have to set DI clock source to
the parent di_pre clock mux to ensure we are having correct clock
chain to drive HDMI display.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
---
 arch/arm/boot/dts/imx6dl.dtsi      |    8 ++++++++
 arch/arm/boot/dts/imx6q.dtsi       |   12 ++++++++++++
 arch/arm/boot/dts/imx6qdl.dtsi     |    3 ---
 drivers/staging/imx-drm/imx-hdmi.c |   32 +++++++++++++++++++++++++++++++-
 4 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 05af0f4..7d1a1bf 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -104,6 +104,14 @@
 
 &hdmi {
 	compatible = "fsl,imx6dl-hdmi";
+	clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, <&clks IMX6QDL_CLK_HDMI_ISFR>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI1_SEL>;
+	clock-names = "iahb", "isfr",
+		      "di0_pre_sel", "di1_pre_sel",
+		      "di0_sel", "di1_sel";
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 9d1f88c..7d0a7bc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -235,6 +235,18 @@
 
 &hdmi {
 	compatible = "fsl,imx6q-hdmi";
+	clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, <&clks IMX6QDL_CLK_HDMI_ISFR>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>,
+		 <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
+		 <&clks IMX6QDL_CLK_IPU2_DI1_SEL>;
+	clock-names = "iahb", "isfr",
+		      "di0_pre_sel", "di1_pre_sel", "di2_pre_sel", "di3_pre_sel",
+		      "di0_sel", "di1_sel", "di2_sel", "di3_sel";
 
 	port@2 {
 		reg = <2>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 13d6b50..4e3a3e8 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -810,9 +810,6 @@
 				reg = <0x00120000 0x9000>;
 				interrupts = <0 115 0x04>;
 				gpr = <&gpr>;
-				clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
-					 <&clks IMX6QDL_CLK_HDMI_ISFR>;
-				clock-names = "iahb", "isfr";
 				status = "disabled";
 
 				port@0 {
diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index 4ef1c0a..d97fa18 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -118,6 +118,8 @@ struct imx_hdmi {
 	struct device *dev;
 	struct clk *isfr_clk;
 	struct clk *iahb_clk;
+	struct clk *di_pre_sel[4];
+	struct clk *di_sel[4];
 
 	struct hdmi_data_info hdmi_data;
 	int vic;
@@ -1452,8 +1454,13 @@ static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
 static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
+	int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
 
 	imx_hdmi_poweroff(hdmi);
+
+	/* set DI clock mux to DI pre clock mux */
+	clk_set_parent(hdmi->di_sel[mux], hdmi->di_pre_sel[mux]);
+
 	imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24, NULL);
 }
 
@@ -1593,7 +1600,7 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 	struct device_node *ddc_node;
 	struct imx_hdmi *hdmi;
 	struct resource *iores;
-	int ret;
+	int i, ret;
 
 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 	if (!hdmi)
@@ -1629,6 +1636,29 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
 	if (IS_ERR(hdmi->regmap))
 		return PTR_ERR(hdmi->regmap);
 
+	for (i = 0; i < 4; i++) {
+		char clkname[16];
+
+		sprintf(clkname, "di%d_pre_sel", i);
+		hdmi->di_pre_sel[i] = devm_clk_get(hdmi->dev, clkname);
+		if (IS_ERR(hdmi->di_pre_sel[i])) {
+			ret = PTR_ERR(hdmi->di_pre_sel[i]);
+			hdmi->di_pre_sel[i] = NULL;
+			break;
+		}
+
+		sprintf(clkname, "di%d_sel", i);
+		hdmi->di_sel[i] = devm_clk_get(hdmi->dev, clkname);
+		if (IS_ERR(hdmi->di_sel[i])) {
+			ret = PTR_ERR(hdmi->di_sel[i]);
+			hdmi->di_pre_sel[i] = NULL;
+			hdmi->di_sel[i] = NULL;
+			break;
+		}
+	}
+	if (i == 0)
+		return ret;
+
 	hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
 	if (IS_ERR(hdmi->isfr_clk)) {
 		ret = PTR_ERR(hdmi->isfr_clk);
-- 
1.7.9.5

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[PATCH 60/72] imx-drm: ipuv3-crtc: Set the crtc device name

[Steve Longerbeam]

Set the i.mx crtc device name to a more meaningful crtc[0-3], which
matches the device tree phandle names.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c |   10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index bd158d6..316e5bf 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -80,6 +80,7 @@ struct ipu_crtc {
 	struct device           *ipu_dev; /* our ipu */
 	struct ipu_soc          *ipu;
 	struct device_node      *port;    /* our port */
+	int			id;       /* this crtc's id */
 
 	const struct ipu_channels *ch;
 
@@ -545,7 +546,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 			 struct drm_device *drm)
 {
 	struct device_node *np = ipu_crtc->dev->of_node;
-	int id, primary_pipe, overlay_pipe;
+	int primary_pipe, overlay_pipe;
 	int ret;
 
 	ret = ipu_get_resources(ipu_crtc, np);
@@ -563,7 +564,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 		goto err_put_resources;
 	}
 
-	id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
+	ipu_crtc->id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
 	primary_pipe = imx_drm_primary_plane_pipe(ipu_crtc->imx_crtc);
 
 	ret = ipu_plane_init(&ipu_crtc->plane[0], drm,
@@ -571,7 +572,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 			     primary_pipe,
 			     ipu_crtc->ch->dma[0],
 			     ipu_crtc->ch->dp[0],
-			     BIT(id), true);
+			     BIT(ipu_crtc->id), true);
 	if (ret) {
 		dev_err(ipu_crtc->dev, "init primary plane failed with %d\n",
 			ret);
@@ -593,7 +594,7 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
 				     overlay_pipe,
 				     ipu_crtc->ch->dma[1],
 				     ipu_crtc->ch->dp[1],
-				     BIT(id), false);
+				     BIT(ipu_crtc->id), false);
 
 		ipu_crtc->have_overlay = ret ? false : true;
 	}
@@ -625,6 +626,7 @@ static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
 		return ret;
 
 	dev_set_drvdata(dev, ipu_crtc);
+	dev_set_name(dev, "crtc%d", ipu_crtc->id);
 
 	return 0;
 }
-- 
1.7.9.5

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[PATCH 61/72] imx-drm: hdmi: Save ipu/di mux for later iomux setup

[Steve Longerbeam]

Store the ipu/di mux in struct imx_hdmi during imx_hdmi_encoder_prepare().
imx_hdmi_encoder_commit() can then use the mux when setting the iomux
instead of looking it up again via imx_drm_encoder_get_mux_id().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-hdmi.c |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index d97fa18..2503237 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -124,6 +124,7 @@ struct imx_hdmi {
 	struct hdmi_data_info hdmi_data;
 	int vic;
 	int irq;
+	int mux;
 
 	u8 edid[HDMI_EDID_LEN];
 	bool cable_plugin;
@@ -1454,12 +1455,13 @@ static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
 static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
 {
 	struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
-	int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
+
+	hdmi->mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
 
 	imx_hdmi_poweroff(hdmi);
 
 	/* set DI clock mux to DI pre clock mux */
-	clk_set_parent(hdmi->di_sel[mux], hdmi->di_pre_sel[mux]);
+	clk_set_parent(hdmi->di_sel[hdmi->mux], hdmi->di_pre_sel[hdmi->mux]);
 
 	imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24, NULL);
 }
@@ -1467,9 +1469,8 @@ static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
 static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
 {
 	struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
-	int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
 
-	imx_hdmi_set_ipu_di_mux(hdmi, mux);
+	imx_hdmi_set_ipu_di_mux(hdmi, hdmi->mux);
 
 	imx_hdmi_poweron(hdmi);
 }
-- 
1.7.9.5

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[PATCH 62/72] imx-drm: ipuv3-plane: Assign correct dmfc burst size

[Steve Longerbeam]

According to the imx6 reference manual, the DMFC channel's
burstsize must match the corresponding IDMAC channel's burstsize,
so make sure to pass the IDMAC channel burstsize to
ipu_dmfc_alloc_bandwidth(). We need to move ipu_dmfc_alloc_bandwidth()
to after the channel is setup, in order to first initialize the
channel burstsize, before retrieving it with ipu_cpmem_get_burstsize().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |   20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index 61d47e9..aa10ae7 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -159,7 +159,7 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 {
 	struct device *dev = ipu_plane->base.dev->dev;
 	bool is_bg = (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_BG);
-	int ret;
+	int burstsize, ret;
 
 	/* no scaling */
 	if (src_w != crtc_w || src_h != crtc_h)
@@ -238,14 +238,6 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		}
 	}
 
-	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
-			calc_bandwidth(crtc_w, crtc_h,
-				       calc_vref(mode)), crtc_w, 64);
-	if (ret) {
-		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
-		return ret;
-	}
-
 	ipu_cpmem_zero(ipu_plane->ipu_ch);
 	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
 	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
@@ -260,6 +252,16 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 
 	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
 
+	burstsize = ipu_cpmem_get_burstsize(ipu_plane->ipu_ch);
+
+	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
+			calc_bandwidth(crtc_w, crtc_h,
+				       calc_vref(mode)), crtc_w, burstsize);
+	if (ret) {
+		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
+		return ret;
+	}
+
 	/* enable double-buffering */
 	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, true);
 
-- 
1.7.9.5

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[PATCH 63/72] drm_modes: videomode: add pos/neg pixel clock polarity flag

[Steve Longerbeam]

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/gpu/drm/drm_modes.c |    4 ++++
 include/uapi/drm/drm_mode.h |    4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index d1b7d20..5016099 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -611,6 +611,10 @@ void drm_display_mode_from_videomode(const struct videomode *vm,
 		dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
 	if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
 		dmode->flags |= DRM_MODE_FLAG_DBLCLK;
+	if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
+		dmode->flags |= DRM_MODE_FLAG_PCLK;
+	else if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+		dmode->flags |= DRM_MODE_FLAG_NCLK;
 	drm_mode_set_name(dmode);
 }
 EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode);
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 8d98cd0..d5d045c 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -72,6 +72,10 @@
 #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6<<14)
 #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7<<14)
 #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8<<14)
+/* drive data on rising pixclk edge */
+#define DRM_MODE_FLAG_PCLK			(1<<19)
+/* drive data on falling pixclk edge */
+#define DRM_MODE_FLAG_NCLK			(1<<20)
 
 
 /* DPMS flags */
-- 
1.7.9.5

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[PATCH 64/72] imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock polarity

[Steve Longerbeam]

Previously, pixel clock polarity was hardcoded and wasn't configurable.
This patch adds support to configure the pixel clock polarity from the
DRM mode flags.

Signed-off-by: Mohsin Kazmi <mohsin_kazmi@mentor.com>
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 316e5bf..65fe429 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -291,9 +291,10 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 		sig_cfg.hsync_pol = 1;
 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 		sig_cfg.vsync_pol = 1;
+	if (mode->flags & DRM_MODE_FLAG_PCLK)
+		sig_cfg.clk_pol = 1;
 
 	sig_cfg.enable_pol = 1;
-	sig_cfg.clk_pol = 0;
 	sig_cfg.width = mode->hdisplay;
 	sig_cfg.height = mode->vdisplay;
 	sig_cfg.pixel_fmt = out_pixel_fmt;
-- 
1.7.9.5

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[PATCH 65/72] imx-drm: imx-ldb: Add all defined of video modes

[Steve Longerbeam]

Instead of assuming only a single defined display-timing node in the
device tree, assume there can be multiple modes and register all of
them in imx_ldb_connector_get_modes().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-ldb.c |   46 ++++++++++++++++++++++---------------
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 53d9d82..615e090 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -28,7 +28,9 @@
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
-#include <video/of_videomode.h>
+#include <video/display_timing.h>
+#include <video/of_display_timing.h>
+#include <video/videomode.h>
 #include <linux/regmap.h>
 #include <linux/videodev2.h>
 
@@ -65,8 +67,7 @@ struct imx_ldb_channel {
 	int chno;
 	void *edid;
 	int edid_len;
-	struct drm_display_mode mode;
-	int mode_valid;
+	struct display_timings *timings;
 };
 
 struct bus_mux {
@@ -100,6 +101,7 @@ static enum drm_connector_status imx_ldb_connector_detect(
 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
 {
 	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
+	struct display_timings *timings = imx_ldb_ch->timings;
 	int num_modes = 0;
 
 	imx_ldb_entry_dbg(imx_ldb_ch);
@@ -113,16 +115,26 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
 		num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
 	}
 
-	if (imx_ldb_ch->mode_valid) {
+	if (timings) {
 		struct drm_display_mode *mode;
+		struct videomode vm;
+		int i;
 
-		mode = drm_mode_create(connector->dev);
-		if (!mode)
-			return -EINVAL;
-		drm_mode_copy(mode, &imx_ldb_ch->mode);
-		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-		drm_mode_probed_add(connector, mode);
-		num_modes++;
+		for (i = 0; i < timings->num_timings; i++) {
+			if (videomode_from_timings(timings, &vm, i))
+				break;
+
+			mode = drm_mode_create(connector->dev);
+			drm_display_mode_from_videomode(&vm, mode);
+
+			mode->type = DRM_MODE_TYPE_DRIVER;
+			if (i == timings->native_mode)
+				mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+			drm_mode_set_name(mode);
+			drm_mode_probed_add(connector, mode);
+			num_modes++;
+		}
 	}
 
 	return num_modes;
@@ -568,16 +580,11 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
 				channel->edid = kmemdup(edidp,
 							channel->edid_len,
 							GFP_KERNEL);
-			} else {
-				/* fallback to display-timings node */
-				ret = of_get_drm_display_mode(child,
-							      &channel->mode,
-							      0);
-				if (!ret)
-					channel->mode_valid = 1;
 			}
 		}
 
+		channel->timings = of_get_display_timings(child);
+
 		ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
 		if (ret)
 			datawidth = 0;
@@ -639,6 +646,9 @@ static void imx_ldb_unbind(struct device *dev, struct device *master,
 		channel->encoder.funcs->destroy(&channel->encoder);
 
 		i2c_put_adapter(channel->ddc);
+
+		if (channel->timings)
+			display_timings_release(channel->timings);
 	}
 }
 
-- 
1.7.9.5

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[PATCH 66/72] imx-drm: parallel-display: Add all defined of video modes

[Steve Longerbeam]

Instead of assuming only a single defined display-timing node in the
device tree, assume there can be multiple modes and register all of
them in imx_pd_connector_get_modes().

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/parallel-display.c |   48 +++++++++++++++-------------
 1 file changed, 26 insertions(+), 22 deletions(-)

diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index e0b0b56..11ae35d 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -25,8 +25,9 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_panel.h>
 #include <linux/videodev2.h>
+#include <video/display_timing.h>
 #include <video/of_display_timing.h>
-#include <video/imx-ipu-v3.h>
+#include <video/videomode.h>
 
 #include "imx-drm.h"
 
@@ -41,8 +42,7 @@ struct imx_parallel_display {
 	int edid_len;
 	u32 interface_pix_fmt;
 	struct ipu_dc_if_map *interface_map;
-	int mode_valid;
-	struct drm_display_mode mode;
+	struct display_timings *timings;
 	struct drm_panel *panel;
 };
 
@@ -55,7 +55,7 @@ static enum drm_connector_status imx_pd_connector_detect(
 static int imx_pd_connector_get_modes(struct drm_connector *connector)
 {
 	struct imx_parallel_display *imxpd = con_to_imxpd(connector);
-	struct device_node *np = imxpd->dev->of_node;
+	struct display_timings *timings = imxpd->timings;
 	int num_modes = 0;
 
 	if (imxpd->panel && imxpd->panel->funcs &&
@@ -70,27 +70,26 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
 		num_modes = drm_add_edid_modes(connector, imxpd->edid);
 	}
 
-	if (imxpd->mode_valid) {
-		struct drm_display_mode *mode = drm_mode_create(connector->dev);
+	if (timings) {
+		struct drm_display_mode *mode;
+		struct videomode vm;
+		int i;
 
-		if (!mode)
-			return -EINVAL;
-		drm_mode_copy(mode, &imxpd->mode);
-		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-		drm_mode_probed_add(connector, mode);
-		num_modes++;
-	}
+		for (i = 0; i < timings->num_timings; i++) {
+			if (videomode_from_timings(timings, &vm, i))
+				break;
 
-	if (np) {
-		struct drm_display_mode *mode = drm_mode_create(connector->dev);
+			mode = drm_mode_create(connector->dev);
+			drm_display_mode_from_videomode(&vm, mode);
 
-		if (!mode)
-			return -EINVAL;
-		of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE);
-		drm_mode_copy(mode, &imxpd->mode);
-		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-		drm_mode_probed_add(connector, mode);
-		num_modes++;
+			mode->type = DRM_MODE_TYPE_DRIVER;
+			if (i == timings->native_mode)
+				mode->type |= DRM_MODE_TYPE_PREFERRED;
+
+			drm_mode_set_name(mode);
+			drm_mode_probed_add(connector, mode);
+			num_modes++;
+		}
 	}
 
 	return num_modes;
@@ -223,6 +222,8 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 	if (edidp)
 		imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL);
 
+	imxpd->timings = of_get_display_timings(np);
+
 	ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
 	if (!ret) {
 		if (!strcmp(fmt, "rgb24"))
@@ -282,6 +283,9 @@ static void imx_pd_unbind(struct device *dev, struct device *master,
 
 	imxpd->encoder.funcs->destroy(&imxpd->encoder);
 	imxpd->connector.funcs->destroy(&imxpd->connector);
+
+	if (imxpd->timings)
+		display_timings_release(imxpd->timings);
 }
 
 static const struct component_ops imx_pd_ops = {
-- 
1.7.9.5

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[PATCH 67/72] imx-drm: ipuv3-crtc: Disable fb on crtc unbind

[Steve Longerbeam]

Call ipu_fb_disable() in the crtc unbind method, in case the
crtc has been left enabled.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 65fe429..53241fd 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -637,6 +637,8 @@ static void ipu_drm_unbind(struct device *dev, struct device *master,
 {
 	struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
 
+	ipu_fb_disable(ipu_crtc);
+
 	imx_drm_remove_crtc(ipu_crtc->imx_crtc);
 
 	ipu_plane_put_resources(&ipu_crtc->plane[0]);
-- 
1.7.9.5

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[PATCH 68/72] imx-drm: imx-ldb: Use DDC probe as connection detect

[Steve Longerbeam]

If a ddc node was specified in the device tree, use it in
imx_ldb_connector_detect() to probe the ddc with drm_probe_ddc(), if
the result is success, we know there is a display connected so return
connected status. Otherwise (no ddc specified in DT) we just have to
assume connected status.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-ldb.c |   24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 615e090..319eedb 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -92,10 +92,32 @@ struct imx_ldb {
 #define imx_ldb_entry_dbg(ch)			\
 	imx_ldb_dbg((ch), "%s\n", __func__)
 
+/*
+ * Use the result of ddc probe to detect LVDS display presence
+ * if a ddc DT node was specified.
+ */
 static enum drm_connector_status imx_ldb_connector_detect(
 		struct drm_connector *connector, bool force)
 {
-	return connector_status_connected;
+	struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
+	enum drm_connector_status status;
+
+	if (imx_ldb_ch->ddc) {
+		if (drm_probe_ddc(imx_ldb_ch->ddc)) {
+			status = connector_status_connected;
+			imx_ldb_dbg(imx_ldb_ch,
+				    "ddc probe success, connected\n");
+		} else {
+			status = connector_status_disconnected;
+			imx_ldb_dbg(imx_ldb_ch,
+				    "ddc probe failed, disconnected\n");
+		}
+	} else {
+		status = connector_status_connected;
+		imx_ldb_dbg(imx_ldb_ch, "no ddc, assuming connected\n");
+	}
+
+	return status;
 }
 
 static int imx_ldb_connector_get_modes(struct drm_connector *connector)
-- 
1.7.9.5

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[PATCH 69/72] imx-drm: ipuv3-crtc: Implement mode_set_base

[Steve Longerbeam]

Implement the mode_set_base drm_crtc_helper callback. DRM core calls
this method when there is a SetCrtc request but only the framebuffer
and/or the x/y scanout position in the framebuffer has changed and no
other video mode parameters have changed.

So mode_set_base is similar to a page flip except that there is no
page flip event handling. So ipu_crtc_mode_set_base() simply calls
ipu_plane_page_flip() with a NULL event pointer. A reference on the
vblank interrupt will be acquired and then released when the flip
completes, as in a normal page flip.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 53241fd..179b764 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -174,6 +174,17 @@ static int ipu_crtc_page_flip(struct drm_crtc *crtc,
 	return ipu_plane_page_flip(crtc->primary, fb, event, page_flip_flags);
 }
 
+static int ipu_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+				  struct drm_framebuffer *old_fb)
+{
+	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+	ipu_crtc->plane[0].x = x;
+	ipu_crtc->plane[0].y = y;
+
+	return ipu_plane_page_flip(crtc->primary, crtc->primary->fb, NULL, 0);
+}
+
 /*
  * Normally the DRM Gamma API is used to program a color LUT that contains
  * gamma-corrected pixel values for red, green, and blue input pixel values
@@ -358,6 +369,7 @@ static void ipu_crtc_commit(struct drm_crtc *crtc)
 
 static struct drm_crtc_helper_funcs ipu_helper_funcs = {
 	.dpms = ipu_crtc_dpms,
+	.mode_set_base = ipu_crtc_mode_set_base,
 	.mode_fixup = ipu_crtc_mode_fixup,
 	.mode_set = ipu_crtc_mode_set,
 	.prepare = ipu_crtc_prepare,
-- 
1.7.9.5

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[PATCH 70/72] imx-drm: Cancel pending page flip events at preclose

[Steve Longerbeam]

At preclose, destroy page flip events that are pending on every
plane.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/imx-drm-core.c |   15 +++++++++++++--
 drivers/staging/imx-drm/imx-drm.h      |    2 ++
 drivers/staging/imx-drm/ipuv3-crtc.c   |   13 +++++++++++++
 drivers/staging/imx-drm/ipuv3-plane.c  |   22 ++++++++++++++++++++++
 drivers/staging/imx-drm/ipuv3-plane.h  |    2 ++
 5 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index b31d291..b2cc77b 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -213,13 +213,24 @@ static void imx_drm_disable_vblank(struct drm_device *drm, int pipe)
 static void imx_drm_driver_preclose(struct drm_device *drm,
 		struct drm_file *file)
 {
+	struct imx_drm_device *imxdrm = drm->dev_private;
+	struct imx_drm_crtc_helper_funcs *helpers;
+	struct imx_drm_crtc *imx_drm_crtc;
 	int pipe;
 
 	if (!file->is_master)
 		return;
 
-	for (pipe = 0; pipe < MAX_PIPES; pipe++)
-		imx_drm_disable_vblank(drm, pipe);
+	for (pipe = 0; pipe < MAX_PIPES; pipe++) {
+		imx_drm_crtc = imxdrm->crtc[pipe_to_crtc_id(pipe)];
+		if (!imx_drm_crtc)
+			continue;
+		helpers = &imx_drm_crtc->imx_drm_helper_funcs;
+		if (!helpers->cancel_page_flip)
+			continue;
+
+		helpers->cancel_page_flip(imx_drm_crtc->crtc, file, pipe);
+	}
 }
 
 static const struct file_operations imx_drm_driver_fops = {
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index 24b889a..8ffcc0a 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -21,6 +21,8 @@ int imx_drm_overlay_plane_pipe(struct imx_drm_crtc *crtc);
 struct imx_drm_crtc_helper_funcs {
 	int (*enable_vblank)(struct drm_crtc *crtc, int pipe);
 	void (*disable_vblank)(struct drm_crtc *crtc, int pipe);
+	void (*cancel_page_flip)(struct drm_crtc *crtc, struct drm_file *file,
+				 int pipe);
 	int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 encoder_type,
 				     u32 pix_fmt, struct ipu_dc_if_map *pix_map,
 				     int hsync_pin, int vsync_pin);
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 179b764..7d5b691 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -398,6 +398,18 @@ static void ipu_disable_vblank(struct drm_crtc *crtc, int pipe)
 	ipu_plane_disable_vblank(ipu_plane);
 }
 
+static void ipu_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file,
+				 int pipe)
+{
+	struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+	struct ipu_plane *ipu_plane = pipe_to_plane(ipu_crtc, pipe);
+
+	if (!ipu_plane)
+		return;
+
+	ipu_plane_cancel_page_flip(ipu_plane, file);
+}
+
 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
 				     u32 pixfmt, struct ipu_dc_if_map *pixmap,
 				     int hsync_pin, int vsync_pin)
@@ -435,6 +447,7 @@ static int ipu_gamma_set(struct drm_crtc *crtc, bool enable, u32 *m, u32 *b)
 static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
 	.enable_vblank = ipu_enable_vblank,
 	.disable_vblank = ipu_disable_vblank,
+	.cancel_page_flip = ipu_cancel_page_flip,
 	.set_interface_pix_fmt = ipu_set_interface_pix_fmt,
 	.gamma_set = ipu_gamma_set,
 	.crtc_funcs = &ipu_crtc_funcs,
diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index aa10ae7..c012c4e 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -150,6 +150,28 @@ void ipu_plane_disable_vblank(struct ipu_plane *ipu_plane)
 	ipu_plane->newfb = NULL;
 }
 
+void ipu_plane_cancel_page_flip(struct ipu_plane *ipu_plane,
+				struct drm_file *file)
+{
+	struct drm_device *drm = ipu_plane->base.dev;
+	struct drm_pending_vblank_event *event;
+	unsigned long flags;
+
+	/*
+	 * Destroy the pending vertical blanking event associated with the
+	 * pending page flip, if any, and disable vertical blanking interrupts.
+	 */
+	spin_lock_irqsave(&drm->event_lock, flags);
+	event = ipu_plane->page_flip_event;
+	if (event && event->base.file_priv == file) {
+		ipu_plane->page_flip_event = NULL;
+		ipu_plane->newfb = NULL;
+		event->base.destroy(&event->base);
+		drm_vblank_put(drm, ipu_plane->pipe);
+	}
+	spin_unlock_irqrestore(&drm->event_lock, flags);
+}
+
 int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 		       struct drm_display_mode *mode,
 		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
diff --git a/drivers/staging/imx-drm/ipuv3-plane.h b/drivers/staging/imx-drm/ipuv3-plane.h
index 912902a..c584a6a 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.h
+++ b/drivers/staging/imx-drm/ipuv3-plane.h
@@ -63,6 +63,8 @@ int ipu_plane_page_flip(struct drm_plane *plane,
 
 int ipu_plane_enable_vblank(struct ipu_plane *ipu_plane);
 void ipu_plane_disable_vblank(struct ipu_plane *ipu_plane);
+void ipu_plane_cancel_page_flip(struct ipu_plane *ipu_plane,
+				struct drm_file *file);
 
 void ipu_plane_enable(struct ipu_plane *plane);
 void ipu_plane_disable(struct ipu_plane *plane);
-- 
1.7.9.5

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[PATCH 71/72] imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable

[Steve Longerbeam]

If the overlay exists and is enabled, it must be disabled before
stopping the DI, otherwise DI synchronous display errors are the
result.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-crtc.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index 7d5b691..b49d1b2 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -138,6 +138,14 @@ static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
 	if (!ipu_crtc->enabled)
 		return;
 
+	/*
+	 * If the overlay exists and is enabled, it must be disabled
+	 * before stopping the DI, otherwise DI synchronous display
+	 * errors are the result.
+	 */
+	if (ipu_crtc->have_overlay && ipu_crtc->plane[1].enabled)
+		ipu_plane_disable(&ipu_crtc->plane[1]);
+
 	/* Stop DC channel and DI before IDMAC */
 	ipu_dc_disable_channel(ipu_crtc->dc);
 	ipu_di_disable(ipu_crtc->di);
-- 
1.7.9.5

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[PATCH 72/72] imx-drm: ipuv3-plane: Enable 8 burst locking

[Steve Longerbeam]

Enable 8 burst locking in the primary and overlay plane
idmac channels. This seems to improve some cases of data
starvation errors to the DI.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
 drivers/staging/imx-drm/ipuv3-plane.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/staging/imx-drm/ipuv3-plane.c b/drivers/staging/imx-drm/ipuv3-plane.c
index c012c4e..5849b30 100644
--- a/drivers/staging/imx-drm/ipuv3-plane.c
+++ b/drivers/staging/imx-drm/ipuv3-plane.c
@@ -273,6 +273,7 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
 					 fb->pitches[0], crtc_h);
 
 	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
+	ipu_idmac_lock_enable(ipu_plane->ipu_ch, 8);
 
 	burstsize = ipu_cpmem_get_burstsize(ipu_plane->ipu_ch);
 
-- 
1.7.9.5

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

Hi Steve,

On Fri, Oct 31, 2014 at 8:53 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> except for two patches that affect drm core (patch 53 and 63, see below).
>
> New features for imx-drm staging driver:
>
> - Support for multi-display (HDMI and LVDS).
> - Support for global alpha and color-key properties for overlay plane.
> - Support for gamma correction.
> - The imx-drm crtc devices moved to device tree.
> - Support for defining custom display interface pixel mappings in the
>   device tree.
> - Implements encoder DPMS for LVDS.
> - YUV planar pixel formats supported for DRM framebuffers.
> - DDC support added for LVDS.
> - Page flip handling moved to imx plane driver and implemented with
>   IPU double-buffering.
> - Support page-flip in the overlay plane (patch 53 affects drm core).
> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> - Add LVDS connection detect via drm_probe_ddc().
> - Implement crtc mode_set_base using plane page-flip.
>
>
> Fixed issues:
>
> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>   support).
> - Use counter added to IPU DC enable/disable (part of multi-display
>   support).
> - Fixed some HDMI timing issues.
> - Wider range of supported DI pixel clocks generated (all EDID modes
>   reported from HDMI displays now work).
> - Fix separate primary plane objects.
> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>   support).
> - Assign correct DMFC burst size.
> - Resolve some DI synchronous display error cases.
>
>
>
> George G. Davis (1):
>   ARM: dts: imx6qdl-sabreauto: Add HDMI device
>
> Jiada Wang (1):
>   gpu: ipu-v3: fix HDMI timing issues
>
> Steve Longerbeam (70):
>   ARM: dts: imx6qdl-sabrelite: Add HDMI device
>   ARM: dts: imx6qdl: Create imx-drm crtc nodes
>   ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
>   ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip
>   gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
>   gpu: ipu-v3: Add ipu_dp_set_chroma_key()
>   gpu: ipu-v3: Add ipu_dp_set_gamma_correction()
>   gpu: ipu-v3: Add support for dynamic DC interface pixel maps
>   gpu: ipu-v3: Add ipu_dc_uninit_sync()
>   gpu: ipu-v3: Pass struct ipu_dc to enable/disable
>   gpu: ipu-v3: Add ipu_dp_uninit_channel()
>   gpu: ipu-v3: Pass struct ipu_dp to enable/disable
>   gpu: ipu-v3: Implement use counter for ipu_dc_enable(),
>     ipu_dc_disable()
>   gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug
>   gpu: ipu-v3: Add ipu_di_uninit_sync_panel()
>   gpu: ipu-v3: Split out DI clock enable/disable
>   gpu: ipu-v3: Protect more CM reg access with IPU lock
>   gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
>   gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()
>   gpu: ipu-v3: Fix indent/ws in ipu-dmfc
>   gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
>   gpu: ipu-v3: Remove ipu_dmfc_init_channel()
>   gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()
>   gpu: ipu-v3: Enumerate the DC channel names
>   gpu: ipu-di: Move ipu pointer init
>   gpu: ipu-di: Add and improve debug/error messages
>   gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg
>   gpu: ipu-v3: Remove IPU client registration
>   gpu: ipu-di: Set rate of DI pre clock
>   gpu: ipu-v3: Add RGB666 interface pixel map
>   gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*
>   gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()
>   gpu: ipu-v3: Add IDMA channel linking support
>   gpu: ipu-cpmem: Support YVU422
>   gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
>   imx-drm: Crtcs moved to device tree
>   imx-drm: hdmi: optimize i2c write wait
>   imx-drm: parallel-display: Support RGB666 pixel fmt
>   imx-drm: imx-ldb: Add debug to connector/encoder entry points
>   imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()
>   imx-drm: parallel-display: Fix typo when setting mode type
>   imx-drm: ipuv3-plane: Fix planar formats
>   imx-drm: ipuv3-plane: Allow YUV space for background plane
>   imx-drm: ipuv3-plane: Add more supported pixel formats
>   imx-drm: ipuv3-plane: Implement global alpha and colorkey properties
>   imx-drm: hdmi: rework irq request/free
>   imx-drm: imx-ldb: Add DDC support
>   imx-drm: Fix separate primary plane objects
>   imx-drm: Move page flip handling to plane driver
>   imx-drm: Reset ipu unit pointers to NULL on errors
>   drm: implement page flipping support for planes
>   imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs
>   imx-drm: Implement DRM gamma set
>   imx-drm: Implement custom ioctl to set gamma
>   imx-drm: Add support for interface pixel maps
>   imx-drm: parallel-display: Add interface-pix-map DT property
>   imx-drm: hdmi: set DI clock source to DI pre clock
>   imx-drm: ipuv3-crtc: Set the crtc device name
>   imx-drm: hdmi: Save ipu/di mux for later iomux setup
>   imx-drm: ipuv3-plane: Assign correct dmfc burst size
>   drm_modes: videomode: add pos/neg pixel clock polarity flag
>   imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock
>     polarity
>   imx-drm: imx-ldb: Add all defined of video modes
>   imx-drm: parallel-display: Add all defined of video modes
>   imx-drm: ipuv3-crtc: Disable fb on crtc unbind
>   imx-drm: imx-ldb: Use DDC probe as connection detect
>   imx-drm: ipuv3-crtc: Implement mode_set_base
>   imx-drm: Cancel pending page flip events at preclose
>   imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
>   imx-drm: ipuv3-plane: Enable 8 burst locking

Cool stuff!

Would you have a git tree we can use for test these?

Thanks
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 10/31/2014 05:09 PM, Fabio Estevam wrote:
> Hi Steve,
>
> On Fri, Oct 31, 2014 at 8:53 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>> except for two patches that affect drm core (patch 53 and 63, see below).
>>
>> New features for imx-drm staging driver:
>>
>> - Support for multi-display (HDMI and LVDS).
>> - Support for global alpha and color-key properties for overlay plane.
>> - Support for gamma correction.
>> - The imx-drm crtc devices moved to device tree.
>> - Support for defining custom display interface pixel mappings in the
>>   device tree.
>> - Implements encoder DPMS for LVDS.
>> - YUV planar pixel formats supported for DRM framebuffers.
>> - DDC support added for LVDS.
>> - Page flip handling moved to imx plane driver and implemented with
>>   IPU double-buffering.
>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>> - Add LVDS connection detect via drm_probe_ddc().
>> - Implement crtc mode_set_base using plane page-flip.
>>
>>
>> Fixed issues:
>>
>> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>>   support).
>> - Use counter added to IPU DC enable/disable (part of multi-display
>>   support).
>> - Fixed some HDMI timing issues.
>> - Wider range of supported DI pixel clocks generated (all EDID modes
>>   reported from HDMI displays now work).
>> - Fix separate primary plane objects.
>> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>>   support).
>> - Assign correct DMFC burst size.
>> - Resolve some DI synchronous display error cases.
>>
>>
>>
>> George G. Davis (1):
>>   ARM: dts: imx6qdl-sabreauto: Add HDMI device
>>
>> Jiada Wang (1):
>>   gpu: ipu-v3: fix HDMI timing issues
>>
>> Steve Longerbeam (70):
>>   ARM: dts: imx6qdl-sabrelite: Add HDMI device
>>   ARM: dts: imx6qdl: Create imx-drm crtc nodes
>>   ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
>>   ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip
>>   gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
>>   gpu: ipu-v3: Add ipu_dp_set_chroma_key()
>>   gpu: ipu-v3: Add ipu_dp_set_gamma_correction()
>>   gpu: ipu-v3: Add support for dynamic DC interface pixel maps
>>   gpu: ipu-v3: Add ipu_dc_uninit_sync()
>>   gpu: ipu-v3: Pass struct ipu_dc to enable/disable
>>   gpu: ipu-v3: Add ipu_dp_uninit_channel()
>>   gpu: ipu-v3: Pass struct ipu_dp to enable/disable
>>   gpu: ipu-v3: Implement use counter for ipu_dc_enable(),
>>     ipu_dc_disable()
>>   gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug
>>   gpu: ipu-v3: Add ipu_di_uninit_sync_panel()
>>   gpu: ipu-v3: Split out DI clock enable/disable
>>   gpu: ipu-v3: Protect more CM reg access with IPU lock
>>   gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
>>   gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()
>>   gpu: ipu-v3: Fix indent/ws in ipu-dmfc
>>   gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
>>   gpu: ipu-v3: Remove ipu_dmfc_init_channel()
>>   gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()
>>   gpu: ipu-v3: Enumerate the DC channel names
>>   gpu: ipu-di: Move ipu pointer init
>>   gpu: ipu-di: Add and improve debug/error messages
>>   gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg
>>   gpu: ipu-v3: Remove IPU client registration
>>   gpu: ipu-di: Set rate of DI pre clock
>>   gpu: ipu-v3: Add RGB666 interface pixel map
>>   gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*
>>   gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()
>>   gpu: ipu-v3: Add IDMA channel linking support
>>   gpu: ipu-cpmem: Support YVU422
>>   gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
>>   imx-drm: Crtcs moved to device tree
>>   imx-drm: hdmi: optimize i2c write wait
>>   imx-drm: parallel-display: Support RGB666 pixel fmt
>>   imx-drm: imx-ldb: Add debug to connector/encoder entry points
>>   imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()
>>   imx-drm: parallel-display: Fix typo when setting mode type
>>   imx-drm: ipuv3-plane: Fix planar formats
>>   imx-drm: ipuv3-plane: Allow YUV space for background plane
>>   imx-drm: ipuv3-plane: Add more supported pixel formats
>>   imx-drm: ipuv3-plane: Implement global alpha and colorkey properties
>>   imx-drm: hdmi: rework irq request/free
>>   imx-drm: imx-ldb: Add DDC support
>>   imx-drm: Fix separate primary plane objects
>>   imx-drm: Move page flip handling to plane driver
>>   imx-drm: Reset ipu unit pointers to NULL on errors
>>   drm: implement page flipping support for planes
>>   imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs
>>   imx-drm: Implement DRM gamma set
>>   imx-drm: Implement custom ioctl to set gamma
>>   imx-drm: Add support for interface pixel maps
>>   imx-drm: parallel-display: Add interface-pix-map DT property
>>   imx-drm: hdmi: set DI clock source to DI pre clock
>>   imx-drm: ipuv3-crtc: Set the crtc device name
>>   imx-drm: hdmi: Save ipu/di mux for later iomux setup
>>   imx-drm: ipuv3-plane: Assign correct dmfc burst size
>>   drm_modes: videomode: add pos/neg pixel clock polarity flag
>>   imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock
>>     polarity
>>   imx-drm: imx-ldb: Add all defined of video modes
>>   imx-drm: parallel-display: Add all defined of video modes
>>   imx-drm: ipuv3-crtc: Disable fb on crtc unbind
>>   imx-drm: imx-ldb: Use DDC probe as connection detect
>>   imx-drm: ipuv3-crtc: Implement mode_set_base
>>   imx-drm: Cancel pending page flip events at preclose
>>   imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
>>   imx-drm: ipuv3-plane: Enable 8 burst locking
> Cool stuff!
>
> Would you have a git tree we can use for test these?

Hi Fabio, Yes I forgot to mention that in the cover letter:

git@github.com:slongerbeam/drm-next.git

Branch is imx-drm-mentor.

Steve

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Re: [PATCH 53/72] drm: implement page flipping support for planes

[Rob Clark]

On Fri, Oct 31, 2014 at 6:54 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
> Planes like crtcs would benefit from having page flip event support.
> With planes page flip it is now possible to synchronize changing a
> framebuffer used by an overlay (or even cursor) plane with vertical
> sync events.
>
> A page flip in the primary plane is equivalent to a crtc page flip,
> which suggests this ioctl could deprecate the crtc page flip ioctl
> at some point in the future.

jfyi, a plane_page_flip ioctl would be useful, except it is about to
be obsolete by the atomic stuff that Daniel is working on

BR,
-R

> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> Signed-off-by: Dmitry Eremin-Solenikov <dmitry_eremin@mentor.com>
> ---
>  drivers/gpu/drm/drm_crtc.c  |  241 +++++++++++++++++++++++++------------------
>  drivers/gpu/drm/drm_ioctl.c |    1 +
>  include/drm/drm_crtc.h      |   11 ++
>  include/uapi/drm/drm.h      |    1 +
>  include/uapi/drm/drm_mode.h |    8 ++
>  5 files changed, 164 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index e79c8d3..53b5f87 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -2445,6 +2445,142 @@ int drm_mode_setplane(struct drm_device *dev, void *data,
>                                  plane_req->src_w, plane_req->src_h);
>  }
>
> +int drm_mode_plane_page_flip_ioctl(struct drm_device *dev,
> +                                  void *data, struct drm_file *file_priv)
> +{
> +       struct drm_mode_plane_page_flip *page_flip = data;
> +       struct drm_plane *plane;
> +       struct drm_crtc *crtc;
> +       struct drm_framebuffer *fb = NULL;
> +       struct drm_pending_vblank_event *e = NULL;
> +       unsigned long flags;
> +       bool is_primary;
> +       int ret;
> +
> +       if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
> +           page_flip->reserved != 0)
> +               return -EINVAL;
> +
> +       if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) &&
> +           !dev->mode_config.async_page_flip)
> +               return -EINVAL;
> +
> +       plane = drm_plane_find(dev, page_flip->plane_id);
> +       if (!plane)
> +               return -ENOENT;
> +
> +       is_primary = (plane->type == DRM_PLANE_TYPE_PRIMARY);
> +
> +       drm_modeset_lock_all(dev);
> +
> +       if (plane->crtc == NULL || plane->fb == NULL) {
> +               /* The crtc and/or framebuffer is currently unbound,
> +                * presumably due to a hotplug event, that userspace
> +                * has not yet discovered.
> +                */
> +               ret = -EBUSY;
> +               goto out;
> +       }
> +       crtc = plane->crtc;
> +
> +       if ((is_primary && crtc->funcs->page_flip == NULL) ||
> +           plane->funcs->page_flip == NULL) {
> +               ret = -EINVAL;
> +               goto out;
> +       }
> +
> +       fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
> +       if (!fb) {
> +               ret = -ENOENT;
> +               goto out;
> +       }
> +
> +       /*
> +        * If this is the primary plane (equivalent to a crtc page flip),
> +        * verify that the fb is valid for the bound crtc's viewport.
> +        * For overlay or cursor planes, the plane's page_flip op should
> +        * check that the fb is valid.
> +        */
> +       if (is_primary) {
> +               ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y,
> +                                             &crtc->mode, fb);
> +               if (ret)
> +                       goto out;
> +       }
> +
> +       if (plane->fb->pixel_format != fb->pixel_format) {
> +               DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
> +               ret = -EINVAL;
> +               goto out;
> +       }
> +
> +       if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
> +               ret = -ENOMEM;
> +               spin_lock_irqsave(&dev->event_lock, flags);
> +               if (file_priv->event_space < sizeof(e->event)) {
> +                       spin_unlock_irqrestore(&dev->event_lock, flags);
> +                       goto out;
> +               }
> +               file_priv->event_space -= sizeof(e->event);
> +               spin_unlock_irqrestore(&dev->event_lock, flags);
> +
> +               e = kzalloc(sizeof(*e), GFP_KERNEL);
> +               if (e == NULL) {
> +                       spin_lock_irqsave(&dev->event_lock, flags);
> +                       file_priv->event_space += sizeof(e->event);
> +                       spin_unlock_irqrestore(&dev->event_lock, flags);
> +                       goto out;
> +               }
> +
> +               e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
> +               e->event.base.length = sizeof(e->event);
> +               e->event.user_data = page_flip->user_data;
> +               e->base.event = &e->event.base;
> +               e->base.file_priv = file_priv;
> +               e->base.destroy =
> +                       (void (*) (struct drm_pending_event *)) kfree;
> +       }
> +
> +       plane->old_fb = plane->fb;
> +
> +       /* for now use crtc page_flip op, if this is the primary plane */
> +       if (is_primary)
> +               ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags);
> +       else
> +               ret = plane->funcs->page_flip(plane, fb, e, page_flip->flags);
> +
> +       if (ret) {
> +               if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
> +                       spin_lock_irqsave(&dev->event_lock, flags);
> +                       file_priv->event_space += sizeof(e->event);
> +                       spin_unlock_irqrestore(&dev->event_lock, flags);
> +                       kfree(e);
> +               }
> +               /* Keep the old fb, don't unref it. */
> +               plane->old_fb = NULL;
> +       } else {
> +               /*
> +                * Warn if the driver hasn't properly updated the plane->fb
> +                * field to reflect that the new framebuffer is now used.
> +                * Failing to do so will screw with the reference counting
> +                * on framebuffers.
> +                */
> +               WARN_ON(plane->fb != fb);
> +               /* Unref only the old framebuffer. */
> +               fb = NULL;
> +       }
> +
> +out:
> +       if (fb)
> +               drm_framebuffer_unreference(fb);
> +       if (plane->old_fb)
> +               drm_framebuffer_unreference(plane->old_fb);
> +       plane->old_fb = NULL;
> +       drm_modeset_unlock_all(dev);
> +
> +       return ret;
> +}
> +
>  /**
>   * drm_mode_set_config_internal - helper to call ->set_config
>   * @set: modeset config to set
> @@ -4582,111 +4718,20 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
>                              void *data, struct drm_file *file_priv)
>  {
>         struct drm_mode_crtc_page_flip *page_flip = data;
> +       struct drm_mode_plane_page_flip primary_pf = {0};
>         struct drm_crtc *crtc;
> -       struct drm_framebuffer *fb = NULL;
> -       struct drm_pending_vblank_event *e = NULL;
> -       unsigned long flags;
> -       int ret = -EINVAL;
> -
> -       if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
> -           page_flip->reserved != 0)
> -               return -EINVAL;
> -
> -       if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
> -               return -EINVAL;
>
>         crtc = drm_crtc_find(dev, page_flip->crtc_id);
>         if (!crtc)
>                 return -ENOENT;
>
> -       drm_modeset_lock_crtc(crtc);
> -       if (crtc->primary->fb == NULL) {
> -               /* The framebuffer is currently unbound, presumably
> -                * due to a hotplug event, that userspace has not
> -                * yet discovered.
> -                */
> -               ret = -EBUSY;
> -               goto out;
> -       }
> -
> -       if (crtc->funcs->page_flip == NULL)
> -               goto out;
> -
> -       fb = drm_framebuffer_lookup(dev, page_flip->fb_id);
> -       if (!fb) {
> -               ret = -ENOENT;
> -               goto out;
> -       }
> -
> -       ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y, &crtc->mode, fb);
> -       if (ret)
> -               goto out;
> -
> -       if (crtc->primary->fb->pixel_format != fb->pixel_format) {
> -               DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
> -               ret = -EINVAL;
> -               goto out;
> -       }
> -
> -       if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
> -               ret = -ENOMEM;
> -               spin_lock_irqsave(&dev->event_lock, flags);
> -               if (file_priv->event_space < sizeof e->event) {
> -                       spin_unlock_irqrestore(&dev->event_lock, flags);
> -                       goto out;
> -               }
> -               file_priv->event_space -= sizeof e->event;
> -               spin_unlock_irqrestore(&dev->event_lock, flags);
> -
> -               e = kzalloc(sizeof *e, GFP_KERNEL);
> -               if (e == NULL) {
> -                       spin_lock_irqsave(&dev->event_lock, flags);
> -                       file_priv->event_space += sizeof e->event;
> -                       spin_unlock_irqrestore(&dev->event_lock, flags);
> -                       goto out;
> -               }
> -
> -               e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
> -               e->event.base.length = sizeof e->event;
> -               e->event.user_data = page_flip->user_data;
> -               e->base.event = &e->event.base;
> -               e->base.file_priv = file_priv;
> -               e->base.destroy =
> -                       (void (*) (struct drm_pending_event *)) kfree;
> -       }
> -
> -       crtc->primary->old_fb = crtc->primary->fb;
> -       ret = crtc->funcs->page_flip(crtc, fb, e, page_flip->flags);
> -       if (ret) {
> -               if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) {
> -                       spin_lock_irqsave(&dev->event_lock, flags);
> -                       file_priv->event_space += sizeof e->event;
> -                       spin_unlock_irqrestore(&dev->event_lock, flags);
> -                       kfree(e);
> -               }
> -               /* Keep the old fb, don't unref it. */
> -               crtc->primary->old_fb = NULL;
> -       } else {
> -               /*
> -                * Warn if the driver hasn't properly updated the crtc->fb
> -                * field to reflect that the new framebuffer is now used.
> -                * Failing to do so will screw with the reference counting
> -                * on framebuffers.
> -                */
> -               WARN_ON(crtc->primary->fb != fb);
> -               /* Unref only the old framebuffer. */
> -               fb = NULL;
> -       }
> +       primary_pf.plane_id  = crtc->primary->base.id;
> +       primary_pf.fb_id     = page_flip->fb_id;
> +       primary_pf.flags     = page_flip->flags;
> +       primary_pf.user_data = page_flip->user_data;
>
> -out:
> -       if (fb)
> -               drm_framebuffer_unreference(fb);
> -       if (crtc->primary->old_fb)
> -               drm_framebuffer_unreference(crtc->primary->old_fb);
> -       crtc->primary->old_fb = NULL;
> -       drm_modeset_unlock_crtc(crtc);
> -
> -       return ret;
> +       return drm_mode_plane_page_flip_ioctl(dev, (void *)&primary_pf,
> +                                             file_priv);
>  }
>
>  /**
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index 00587a1..2e60ee3 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -620,6 +620,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
>         DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, DRM_CONTROL_ALLOW|DRM_UNLOCKED),
>         DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
>         DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
> +       DRM_IOCTL_DEF(DRM_IOCTL_MODE_PLANE_PAGE_FLIP, drm_mode_plane_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
>  };
>
>  #define DRM_CORE_IOCTL_COUNT   ARRAY_SIZE( drm_ioctls )
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index c40070a..26d859b 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -571,6 +571,7 @@ struct drm_connector {
>   * @disable_plane: shut down the plane
>   * @destroy: clean up plane resources
>   * @set_property: called when a property is changed
> + * @page_flip: initiate a page flip
>   */
>  struct drm_plane_funcs {
>         int (*update_plane)(struct drm_plane *plane,
> @@ -585,6 +586,14 @@ struct drm_plane_funcs {
>
>         int (*set_property)(struct drm_plane *plane,
>                             struct drm_property *property, uint64_t val);
> +
> +       /*
> +        * See comment at drm_crtc_funcs.page_flip
> +        */
> +       int (*page_flip)(struct drm_plane *plane,
> +                        struct drm_framebuffer *fb,
> +                        struct drm_pending_vblank_event *event,
> +                        uint32_t flags);
>  };
>
>  enum drm_plane_type {
> @@ -1105,6 +1114,8 @@ extern bool drm_detect_monitor_audio(struct edid *edid);
>  extern bool drm_rgb_quant_range_selectable(struct edid *edid);
>  extern int drm_mode_page_flip_ioctl(struct drm_device *dev,
>                                     void *data, struct drm_file *file_priv);
> +extern int drm_mode_plane_page_flip_ioctl(struct drm_device *dev,
> +                                   void *data, struct drm_file *file_priv);
>  extern int drm_add_modes_noedid(struct drm_connector *connector,
>                                 int hdisplay, int vdisplay);
>  extern void drm_set_preferred_mode(struct drm_connector *connector,
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index b0b8556..48d9da6 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -777,6 +777,7 @@ struct drm_prime_handle {
>  #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES       DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
>  #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
>  #define DRM_IOCTL_MODE_CURSOR2         DRM_IOWR(0xBB, struct drm_mode_cursor2)
> +#define DRM_IOCTL_MODE_PLANE_PAGE_FLIP DRM_IOWR(0xBC, struct drm_mode_plane_page_flip)
>
>  /**
>   * Device specific ioctls should only be in their respective headers
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index a0db2d4a..8d98cd0 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -488,6 +488,14 @@ struct drm_mode_crtc_page_flip {
>         __u64 user_data;
>  };
>
> +struct drm_mode_plane_page_flip {
> +       __u32 plane_id;
> +       __u32 fb_id;
> +       __u32 flags;
> +       __u32 reserved;
> +       __u64 user_data;
> +};
> +
>  /* create a dumb scanout buffer */
>  struct drm_mode_create_dumb {
>         uint32_t height;
> --
> 1.7.9.5
>
> _______________________________________________
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> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 10/31/2014 05:09 PM, Fabio Estevam wrote:
> Hi Steve,
>
> On Fri, Oct 31, 2014 at 8:53 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>> except for two patches that affect drm core (patch 53 and 63, see below).
>>
>> New features for imx-drm staging driver:
>>
>> - Support for multi-display (HDMI and LVDS).
>> - Support for global alpha and color-key properties for overlay plane.
>> - Support for gamma correction.
>> - The imx-drm crtc devices moved to device tree.
>> - Support for defining custom display interface pixel mappings in the
>>   device tree.
>> - Implements encoder DPMS for LVDS.
>> - YUV planar pixel formats supported for DRM framebuffers.
>> - DDC support added for LVDS.
>> - Page flip handling moved to imx plane driver and implemented with
>>   IPU double-buffering.
>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>> - Add LVDS connection detect via drm_probe_ddc().
>> - Implement crtc mode_set_base using plane page-flip.
>>
>>
>> Fixed issues:
>>
>> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>>   support).
>> - Use counter added to IPU DC enable/disable (part of multi-display
>>   support).
>> - Fixed some HDMI timing issues.
>> - Wider range of supported DI pixel clocks generated (all EDID modes
>>   reported from HDMI displays now work).
>> - Fix separate primary plane objects.
>> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>>   support).
>> - Assign correct DMFC burst size.
>> - Resolve some DI synchronous display error cases.
>>
>>
>>
>> George G. Davis (1):
>>   ARM: dts: imx6qdl-sabreauto: Add HDMI device
>>
>> Jiada Wang (1):
>>   gpu: ipu-v3: fix HDMI timing issues
>>
>> Steve Longerbeam (70):
>>   ARM: dts: imx6qdl-sabrelite: Add HDMI device
>>   ARM: dts: imx6qdl: Create imx-drm crtc nodes
>>   ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
>>   ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip
>>   gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
>>   gpu: ipu-v3: Add ipu_dp_set_chroma_key()
>>   gpu: ipu-v3: Add ipu_dp_set_gamma_correction()
>>   gpu: ipu-v3: Add support for dynamic DC interface pixel maps
>>   gpu: ipu-v3: Add ipu_dc_uninit_sync()
>>   gpu: ipu-v3: Pass struct ipu_dc to enable/disable
>>   gpu: ipu-v3: Add ipu_dp_uninit_channel()
>>   gpu: ipu-v3: Pass struct ipu_dp to enable/disable
>>   gpu: ipu-v3: Implement use counter for ipu_dc_enable(),
>>     ipu_dc_disable()
>>   gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug
>>   gpu: ipu-v3: Add ipu_di_uninit_sync_panel()
>>   gpu: ipu-v3: Split out DI clock enable/disable
>>   gpu: ipu-v3: Protect more CM reg access with IPU lock
>>   gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
>>   gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()
>>   gpu: ipu-v3: Fix indent/ws in ipu-dmfc
>>   gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
>>   gpu: ipu-v3: Remove ipu_dmfc_init_channel()
>>   gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()
>>   gpu: ipu-v3: Enumerate the DC channel names
>>   gpu: ipu-di: Move ipu pointer init
>>   gpu: ipu-di: Add and improve debug/error messages
>>   gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg
>>   gpu: ipu-v3: Remove IPU client registration
>>   gpu: ipu-di: Set rate of DI pre clock
>>   gpu: ipu-v3: Add RGB666 interface pixel map
>>   gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*
>>   gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()
>>   gpu: ipu-v3: Add IDMA channel linking support
>>   gpu: ipu-cpmem: Support YVU422
>>   gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
>>   imx-drm: Crtcs moved to device tree
>>   imx-drm: hdmi: optimize i2c write wait
>>   imx-drm: parallel-display: Support RGB666 pixel fmt
>>   imx-drm: imx-ldb: Add debug to connector/encoder entry points
>>   imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()
>>   imx-drm: parallel-display: Fix typo when setting mode type
>>   imx-drm: ipuv3-plane: Fix planar formats
>>   imx-drm: ipuv3-plane: Allow YUV space for background plane
>>   imx-drm: ipuv3-plane: Add more supported pixel formats
>>   imx-drm: ipuv3-plane: Implement global alpha and colorkey properties
>>   imx-drm: hdmi: rework irq request/free
>>   imx-drm: imx-ldb: Add DDC support
>>   imx-drm: Fix separate primary plane objects
>>   imx-drm: Move page flip handling to plane driver
>>   imx-drm: Reset ipu unit pointers to NULL on errors
>>   drm: implement page flipping support for planes
>>   imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs
>>   imx-drm: Implement DRM gamma set
>>   imx-drm: Implement custom ioctl to set gamma
>>   imx-drm: Add support for interface pixel maps
>>   imx-drm: parallel-display: Add interface-pix-map DT property
>>   imx-drm: hdmi: set DI clock source to DI pre clock
>>   imx-drm: ipuv3-crtc: Set the crtc device name
>>   imx-drm: hdmi: Save ipu/di mux for later iomux setup
>>   imx-drm: ipuv3-plane: Assign correct dmfc burst size
>>   drm_modes: videomode: add pos/neg pixel clock polarity flag
>>   imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock
>>     polarity
>>   imx-drm: imx-ldb: Add all defined of video modes
>>   imx-drm: parallel-display: Add all defined of video modes
>>   imx-drm: ipuv3-crtc: Disable fb on crtc unbind
>>   imx-drm: imx-ldb: Use DDC probe as connection detect
>>   imx-drm: ipuv3-crtc: Implement mode_set_base
>>   imx-drm: Cancel pending page flip events at preclose
>>   imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
>>   imx-drm: ipuv3-plane: Enable 8 burst locking
> Cool stuff!
>
> Would you have a git tree we can use for test these?

Hi Fabio, Yes I forgot to mention that in the cover letter:

git@github.com:slongerbeam/drm-next.git

Branch is imx-drm-mentor.

Steve



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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Zubair Lutfullah Kakakhel]

Steve Longerbeam <slongerbeam <at> gmail.com> writes:

> 
> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> except for two patches that affect drm core (patch 53 and 63, see below).
> 
> New features for imx-drm staging driver:
> 
> - Support for multi-display (HDMI and LVDS).
> - Support for global alpha and color-key properties for overlay plane.
> - Support for gamma correction.
> - The imx-drm crtc devices moved to device tree.
> - Support for defining custom display interface pixel mappings in the
>   device tree.
> - Implements encoder DPMS for LVDS.
> - YUV planar pixel formats supported for DRM framebuffers.
> - DDC support added for LVDS.
> - Page flip handling moved to imx plane driver and implemented with
>   IPU double-buffering.
> - Support page-flip in the overlay plane (patch 53 affects drm core).
> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> - Add LVDS connection detect via drm_probe_ddc().
> - Implement crtc mode_set_base using plane page-flip.
> 
> Fixed issues:
> 
> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>   support).
> - Use counter added to IPU DC enable/disable (part of multi-display
>   support).
> - Fixed some HDMI timing issues.
> - Wider range of supported DI pixel clocks generated (all EDID modes
>   reported from HDMI displays now work).
> - Fix separate primary plane objects.
> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>   support).
> - Assign correct DMFC burst size.
> - Resolve some DI synchronous display error cases.
> 

Hi,

Great work on these patches. 
Please cc me on imx-hdmi related patches as well.

We are working on the JZ4780 (Ingenic Xburst/MIPS, not yet pushed 
upstream). It has the same/similar DWC HDMI block in silicon. 

I took the imx-hdmi driver from 3.14 and managed to use the driver with 
almost no modification except for replacing the imx_drm_xxx function calls 
for encoder/connector attach/register. Tested on the MIPS Creator CI20 
board.

Recently, I was looking at understanding the latest code and try to send an 
RFC mail on how to further reduce/break the imx-drm interaction with the 
hdmi driver. Compared to 3.14, the 3.18 driver has fewer imx_drm_xxx calls. 
Which is great.

We will probably have other SoCs in the future using this HDMI block as 
well.

So separating it completely from staging/imx-drm might make sense.
Possibly rename it to dwc_hdmi as well unless people have an objection at 
redundant code churn.

Just thought I'd pop in, highlight a different angle on the hdmi driver 
that will come up in the future, and request to be kept in the loop.

Cheers,
ZubairLK


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Re: [PATCH 05/72] ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
> Select pll3_usb_otg for ldb_di clock for rev 1.0 chips.
> 
> Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
>  arch/arm/mach-imx/clk-imx6q.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 86b58fc..68064a6 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>  	    cpu_is_imx6dl()) {
>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
> +	} else {
> +		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
> +		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
>  	}
>  
>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);

Does the issue with the LDB DI mux glitch locking up the LDB DI divider
also affect rev 1.0 silicon?
(http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268864.html)

We probably shouldn't touch LDB_DIx_SEL here for the other revisions
either. In any case, this would be a patch for the linux-arm-kernel
mailing list.

regards
Philipp

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Re: [PATCH 04/72] ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
> AS pll5_video_div has already been used as clock root for ldb_di,
> so use pll2_pfd0_352m as clock root of ipu_di for HDMI.
> 
> Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>

What about devices that don't use LVDS? It would be nice to let them use
PLL5 for HDMI.

> ---
>  arch/arm/mach-imx/clk-imx6q.c |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
> index 4e79da7..86b58fc 100644
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -483,10 +483,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>  	}
>  
> -	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
> -	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
> -	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
> -	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
> +	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
> +	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
> +	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
> +	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
>  	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);

regards
Philipp

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Re: [PATCH 06/72] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
> Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.
> 
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
>  drivers/gpu/ipu-v3/ipu-cpmem.c |    7 +++++++
>  include/video/imx-ipu-v3.h     |    1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
> index 3bf05bc..2c93e9c 100644
> --- a/drivers/gpu/ipu-v3/ipu-cpmem.c
> +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
> @@ -253,6 +253,13 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
>  }
>  EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
>  
> +void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
> +{
> +	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
> +	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
> +}
> +EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
> +
>  void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
>  {
>  	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
> index c74bf4a..03cda50 100644
> --- a/include/video/imx-ipu-v3.h
> +++ b/include/video/imx-ipu-v3.h
> @@ -195,6 +195,7 @@ void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
>  void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
>  void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
>  void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
> +void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
>  void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
>  void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
>  void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);

Looks good to me, just where this be used where
ipu_cpmem_set_yuv_planar_full can not?

regards
Philipp

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Re: [PATCH 07/72] gpu: ipu-v3: Add ipu_dp_set_chroma_key()

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
> Adds the function ipu_dp_set_chroma_key(), which sets up a color key
> value for a DP foreground plane.
> 
> ipu_dp_set_chroma_key() accepts a color key value in RGB24 format.
> If the combiner unit colorspace is YUV, the key must be converted
> to YUV444, using the same CSC coefficients as programmed in the DP.
> So pull out the CSC coefficients from ipu_dp_csc_init() to make
> them available to rgb24_to_yuv444() that converts to color key.

What is the rationale to disallow specifying the color key in YUV?
Regardless of the new feature, I like the move to static const
coefficient tables. Maybe split that into two patches?

regards
Philipp

> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
>  drivers/gpu/ipu-v3/ipu-dp.c |  121 ++++++++++++++++++++++++++++++++++++-------
>  include/video/imx-ipu-v3.h  |    1 +
>  2 files changed, 103 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
> index 98686ed..e4026f1 100644
> --- a/drivers/gpu/ipu-v3/ipu-dp.c
> +++ b/drivers/gpu/ipu-v3/ipu-dp.c
> @@ -84,6 +84,52 @@ static inline struct ipu_flow *to_flow(struct ipu_dp *dp)
>  		return container_of(dp, struct ipu_flow, background);
>  }
>  
> +static const int rgb2yuv_coeff[5][3] = {
> +	{ 0x0099, 0x012d, 0x003a },
> +	{ 0x03a9, 0x0356, 0x0100 },
> +	{ 0x0100, 0x0329, 0x03d6 },
> +	{ 0x0000, 0x0200, 0x0200 }, /* B0, B1, B2 */
> +	{ 0x2,    0x2,    0x2 },    /* S0, S1, S2 */
> +};
> +
> +static const int yuv2rgb_coeff[5][3] = {
> +	{ 0x0095, 0x0000, 0x00cc },
> +	{ 0x0095, 0x03ce, 0x0398 },
> +	{ 0x0095, 0x00ff, 0x0000 },
> +	{ 0x3e42, 0x010a, 0x3dd6 }, /* B0,B1,B2 */
> +	{ 0x1,    0x1,    0x1 },    /* S0,S1,S2 */
> +};
> +
> +/*
> + * This is used to convert an RGB24 color key to YUV444, using
> + * the same CSC coefficients as programmed in the DP.
> + */
> +static u32 rgb24_to_yuv444(u32 rgb24)
> +{
> +	u32 red, green, blue;
> +	int i, c[3];
> +
> +	red   = (rgb24 >> 16) & 0xff;
> +	green = (rgb24 >>  8) & 0xff;
> +	blue  = (rgb24 >>  0) & 0xff;
> +
> +	for (i = 0; i < 3; i++) {
> +		c[i] = red * rgb2yuv_coeff[i][0];
> +		c[i] += green * rgb2yuv_coeff[i][1];
> +		c[i] += blue * rgb2yuv_coeff[i][2];
> +		c[i] /= 16;
> +		c[i] += rgb2yuv_coeff[3][i] * 4;
> +		c[i] += 8;
> +		c[i] /= 16;
> +		if (c[i] < 0)
> +			c[i] = 0;
> +		if (c[i] > 255)
> +			c[i] = 255;
> +	}
> +
> +	return (c[0] << 16) | (c[1] << 8) | c[2];
> +}
> +
>  int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
>  		u8 alpha, bool bg_chan)
>  {
> @@ -120,6 +166,48 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
>  }
>  EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);
>  
> +/*
> + * The input color_key must always be RGB24. It will be converted to
> + * YUV444 if the pixel format to the Combining unit is YUV space.
> + */
> +int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key)
> +{
> +	struct ipu_flow *flow = to_flow(dp);
> +	struct ipu_dp_priv *priv = flow->priv;
> +	enum ipu_color_space combiner_cs;
> +	u32 reg;
> +
> +	mutex_lock(&priv->mutex);
> +
> +	if (flow->foreground.in_cs == flow->background.in_cs)
> +		combiner_cs = flow->foreground.in_cs;
> +	else
> +		combiner_cs = flow->out_cs;
> +
> +	if (combiner_cs == IPUV3_COLORSPACE_YUV)
> +		color_key = rgb24_to_yuv444(color_key);
> +
> +	color_key &= 0x00ffffff;
> +
> +	if (enable) {
> +		reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & ~0x00FFFFFFL;
> +		writel(reg | color_key, flow->base + DP_GRAPH_WIND_CTRL);
> +
> +		reg = readl(flow->base + DP_COM_CONF);
> +		writel(reg | DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
> +	} else {
> +		reg = readl(flow->base + DP_COM_CONF);
> +		writel(reg & ~DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
> +	}
> +
> +	ipu_srm_dp_sync_update(priv->ipu);
> +
> +	mutex_unlock(&priv->mutex);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(ipu_dp_set_chroma_key);
> +
>  int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
>  {
>  	struct ipu_flow *flow = to_flow(dp);
> @@ -138,6 +226,7 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
>  		enum ipu_color_space out,
>  		u32 place)
>  {
> +	const int (*c)[3];
>  	u32 reg;
>  
>  	reg = readl(flow->base + DP_COM_CONF);
> @@ -148,25 +237,19 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
>  		return;
>  	}
>  
> -	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
> -		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
> -		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
> -		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
> -		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
> -		writel(0x3d6 | (0x0000 << 16) | (2 << 30),
> -				flow->base + DP_CSC_0);
> -		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
> -				flow->base + DP_CSC_1);
> -	} else {
> -		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
> -		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
> -		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
> -		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
> -		writel(0x000 | (0x3e42 << 16) | (1 << 30),
> -				flow->base + DP_CSC_0);
> -		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
> -				flow->base + DP_CSC_1);
> -	}
> +	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV)
> +		c = rgb2yuv_coeff;
> +	else
> +		c = yuv2rgb_coeff;
> +
> +	writel(c[0][0] | (c[0][1] << 16), flow->base + DP_CSC_A_0);
> +	writel(c[0][2] | (c[1][0] << 16), flow->base + DP_CSC_A_1);
> +	writel(c[1][1] | (c[1][2] << 16), flow->base + DP_CSC_A_2);
> +	writel(c[2][0] | (c[2][1] << 16), flow->base + DP_CSC_A_3);
> +	writel(c[2][2] | (c[3][0] << 16) | (c[4][0] << 30),
> +	       flow->base + DP_CSC_0);
> +	writel(c[3][1] | (c[4][1] << 14) | (c[3][2] << 16) | (c[4][2] << 30),
> +	       flow->base + DP_CSC_1);
>  
>  	reg |= place;
>  
> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
> index 03cda50..e878343 100644
> --- a/include/video/imx-ipu-v3.h
> +++ b/include/video/imx-ipu-v3.h
> @@ -273,6 +273,7 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
>  int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
>  int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
>  		bool bg_chan);
> +int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key);
>  
>  /*
>   * IPU CMOS Sensor Interface (csi) functions


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Re: [PATCH 03/72] ARM: dts: imx6qdl: Create imx-drm crtc nodes

[Philipp Zabel]

Hi Steve,

Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
> Create imx-drm crtc device nodes. Each crtc node requires the following
> parameters:
> 
> - parent ipu phandle.
> - di number.
> - port endpoints.
[...]

the crtcs do not belong in the device tree. Currently the crtcs are each
fixed to one of the DIs (the DIs are is what the two IPU output ports in
the device tree describe), but that could be changed, dynamically, with
each modeset.

regards
Philipp


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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

Hi Steve,

On Fri, Oct 31, 2014 at 10:19 PM, Steve Longerbeam
<slongerbeam@gmail.com> wrote:

> Hi Fabio, Yes I forgot to mention that in the cover letter:
>
> git@github.com:slongerbeam/drm-next.git
>
> Branch is imx-drm-mentor.

Just tried it here. There were some dtb file build issues and I just
removed the dtb's that caused issues from the Makefile.

Then I ran the kernel and dtb on a imx6q-sabresd, but no HDMI output
could be seen.
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

On Mon, Nov 3, 2014 at 11:12 AM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Steve,
>
> On Fri, Oct 31, 2014 at 10:19 PM, Steve Longerbeam
> <slongerbeam@gmail.com> wrote:
>
>> Hi Fabio, Yes I forgot to mention that in the cover letter:
>>
>> git@github.com:slongerbeam/drm-next.git
>>
>> Branch is imx-drm-mentor.
>
> Just tried it here. There were some dtb file build issues and I just
> removed the dtb's that caused issues from the Makefile.
>
> Then I ran the kernel and dtb on a imx6q-sabresd, but no HDMI output
> could be seen.

[    2.577748] imx-drm display-subsystem: missing 'ports' property
[    2.585347] imx-ipuv3-crtc imx-ipuv3-crtc.0: missing port@2 node in
/soc/ipu@02400000
[    2.593333] imx-ipuv3-crtc imx-ipuv3-crtc.1: missing port@3 node in
/soc/ipu@02400000
[    2.601312] imx-ipuv3-crtc imx-ipuv3-crtc.4: missing port@2 node in
/soc/ipu@02800000
[    2.609293] imx-ipuv3-crtc imx-ipuv3-crtc.5: missing port@3 node in
/soc/ipu@02800000
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

On Mon, Nov 3, 2014 at 11:12 AM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Steve,
>
> On Fri, Oct 31, 2014 at 10:19 PM, Steve Longerbeam
> <slongerbeam@gmail.com> wrote:
>
>> Hi Fabio, Yes I forgot to mention that in the cover letter:
>>
>> git@github.com:slongerbeam/drm-next.git
>>
>> Branch is imx-drm-mentor.
>
> Just tried it here. There were some dtb file build issues and I just
> removed the dtb's that caused issues from the Makefile.
>
> Then I ran the kernel and dtb on a imx6q-sabresd, but no HDMI output
> could be seen.

Sorry, I was using the wrong kernel. HDMI is fine now.

Will run some tests now. Thanks
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

On Mon, Nov 3, 2014 at 11:20 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Mon, Nov 3, 2014 at 11:12 AM, Fabio Estevam <festevam@gmail.com> wrote:
>> Hi Steve,
>>
>> On Fri, Oct 31, 2014 at 10:19 PM, Steve Longerbeam
>> <slongerbeam@gmail.com> wrote:
>>
>>> Hi Fabio, Yes I forgot to mention that in the cover letter:
>>>
>>> git@github.com:slongerbeam/drm-next.git
>>>
>>> Branch is imx-drm-mentor.
>>
>> Just tried it here. There were some dtb file build issues and I just
>> removed the dtb's that caused issues from the Makefile.
>>
>> Then I ran the kernel and dtb on a imx6q-sabresd, but no HDMI output
>> could be seen.
>
> Sorry, I was using the wrong kernel. HDMI is fine now.
>
> Will run some tests now. Thanks

Some nice improvements that I could notice: now HDMI is detected
correctly when used together with LVDS.

Also, the LVDS picture does not go away when I remove the HDMI connector.

However, the Linux penguins are appearing with incorrect colours on
the LVDS panel of my imx6q-sabresd.

Thanks
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Rob Clark]

On Mon, Nov 3, 2014 at 6:17 AM, Zubair Lutfullah Kakakhel
<Zubair.Kakakhel@imgtec.com> wrote:
> Steve Longerbeam <slongerbeam <at> gmail.com> writes:
>
>>
>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>> except for two patches that affect drm core (patch 53 and 63, see below).
>>
>> New features for imx-drm staging driver:
>>
>> - Support for multi-display (HDMI and LVDS).
>> - Support for global alpha and color-key properties for overlay plane.
>> - Support for gamma correction.
>> - The imx-drm crtc devices moved to device tree.
>> - Support for defining custom display interface pixel mappings in the
>>   device tree.
>> - Implements encoder DPMS for LVDS.
>> - YUV planar pixel formats supported for DRM framebuffers.
>> - DDC support added for LVDS.
>> - Page flip handling moved to imx plane driver and implemented with
>>   IPU double-buffering.
>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>> - Add LVDS connection detect via drm_probe_ddc().
>> - Implement crtc mode_set_base using plane page-flip.
>>
>> Fixed issues:
>>
>> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>>   support).
>> - Use counter added to IPU DC enable/disable (part of multi-display
>>   support).
>> - Fixed some HDMI timing issues.
>> - Wider range of supported DI pixel clocks generated (all EDID modes
>>   reported from HDMI displays now work).
>> - Fix separate primary plane objects.
>> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>>   support).
>> - Assign correct DMFC burst size.
>> - Resolve some DI synchronous display error cases.
>>
>
> Hi,
>
> Great work on these patches.
> Please cc me on imx-hdmi related patches as well.
>
> We are working on the JZ4780 (Ingenic Xburst/MIPS, not yet pushed
> upstream). It has the same/similar DWC HDMI block in silicon.
>
> I took the imx-hdmi driver from 3.14 and managed to use the driver with
> almost no modification except for replacing the imx_drm_xxx function calls
> for encoder/connector attach/register. Tested on the MIPS Creator CI20
> board.
>
> Recently, I was looking at understanding the latest code and try to send an
> RFC mail on how to further reduce/break the imx-drm interaction with the
> hdmi driver. Compared to 3.14, the 3.18 driver has fewer imx_drm_xxx calls.
> Which is great.
>
> We will probably have other SoCs in the future using this HDMI block as
> well.

fwiw, probably worth looking at drm_bridge or drm i2c encoder slave
stuff (for ex. tda998x) for how to split out shared hdmi blocks.  We
have a few drivers currently sharing the tda998x hdmi encoder chip.

BR,
-R


> So separating it completely from staging/imx-drm might make sense.
> Possibly rename it to dwc_hdmi as well unless people have an objection at
> redundant code churn.
>
> Just thought I'd pop in, highlight a different angle on the hdmi driver
> that will come up in the future, and request to be kept in the loop.
>
> Cheers,
> ZubairLK
>
>
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Daniel Vetter]

On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> except for two patches that affect drm core (patch 53 and 63, see below).
> 
> New features for imx-drm staging driver:
> 
> - Support for multi-display (HDMI and LVDS).
> - Support for global alpha and color-key properties for overlay plane.
> - Support for gamma correction.
> - The imx-drm crtc devices moved to device tree.
> - Support for defining custom display interface pixel mappings in the
>   device tree.
> - Implements encoder DPMS for LVDS.
> - YUV planar pixel formats supported for DRM framebuffers.
> - DDC support added for LVDS.
> - Page flip handling moved to imx plane driver and implemented with
>   IPU double-buffering.
> - Support page-flip in the overlay plane (patch 53 affects drm core).
> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> - Add LVDS connection detect via drm_probe_ddc().
> - Implement crtc mode_set_base using plane page-flip.

Isn't the point of staging to get the driver out of it, instead of adding
massive piles of features and continously keeping it there? Greg?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Greg KH]

On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
> > Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> > except for two patches that affect drm core (patch 53 and 63, see below).
> > 
> > New features for imx-drm staging driver:
> > 
> > - Support for multi-display (HDMI and LVDS).
> > - Support for global alpha and color-key properties for overlay plane.
> > - Support for gamma correction.
> > - The imx-drm crtc devices moved to device tree.
> > - Support for defining custom display interface pixel mappings in the
> >   device tree.
> > - Implements encoder DPMS for LVDS.
> > - YUV planar pixel formats supported for DRM framebuffers.
> > - DDC support added for LVDS.
> > - Page flip handling moved to imx plane driver and implemented with
> >   IPU double-buffering.
> > - Support page-flip in the overlay plane (patch 53 affects drm core).
> > - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> > - Add LVDS connection detect via drm_probe_ddc().
> > - Implement crtc mode_set_base using plane page-flip.
> 
> Isn't the point of staging to get the driver out of it, instead of adding
> massive piles of features and continously keeping it there? Greg?

Yes, please don't add new features to this codebase, fix it up so it
gets out of staging first, I'm not going to take any of these (not the
least reason being that I wasn't even cc:ed on them...)

thanks,

greg k-h
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Re: [PATCH 03/72] ARM: dts: imx6qdl: Create imx-drm crtc nodes

[Steve Longerbeam]

On 11/03/2014 04:31 AM, Philipp Zabel wrote:
> Hi Steve,
> 
> Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
>> Create imx-drm crtc device nodes. Each crtc node requires the following
>> parameters:
>>
>> - parent ipu phandle.
>> - di number.
>> - port endpoints.
> [...]
> 
> the crtcs do not belong in the device tree. Currently the crtcs are each
> fixed to one of the DIs (the DIs are is what the two IPU output ports in
> the device tree describe), but that could be changed, dynamically, with
> each modeset.
> 
> 

Hi Philipp, yes currently the crtc's are fixed to a DI. I wasn't aware that
there are future plans to change this.

But I don't see any difference between the crtcs being created in code versus
in the device tree, even with the above new info. In both cases, the assigned
DI could simply be an initial assignment that can be re-assigned on mode changes.

Steve

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Daniel Vetter]

On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
> > On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
> > > Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> > > except for two patches that affect drm core (patch 53 and 63, see below).
> > > 
> > > New features for imx-drm staging driver:
> > > 
> > > - Support for multi-display (HDMI and LVDS).
> > > - Support for global alpha and color-key properties for overlay plane.
> > > - Support for gamma correction.
> > > - The imx-drm crtc devices moved to device tree.
> > > - Support for defining custom display interface pixel mappings in the
> > >   device tree.
> > > - Implements encoder DPMS for LVDS.
> > > - YUV planar pixel formats supported for DRM framebuffers.
> > > - DDC support added for LVDS.
> > > - Page flip handling moved to imx plane driver and implemented with
> > >   IPU double-buffering.
> > > - Support page-flip in the overlay plane (patch 53 affects drm core).
> > > - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> > > - Add LVDS connection detect via drm_probe_ddc().
> > > - Implement crtc mode_set_base using plane page-flip.
> > 
> > Isn't the point of staging to get the driver out of it, instead of adding
> > massive piles of features and continously keeping it there? Greg?
> 
> Yes, please don't add new features to this codebase, fix it up so it
> gets out of staging first, I'm not going to take any of these (not the
> least reason being that I wasn't even cc:ed on them...)

Yeah I think imx works a bit like a driver outside of staging with patches
submitted to the subsystem and reviewed all there like normal. Except it's
not ...
-Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Greg KH]

On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
> > On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
> > > On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
> > > > Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> > > > except for two patches that affect drm core (patch 53 and 63, see below).
> > > > 
> > > > New features for imx-drm staging driver:
> > > > 
> > > > - Support for multi-display (HDMI and LVDS).
> > > > - Support for global alpha and color-key properties for overlay plane.
> > > > - Support for gamma correction.
> > > > - The imx-drm crtc devices moved to device tree.
> > > > - Support for defining custom display interface pixel mappings in the
> > > >   device tree.
> > > > - Implements encoder DPMS for LVDS.
> > > > - YUV planar pixel formats supported for DRM framebuffers.
> > > > - DDC support added for LVDS.
> > > > - Page flip handling moved to imx plane driver and implemented with
> > > >   IPU double-buffering.
> > > > - Support page-flip in the overlay plane (patch 53 affects drm core).
> > > > - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> > > > - Add LVDS connection detect via drm_probe_ddc().
> > > > - Implement crtc mode_set_base using plane page-flip.
> > > 
> > > Isn't the point of staging to get the driver out of it, instead of adding
> > > massive piles of features and continously keeping it there? Greg?
> > 
> > Yes, please don't add new features to this codebase, fix it up so it
> > gets out of staging first, I'm not going to take any of these (not the
> > least reason being that I wasn't even cc:ed on them...)
> 
> Yeah I think imx works a bit like a driver outside of staging with patches
> submitted to the subsystem and reviewed all there like normal. Except it's
> not ...

And I keep taking imx driver patches as well through my staging tree.

Steve, what's the status of getting this driver out of staging?  What is
left to do, and who is doing the work?

thanks,

greg k-h
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 11/03/2014 09:48 AM, Greg KH wrote:
> On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
>> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
>>> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
>>>> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
>>>>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>>>>> except for two patches that affect drm core (patch 53 and 63, see below).
>>>>>
>>>>> New features for imx-drm staging driver:
>>>>>
>>>>> - Support for multi-display (HDMI and LVDS).
>>>>> - Support for global alpha and color-key properties for overlay plane.
>>>>> - Support for gamma correction.
>>>>> - The imx-drm crtc devices moved to device tree.
>>>>> - Support for defining custom display interface pixel mappings in the
>>>>>   device tree.
>>>>> - Implements encoder DPMS for LVDS.
>>>>> - YUV planar pixel formats supported for DRM framebuffers.
>>>>> - DDC support added for LVDS.
>>>>> - Page flip handling moved to imx plane driver and implemented with
>>>>>   IPU double-buffering.
>>>>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>>>>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>>>>> - Add LVDS connection detect via drm_probe_ddc().
>>>>> - Implement crtc mode_set_base using plane page-flip.
>>>> Isn't the point of staging to get the driver out of it, instead of adding
>>>> massive piles of features and continously keeping it there? Greg?
>>> Yes, please don't add new features to this codebase, fix it up so it
>>> gets out of staging first, I'm not going to take any of these (not the
>>> least reason being that I wasn't even cc:ed on them...)
>> Yeah I think imx works a bit like a driver outside of staging with patches
>> submitted to the subsystem and reviewed all there like normal. Except it's
>> not ...
> And I keep taking imx driver patches as well through my staging tree.
>
> Steve, what's the status of getting this driver out of staging?  What is
> left to do, and who is doing the work?

Hi Greg, you should also talk with the original authors (Sascha and
Philipp at Pengutronix), but in my experience, this driver is still suffering
from some chronic IPU issues with data starvation to the display interface.
So from my experience, that is really the only thing that is holding it up.

Steve


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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 11/03/2014 09:48 AM, Greg KH wrote:
> On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
>> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
>>> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
>>>> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
>>>>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>>>>> except for two patches that affect drm core (patch 53 and 63, see below).
>>>>>
>>>>> New features for imx-drm staging driver:
>>>>>
>>>>> - Support for multi-display (HDMI and LVDS).
>>>>> - Support for global alpha and color-key properties for overlay plane.
>>>>> - Support for gamma correction.
>>>>> - The imx-drm crtc devices moved to device tree.
>>>>> - Support for defining custom display interface pixel mappings in the
>>>>>   device tree.
>>>>> - Implements encoder DPMS for LVDS.
>>>>> - YUV planar pixel formats supported for DRM framebuffers.
>>>>> - DDC support added for LVDS.
>>>>> - Page flip handling moved to imx plane driver and implemented with
>>>>>   IPU double-buffering.
>>>>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>>>>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>>>>> - Add LVDS connection detect via drm_probe_ddc().
>>>>> - Implement crtc mode_set_base using plane page-flip.
>>>> Isn't the point of staging to get the driver out of it, instead of adding
>>>> massive piles of features and continously keeping it there? Greg?
>>> Yes, please don't add new features to this codebase, fix it up so it
>>> gets out of staging first, I'm not going to take any of these (not the
>>> least reason being that I wasn't even cc:ed on them...)
>> Yeah I think imx works a bit like a driver outside of staging with patches
>> submitted to the subsystem and reviewed all there like normal. Except it's
>> not ...
> And I keep taking imx driver patches as well through my staging tree.
>
> Steve, what's the status of getting this driver out of staging?  What is
> left to do, and who is doing the work?

Hi Greg, you should also talk with the original authors (Sascha and
Philipp at Pengutronix), but in my experience, this driver is still suffering
from some chronic IPU issues with data starvation to the display interface.
So from my experience, that is really the only thing that is holding it up.

Steve




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Re: [PATCH 04/72] ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di

[Steve Longerbeam]

On 11/03/2014 04:30 AM, Philipp Zabel wrote:
> Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
>> AS pll5_video_div has already been used as clock root for ldb_di,
>> so use pll2_pfd0_352m as clock root of ipu_di for HDMI.
>>
>> Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> What about devices that don't use LVDS? It would be nice to let them use
> PLL5 for HDMI.

Yeah, I agree. Maybe the right approach is to move root PLL selection
into the device tree hdmi and lvds nodes.

Steve

>> ---
>>  arch/arm/mach-imx/clk-imx6q.c |    8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
>> index 4e79da7..86b58fc 100644
>> --- a/arch/arm/mach-imx/clk-imx6q.c
>> +++ b/arch/arm/mach-imx/clk-imx6q.c
>> @@ -483,10 +483,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>>  	}
>>  
>> -	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>> -	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>> -	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>> -	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>> +	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
>> +	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
>> +	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
>> +	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
>>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
>>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
>>  	clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
> regards
> Philipp
>
> _______________________________________________
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-- 
Steve Longerbeam | Senior Embedded Engineer, ESD Services
Mentor Embedded(tm) | 46871 Bayside Parkway, Fremont, CA 94538
P 510.354.5838 | M 408.410.2735

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Re: [PATCH 05/72] ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip

[Steve Longerbeam]

On 11/03/2014 04:30 AM, Philipp Zabel wrote:
> Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
>> Select pll3_usb_otg for ldb_di clock for rev 1.0 chips.
>>
>> Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> ---
>>  arch/arm/mach-imx/clk-imx6q.c |    3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
>> index 86b58fc..68064a6 100644
>> --- a/arch/arm/mach-imx/clk-imx6q.c
>> +++ b/arch/arm/mach-imx/clk-imx6q.c
>> @@ -481,6 +481,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
>>  	    cpu_is_imx6dl()) {
>>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>>  		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
>> +	} else {
>> +		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
>> +		clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
>>  	}
>>  
>>  	clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
> Does the issue with the LDB DI mux glitch locking up the LDB DI divider
> also affect rev 1.0 silicon?
> (http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/268864.html)

I can't say for sure, but I would guess that it does.

Internally we are using Freescale's workaround patch for this problem,
but it has a lot of issues, most of which is that it needs to be incorporated
into the clk API so that the workaround would be applied whenever the
LDB parent mux is changed.

Steve
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

On Mon, Nov 3, 2014 at 4:59 PM, Steve Longerbeam
<steve_longerbeam@mentor.com> wrote:

>> Steve, what's the status of getting this driver out of staging?  What is
>> left to do, and who is doing the work?
>
> Hi Greg, you should also talk with the original authors (Sascha and
> Philipp at Pengutronix), but in my experience, this driver is still suffering
> from some chronic IPU issues with data starvation to the display interface.
> So from my experience, that is really the only thing that is holding it up.

Adding Pengutronix and Russell on Cc.

Care to explain on the " data starvation to the display interface" issue?
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Re: [PATCH 05/72] ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip

[Fabio Estevam]

On Mon, Nov 3, 2014 at 5:17 PM, Steve Longerbeam
<steve_longerbeam@mentor.com> wrote:

> Internally we are using Freescale's workaround patch for this problem,
> but it has a lot of issues, most of which is that it needs to be incorporated
> into the clk API so that the workaround would be applied whenever the
> LDB parent mux is changed.

Could you please post a patch with this approach? It would be really
nice to have this fixed in mainline.
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 11/03/2014 12:00 PM, Fabio Estevam wrote:
> On Mon, Nov 3, 2014 at 4:59 PM, Steve Longerbeam
> <steve_longerbeam@mentor.com> wrote:
>
>>> Steve, what's the status of getting this driver out of staging?  What is
>>> left to do, and who is doing the work?
>> Hi Greg, you should also talk with the original authors (Sascha and
>> Philipp at Pengutronix), but in my experience, this driver is still suffering
>> from some chronic IPU issues with data starvation to the display interface.
>> So from my experience, that is really the only thing that is holding it up.
> Adding Pengutronix and Russell on Cc.
>
> Care to explain on the " data starvation to the display interface" issue?

Hi Fabio, I was referring to the DI synchronous display errors
(IPUx_INT_STAT_10, bits 19 and 20).

Steve

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 11/03/2014 06:13 AM, Fabio Estevam wrote:
> On Mon, Nov 3, 2014 at 11:20 AM, Fabio Estevam <festevam@gmail.com> wrote:
>> On Mon, Nov 3, 2014 at 11:12 AM, Fabio Estevam <festevam@gmail.com> wrote:
>>> Hi Steve,
>>>
>>> On Fri, Oct 31, 2014 at 10:19 PM, Steve Longerbeam
>>> <slongerbeam@gmail.com> wrote:
>>>
>>>> Hi Fabio, Yes I forgot to mention that in the cover letter:
>>>>
>>>> git@github.com:slongerbeam/drm-next.git
>>>>
>>>> Branch is imx-drm-mentor.
>>> Just tried it here. There were some dtb file build issues and I just
>>> removed the dtb's that caused issues from the Makefile.
>>>
>>> Then I ran the kernel and dtb on a imx6q-sabresd, but no HDMI output
>>> could be seen.
>> Sorry, I was using the wrong kernel. HDMI is fine now.
>>
>> Will run some tests now. Thanks
> Some nice improvements that I could notice: now HDMI is detected
> correctly when used together with LVDS.
>
> Also, the LVDS picture does not go away when I remove the HDMI connector.
>
> However, the Linux penguins are appearing with incorrect colours on
> the LVDS panel of my imx6q-sabresd.

Hi Fabio, which panel? The Hannstar or the 1024x600 Okaya 7"
panel?

I have noticed wrong colors using the Okaya panel as well, and it
is fixed by switching to "jeida" 24-bit interface in the DT (along with
1024x600 res and slightly different timings).

I didn't change to jeida 24-bit for Hannstar in the DT because I am
assuming 18-bit and "spwg" ordering is correct for Hannstar, but
maybe I'm wrong. Try switching to jeida 24-bit to see if the colors
are fixed. If so maybe we need to switch to jeida 24-bit for Hannstar
as well.

For reference here are the ldb node settings/timings that work for
the Okaya panel:

&ldb {
        status = "okay";

        lvds-channel@0 {
                fsl,data-mapping = "jeida";
                fsl,data-width = <24>;
                status = "okay";

                display-timings {
                        native-mode = <&timing0>;
                        timing0: nit6x_1024x600 {
                                clock-frequency = <51200000>;
                                hactive = <1024>;
                                vactive = <600>;
                                hback-porch = <220>;
                                hfront-porch = <40>;
                                vback-porch = <20>;
                                vfront-porch = <5>;
                                hsync-len = <60>;
                                vsync-len = <10>;
                        };
                };
        };
};

Steve

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Re: [PATCH 06/72] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

[Steve Longerbeam]

On 11/03/2014 04:30 AM, Philipp Zabel wrote:
> Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
>> Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.
>>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> ---
>>  drivers/gpu/ipu-v3/ipu-cpmem.c |    7 +++++++
>>  include/video/imx-ipu-v3.h     |    1 +
>>  2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
>> index 3bf05bc..2c93e9c 100644
>> --- a/drivers/gpu/ipu-v3/ipu-cpmem.c
>> +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
>> @@ -253,6 +253,13 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
>>  }
>>  EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
>>  
>> +void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
>> +{
>> +	ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
>> +	ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
>> +}
>> +EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
>> +
>>  void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
>>  {
>>  	ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
>> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
>> index c74bf4a..03cda50 100644
>> --- a/include/video/imx-ipu-v3.h
>> +++ b/include/video/imx-ipu-v3.h
>> @@ -195,6 +195,7 @@ void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
>>  void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
>>  void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
>>  void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
>> +void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
>>  void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
>>  void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
>>  void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
> Looks good to me, just where this be used where
> ipu_cpmem_set_yuv_planar_full can not?

It is useful when the U/V offsets are not the "standard" values for
planar formats. For instance for implementing tiling to support
IC output frames larger that 1024x1024. We use this function
in our mem2mem driver to support tiling.

Steve
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Re: [PATCH 07/72] gpu: ipu-v3: Add ipu_dp_set_chroma_key()

[Steve Longerbeam]

On 11/03/2014 04:31 AM, Philipp Zabel wrote:
> Am Freitag, den 31.10.2014, 15:53 -0700 schrieb Steve Longerbeam:
>> Adds the function ipu_dp_set_chroma_key(), which sets up a color key
>> value for a DP foreground plane.
>>
>> ipu_dp_set_chroma_key() accepts a color key value in RGB24 format.
>> If the combiner unit colorspace is YUV, the key must be converted
>> to YUV444, using the same CSC coefficients as programmed in the DP.
>> So pull out the CSC coefficients from ipu_dp_csc_init() to make
>> them available to rgb24_to_yuv444() that converts to color key.
> What is the rationale to disallow specifying the color key in YUV?

The color key passed to ipu_dp_set_chroma_key() has to be in one
colorspace or the other, and the convention from elsewhere seems
to be RGB24. The caller can't know what the colorspace of the Combining
Unit in the DP is set to, so it can't be left to the caller to decide which
colorspace to provide. So the point is, a choice has to be made and the
best choice is an RGB24 color key, the DP can then convert to YUV444
if needed.


> Regardless of the new feature, I like the move to static const
> coefficient tables. Maybe split that into two patches?

Sure, I'll do that.

Steve

> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
>  drivers/gpu/ipu-v3/ipu-dp.c |  121 ++++++++++++++++++++++++++++++++++++-------
>  include/video/imx-ipu-v3.h  |    1 +
>  2 files changed, 103 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
> index 98686ed..e4026f1 100644
> --- a/drivers/gpu/ipu-v3/ipu-dp.c
> +++ b/drivers/gpu/ipu-v3/ipu-dp.c
> @@ -84,6 +84,52 @@ static inline struct ipu_flow *to_flow(struct ipu_dp *dp)
>  		return container_of(dp, struct ipu_flow, background);
>  }
>  
> +static const int rgb2yuv_coeff[5][3] = {
> +	{ 0x0099, 0x012d, 0x003a },
> +	{ 0x03a9, 0x0356, 0x0100 },
> +	{ 0x0100, 0x0329, 0x03d6 },
> +	{ 0x0000, 0x0200, 0x0200 }, /* B0, B1, B2 */
> +	{ 0x2,    0x2,    0x2 },    /* S0, S1, S2 */
> +};
> +
> +static const int yuv2rgb_coeff[5][3] = {
> +	{ 0x0095, 0x0000, 0x00cc },
> +	{ 0x0095, 0x03ce, 0x0398 },
> +	{ 0x0095, 0x00ff, 0x0000 },
> +	{ 0x3e42, 0x010a, 0x3dd6 }, /* B0,B1,B2 */
> +	{ 0x1,    0x1,    0x1 },    /* S0,S1,S2 */
> +};
> +
> +/*
> + * This is used to convert an RGB24 color key to YUV444, using
> + * the same CSC coefficients as programmed in the DP.
> + */
> +static u32 rgb24_to_yuv444(u32 rgb24)
> +{
> +	u32 red, green, blue;
> +	int i, c[3];
> +
> +	red   = (rgb24 >> 16) & 0xff;
> +	green = (rgb24 >>  8) & 0xff;
> +	blue  = (rgb24 >>  0) & 0xff;
> +
> +	for (i = 0; i < 3; i++) {
> +		c[i] = red * rgb2yuv_coeff[i][0];
> +		c[i] += green * rgb2yuv_coeff[i][1];
> +		c[i] += blue * rgb2yuv_coeff[i][2];
> +		c[i] /= 16;
> +		c[i] += rgb2yuv_coeff[3][i] * 4;
> +		c[i] += 8;
> +		c[i] /= 16;
> +		if (c[i] < 0)
> +			c[i] = 0;
> +		if (c[i] > 255)
> +			c[i] = 255;
> +	}
> +
> +	return (c[0] << 16) | (c[1] << 8) | c[2];
> +}
> +
>  int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
>  		u8 alpha, bool bg_chan)
>  {
> @@ -120,6 +166,48 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
>  }
>  EXPORT_SYMBOL_GPL(ipu_dp_set_global_alpha);
>  
> +/*
> + * The input color_key must always be RGB24. It will be converted to
> + * YUV444 if the pixel format to the Combining unit is YUV space.
> + */
> +int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key)
> +{
> +	struct ipu_flow *flow = to_flow(dp);
> +	struct ipu_dp_priv *priv = flow->priv;
> +	enum ipu_color_space combiner_cs;
> +	u32 reg;
> +
> +	mutex_lock(&priv->mutex);
> +
> +	if (flow->foreground.in_cs == flow->background.in_cs)
> +		combiner_cs = flow->foreground.in_cs;
> +	else
> +		combiner_cs = flow->out_cs;
> +
> +	if (combiner_cs == IPUV3_COLORSPACE_YUV)
> +		color_key = rgb24_to_yuv444(color_key);
> +
> +	color_key &= 0x00ffffff;
> +
> +	if (enable) {
> +		reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & ~0x00FFFFFFL;
> +		writel(reg | color_key, flow->base + DP_GRAPH_WIND_CTRL);
> +
> +		reg = readl(flow->base + DP_COM_CONF);
> +		writel(reg | DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
> +	} else {
> +		reg = readl(flow->base + DP_COM_CONF);
> +		writel(reg & ~DP_COM_CONF_GWCKE, flow->base + DP_COM_CONF);
> +	}
> +
> +	ipu_srm_dp_sync_update(priv->ipu);
> +
> +	mutex_unlock(&priv->mutex);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(ipu_dp_set_chroma_key);
> +
>  int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
>  {
>  	struct ipu_flow *flow = to_flow(dp);
> @@ -138,6 +226,7 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
>  		enum ipu_color_space out,
>  		u32 place)
>  {
> +	const int (*c)[3];
>  	u32 reg;
>  
>  	reg = readl(flow->base + DP_COM_CONF);
> @@ -148,25 +237,19 @@ static void ipu_dp_csc_init(struct ipu_flow *flow,
>  		return;
>  	}
>  
> -	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV) {
> -		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);
> -		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);
> -		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);
> -		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);
> -		writel(0x3d6 | (0x0000 << 16) | (2 << 30),
> -				flow->base + DP_CSC_0);
> -		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),
> -				flow->base + DP_CSC_1);
> -	} else {
> -		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);
> -		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);
> -		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);
> -		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);
> -		writel(0x000 | (0x3e42 << 16) | (1 << 30),
> -				flow->base + DP_CSC_0);
> -		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),
> -				flow->base + DP_CSC_1);
> -	}
> +	if (in == IPUV3_COLORSPACE_RGB && out == IPUV3_COLORSPACE_YUV)
> +		c = rgb2yuv_coeff;
> +	else
> +		c = yuv2rgb_coeff;
> +
> +	writel(c[0][0] | (c[0][1] << 16), flow->base + DP_CSC_A_0);
> +	writel(c[0][2] | (c[1][0] << 16), flow->base + DP_CSC_A_1);
> +	writel(c[1][1] | (c[1][2] << 16), flow->base + DP_CSC_A_2);
> +	writel(c[2][0] | (c[2][1] << 16), flow->base + DP_CSC_A_3);
> +	writel(c[2][2] | (c[3][0] << 16) | (c[4][0] << 30),
> +	       flow->base + DP_CSC_0);
> +	writel(c[3][1] | (c[4][1] << 14) | (c[3][2] << 16) | (c[4][2] << 30),
> +	       flow->base + DP_CSC_1);
>  
>  	reg |= place;
>  
> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
> index 03cda50..e878343 100644
> --- a/include/video/imx-ipu-v3.h
> +++ b/include/video/imx-ipu-v3.h
> @@ -273,6 +273,7 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
>  int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
>  int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
>  		bool bg_chan);
> +int ipu_dp_set_chroma_key(struct ipu_dp *dp, bool enable, u32 color_key);
>  
>  /*
>   * IPU CMOS Sensor Interface (csi) functions
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel


-- 
Steve Longerbeam | Senior Embedded Engineer, ESD Services
Mentor Embedded(tm) | 46871 Bayside Parkway, Fremont, CA 94538
P 510.354.5838 | M 408.410.2735

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Alex Deucher]

On Mon, Nov 3, 2014 at 1:58 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
> On 11/03/2014 09:48 AM, Greg KH wrote:
>> On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
>>> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
>>>> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
>>>>> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
>>>>>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>>>>>> except for two patches that affect drm core (patch 53 and 63, see below).
>>>>>>
>>>>>> New features for imx-drm staging driver:
>>>>>>
>>>>>> - Support for multi-display (HDMI and LVDS).
>>>>>> - Support for global alpha and color-key properties for overlay plane.
>>>>>> - Support for gamma correction.
>>>>>> - The imx-drm crtc devices moved to device tree.
>>>>>> - Support for defining custom display interface pixel mappings in the
>>>>>>   device tree.
>>>>>> - Implements encoder DPMS for LVDS.
>>>>>> - YUV planar pixel formats supported for DRM framebuffers.
>>>>>> - DDC support added for LVDS.
>>>>>> - Page flip handling moved to imx plane driver and implemented with
>>>>>>   IPU double-buffering.
>>>>>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>>>>>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>>>>>> - Add LVDS connection detect via drm_probe_ddc().
>>>>>> - Implement crtc mode_set_base using plane page-flip.
>>>>> Isn't the point of staging to get the driver out of it, instead of adding
>>>>> massive piles of features and continously keeping it there? Greg?
>>>> Yes, please don't add new features to this codebase, fix it up so it
>>>> gets out of staging first, I'm not going to take any of these (not the
>>>> least reason being that I wasn't even cc:ed on them...)
>>> Yeah I think imx works a bit like a driver outside of staging with patches
>>> submitted to the subsystem and reviewed all there like normal. Except it's
>>> not ...
>> And I keep taking imx driver patches as well through my staging tree.
>>
>> Steve, what's the status of getting this driver out of staging?  What is
>> left to do, and who is doing the work?
>
> Hi Greg, you should also talk with the original authors (Sascha and
> Philipp at Pengutronix), but in my experience, this driver is still suffering
> from some chronic IPU issues with data starvation to the display interface.
> So from my experience, that is really the only thing that is holding it up.

I'm not familiar with the hw in question, but that sounds like more of
a driver optimization that needs to be done than something keeping the
driver in staging.

Alex
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Re: [PATCH 05/72] ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip

[Steve Longerbeam]

On 11/03/2014 12:06 PM, Fabio Estevam wrote:
> On Mon, Nov 3, 2014 at 5:17 PM, Steve Longerbeam
> <steve_longerbeam@mentor.com> wrote:
>
>> Internally we are using Freescale's workaround patch for this problem,
>> but it has a lot of issues, most of which is that it needs to be incorporated
>> into the clk API so that the workaround would be applied whenever the
>> LDB parent mux is changed.
> Could you please post a patch with this approach? It would be really
> nice to have this fixed in mainline.


Hmm, well I reviewed the Freescale patch again, and it won't be so
simple. The patch assumes the ldb_di_clk_sel mux is set to the reset
default mmdc_ch1_axi source, and that's a central premise of the whole
patch. When the workaround is folded into the clk set_parent ops, this
assumption can't be made any more.

I'm not sure I can capably generalize this patch to switch away from any
of the mux sources to any other, avoiding glitch generation, given that there
appears to be so many undocumented pieces in the CCM module. Is there
someone at Freescale who can take this on?

Steve

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Philipp Zabel]

Hi,

Am Montag, den 03.11.2014, 10:59 -0800 schrieb Steve Longerbeam:
> On 11/03/2014 09:48 AM, Greg KH wrote:
> > On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
> >> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
> >>> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
> >>>> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
> >>>>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> >>>>> except for two patches that affect drm core (patch 53 and 63, see below).
> >>>>>
> >>>>> New features for imx-drm staging driver:
> >>>>>
> >>>>> - Support for multi-display (HDMI and LVDS).
> >>>>> - Support for global alpha and color-key properties for overlay plane.
> >>>>> - Support for gamma correction.
> >>>>> - The imx-drm crtc devices moved to device tree.
> >>>>> - Support for defining custom display interface pixel mappings in the
> >>>>>   device tree.
> >>>>> - Implements encoder DPMS for LVDS.
> >>>>> - YUV planar pixel formats supported for DRM framebuffers.
> >>>>> - DDC support added for LVDS.
> >>>>> - Page flip handling moved to imx plane driver and implemented with
> >>>>>   IPU double-buffering.
> >>>>> - Support page-flip in the overlay plane (patch 53 affects drm core).
> >>>>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> >>>>> - Add LVDS connection detect via drm_probe_ddc().
> >>>>> - Implement crtc mode_set_base using plane page-flip.
> >>>> Isn't the point of staging to get the driver out of it, instead of adding
> >>>> massive piles of features and continously keeping it there? Greg?
> >>> Yes, please don't add new features to this codebase, fix it up so it
> >>> gets out of staging first, I'm not going to take any of these (not the
> >>> least reason being that I wasn't even cc:ed on them...)
> >> Yeah I think imx works a bit like a driver outside of staging with patches
> >> submitted to the subsystem and reviewed all there like normal. Except it's
> >> not ...
> > And I keep taking imx driver patches as well through my staging tree.
> >
> > Steve, what's the status of getting this driver out of staging?  What is
> > left to do, and who is doing the work?
> 
> Hi Greg, you should also talk with the original authors (Sascha and
> Philipp at Pengutronix), but in my experience, this driver is still suffering
> from some chronic IPU issues with data starvation to the display interface.
> So from my experience, that is really the only thing that is holding it up.

I hadn't realized that Russell decided to step away from his imx-drm
submission effort. I'd like to take it on, and I'd also like to start by
moving it out of staging first so we have a single place to push patches
to again.
I'll submit a MAINTAINERS entry, so that I'll be put on Cc: for related
patches.

Steve, it would be generally helpful if you could spread your
submissions out a bit over time and separate the fixes from the
features. Regarding your current series, which are the critical patches
you think should be applied to staging before moving imx-drm out of it?
In either case I'll keep going over it the next few days, but maybe you
could hilight the important fixes by resending just them (the locking,
DMA burst and irq ordering related patches seem to be candidates).

regards
Philipp

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

Hi Steve,

On Mon, Nov 3, 2014 at 8:41 PM, Steve Longerbeam
<steve_longerbeam@mentor.com> wrote:

> Hi Fabio, which panel? The Hannstar or the 1024x600 Okaya 7"
> panel?

I am using the Hannstar.

>
> I have noticed wrong colors using the Okaya panel as well, and it
> is fixed by switching to "jeida" 24-bit interface in the DT (along with
> 1024x600 res and slightly different timings).
>
> I didn't change to jeida 24-bit for Hannstar in the DT because I am
> assuming 18-bit and "spwg" ordering is correct for Hannstar, but
> maybe I'm wrong. Try switching to jeida 24-bit to see if the colors
> are fixed. If so maybe we need to switch to jeida 24-bit for Hannstar
> as well.

I followed your suggestion and with the change below the Hannstar
display shows the correct colours:

--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -497,8 +497,8 @@
        status = "okay";

        lvds-channel@1 {
-               fsl,data-mapping = "spwg";
-               fsl,data-width = <18>;
+               fsl,data-mapping = "jeida";
+               fsl,data-width = <24>;
                status = "okay";

                display-timings {

Thanks
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Re: [PATCH 19/72] gpu: ipu-v3: Protect more CM reg access with IPU lock

[Philipp Zabel]

Hi Steve,

Am Freitag, den 31.10.2014, 15:54 -0700 schrieb Steve Longerbeam:
> Some cm_reg accesses were not being protected by the IPU spin lock.
>
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
> ---
>  drivers/gpu/ipu-v3/ipu-common.c |   22 ++++++++++++++++++++--
>  1 file changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
> index f707d25..d3af206 100644
> --- a/drivers/gpu/ipu-v3/ipu-common.c
> +++ b/drivers/gpu/ipu-v3/ipu-common.c
> @@ -46,11 +46,16 @@ static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
>  
>  void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
>  {
> +	unsigned long flags;
>  	u32 val;
>  
> +	spin_lock_irqsave(&ipu->lock, flags);
> +
>  	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
>  	val |= 0x8;
>  	ipu_cm_write(ipu, val, IPU_SRM_PRI2);
> +
> +	spin_unlock_irqrestore(&ipu->lock, flags);
>  }
>  EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);

This is the only place this register touched, only bit 3 is ever enabled
by software. This lock is not needed.

> @@ -451,8 +456,17 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
>  {
>  	struct ipu_soc *ipu = channel->ipu;
>  	unsigned int chno = channel->num;
> +	unsigned long flags;
> +	int ret;
> +
> +	spin_lock_irqsave(&ipu->lock, flags);
>  
> -	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
> +	ret = (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ?
> +		1 : 0;
> +
> +	spin_unlock_irqrestore(&ipu->lock, flags);
> +
> +	return ret;

Dito. This register isn't written partially multiple times under the
spinlock anywhere, so there is no gain from this lock around a register
read.

>  }
>  EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
>  
> @@ -569,10 +583,14 @@ EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
>  
>  int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
>  {
> -	unsigned long timeout;
> +	unsigned long flags, timeout;
>  
>  	timeout = jiffies + msecs_to_jiffies(ms);
> +
> +	spin_lock_irqsave(&ipu->lock, flags);
>  	ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
> +	spin_unlock_irqrestore(&ipu->lock, flags);
> +
>  	while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
>  		if (time_after(jiffies, timeout))
>  			return -ETIMEDOUT;

This is a write to clear register, the only other place it is accessed
is by the regmap irq handler. Can you think of a scenario where this
lock would protect anything?

regards
Philipp

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Re: [PATCH 49/72] imx-drm: imx-ldb: Add DDC support

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:54 -0700 schrieb Steve Longerbeam:
> Add support for reading EDID over Display Data Channel. If no DDC
> adapter is available, falls back to hardcoded EDID or display-timings
> node as before.
> 
> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

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Re: [PATCH 68/72] imx-drm: imx-ldb: Use DDC probe as connection detect

[Philipp Zabel]

Am Freitag, den 31.10.2014, 15:54 -0700 schrieb Steve Longerbeam:
> If a ddc node was specified in the device tree, use it in
> imx_ldb_connector_detect() to probe the ddc with drm_probe_ddc(), if
> the result is success, we know there is a display connected so return
> connected status. Otherwise (no ddc specified in DT) we just have to
> assume connected status.

This is a nice trick, unless of course you have a board with multiple
possible panels, not all of them including the EDID EEPROM. In that case
I guess ddc channel property + fallback timing in DT could always report
a connected panel.

regards
Philipp

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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Steve Longerbeam]

On 11/04/2014 01:35 AM, Philipp Zabel wrote:
> Hi,
>
> Am Montag, den 03.11.2014, 10:59 -0800 schrieb Steve Longerbeam:
>> On 11/03/2014 09:48 AM, Greg KH wrote:
>>> On Mon, Nov 03, 2014 at 06:17:28PM +0100, Daniel Vetter wrote:
>>>> On Mon, Nov 03, 2014 at 08:14:23AM -0800, Greg KH wrote:
>>>>> On Mon, Nov 03, 2014 at 05:12:14PM +0100, Daniel Vetter wrote:
>>>>>> On Fri, Oct 31, 2014 at 03:53:43PM -0700, Steve Longerbeam wrote:
>>>>>>> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
>>>>>>> except for two patches that affect drm core (patch 53 and 63, see below).
>>>>>>>
>>>>>>> New features for imx-drm staging driver:
>>>>>>>
>>>>>>> - Support for multi-display (HDMI and LVDS).
>>>>>>> - Support for global alpha and color-key properties for overlay plane.
>>>>>>> - Support for gamma correction.
>>>>>>> - The imx-drm crtc devices moved to device tree.
>>>>>>> - Support for defining custom display interface pixel mappings in the
>>>>>>>   device tree.
>>>>>>> - Implements encoder DPMS for LVDS.
>>>>>>> - YUV planar pixel formats supported for DRM framebuffers.
>>>>>>> - DDC support added for LVDS.
>>>>>>> - Page flip handling moved to imx plane driver and implemented with
>>>>>>>   IPU double-buffering.
>>>>>>> - Support page-flip in the overlay plane (patch 53 affects drm core).
>>>>>>> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
>>>>>>> - Add LVDS connection detect via drm_probe_ddc().
>>>>>>> - Implement crtc mode_set_base using plane page-flip.
>>>>>> Isn't the point of staging to get the driver out of it, instead of adding
>>>>>> massive piles of features and continously keeping it there? Greg?
>>>>> Yes, please don't add new features to this codebase, fix it up so it
>>>>> gets out of staging first, I'm not going to take any of these (not the
>>>>> least reason being that I wasn't even cc:ed on them...)
>>>> Yeah I think imx works a bit like a driver outside of staging with patches
>>>> submitted to the subsystem and reviewed all there like normal. Except it's
>>>> not ...
>>> And I keep taking imx driver patches as well through my staging tree.
>>>
>>> Steve, what's the status of getting this driver out of staging?  What is
>>> left to do, and who is doing the work?
>> Hi Greg, you should also talk with the original authors (Sascha and
>> Philipp at Pengutronix), but in my experience, this driver is still suffering
>> from some chronic IPU issues with data starvation to the display interface.
>> So from my experience, that is really the only thing that is holding it up.
> I hadn't realized that Russell decided to step away from his imx-drm
> submission effort. I'd like to take it on, and I'd also like to start by
> moving it out of staging first so we have a single place to push patches
> to again.
> I'll submit a MAINTAINERS entry, so that I'll be put on Cc: for related
> patches.
>
> Steve, it would be generally helpful if you could spread your
> submissions out a bit over time and separate the fixes from the
> features. Regarding your current series, which are the critical patches
> you think should be applied to staging before moving imx-drm out of it?

Well, if you think imx-drm is ready to be moved out of staging, then
let's do that first. I will resubmit the imx-drm patches after the move
is merged.

In the meantime I will go ahead and resubmit only the IPU patches.

> In either case I'll keep going over it the next few days, but maybe you
> could hilight the important fixes by resending just them (the locking,
> DMA burst and irq ordering related patches seem to be candidates).

The fixes that are important in terms of multi-display, upping channel
priorities, stability (irq ordering, locking), and better video mode support
are:

ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
gpu: ipu-v3: Implement use counter for ipu_dc_enable(), ipu_dc_disable()
gpu: ipu-v3: Split out DI clock enable/disable
gpu: ipu-v3: Protect more CM reg access with IPU lock
gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
gpu: ipu-di: Set rate of DI pre clock
imx-drm: hdmi: rework irq request/free
imx-drm: hdmi: set DI clock source to DI pre clock
imx-drm: ipuv3-plane: Assign correct dmfc burst size
imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
imx-drm: ipuv3-plane: Enable 8 burst locking


But in any case, I'd prefer if we just wait until imx-drm is moved
and then I will resubmit the imx-drm patches, and in the meantime
I will go ahead and resubmit only the IPU patches.


Steve

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Re: [PATCH 19/72] gpu: ipu-v3: Protect more CM reg access with IPU lock

[Steve Longerbeam]

On 11/04/2014 09:51 AM, Philipp Zabel wrote:
> Hi Steve,
>
> Am Freitag, den 31.10.2014, 15:54 -0700 schrieb Steve Longerbeam:
>> Some cm_reg accesses were not being protected by the IPU spin lock.
>>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> ---
>>  drivers/gpu/ipu-v3/ipu-common.c |   22 ++++++++++++++++++++--
>>  1 file changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
>> index f707d25..d3af206 100644
>> --- a/drivers/gpu/ipu-v3/ipu-common.c
>> +++ b/drivers/gpu/ipu-v3/ipu-common.c
>> @@ -46,11 +46,16 @@ static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
>>  
>>  void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
>>  {
>> +	unsigned long flags;
>>  	u32 val;
>>  
>> +	spin_lock_irqsave(&ipu->lock, flags);
>> +
>>  	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
>>  	val |= 0x8;
>>  	ipu_cm_write(ipu, val, IPU_SRM_PRI2);
>> +
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>>  }
>>  EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
> This is the only place this register touched, only bit 3 is ever enabled
> by software. This lock is not needed.

yes, I verified that too. Never mind then.

>> @@ -451,8 +456,17 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
>>  {
>>  	struct ipu_soc *ipu = channel->ipu;
>>  	unsigned int chno = channel->num;
>> +	unsigned long flags;
>> +	int ret;
>> +
>> +	spin_lock_irqsave(&ipu->lock, flags);
>>  
>> -	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
>> +	ret = (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ?
>> +		1 : 0;
>> +
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>> +
>> +	return ret;
> Dito. This register isn't written partially multiple times under the
> spinlock anywhere, so there is no gain from this lock around a register
> read.

Well, I was thinking get_current_buffer could race with
reset_current_buffer, but these functions are doing plain
readl() and writel() (i.e. not read-modify-write), so they
are atomic operations. So never mind this either.

>>  }
>>  EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
>>  
>> @@ -569,10 +583,14 @@ EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
>>  
>>  int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
>>  {
>> -	unsigned long timeout;
>> +	unsigned long flags, timeout;
>>  
>>  	timeout = jiffies + msecs_to_jiffies(ms);
>> +
>> +	spin_lock_irqsave(&ipu->lock, flags);
>>  	ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>> +
>>  	while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
>>  		if (time_after(jiffies, timeout))
>>  			return -ETIMEDOUT;
> This is a write to clear register, the only other place it is accessed
> is by the regmap irq handler. Can you think of a scenario where this
> lock would protect anything?

In this case I do see potential problems. What if thread A calls
ipu_wait_interrupt() while thread B is currently looping through
irq status bits in ipu_irq_handle()? A has now cleared an irq status
before B has had a chance to get to that status bit. Thus the irq
status is missed and the irq not handled. That being said this patch
will not fix the problem because ipu_wait_interrupt() and ipu_irq_handle()
are under different locks.

Maybe the solution is to verify ipu_wait_interrupt() is never called
on enabled irqs so that it doesn't interfere with irq handling. But I
don't know that that is true, is it?

Steve


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Re: [PATCH 19/72] gpu: ipu-v3: Protect more CM reg access with IPU lock

[Steve Longerbeam]

On 11/04/2014 09:51 AM, Philipp Zabel wrote:
> Hi Steve,
>
> Am Freitag, den 31.10.2014, 15:54 -0700 schrieb Steve Longerbeam:
>> Some cm_reg accesses were not being protected by the IPU spin lock.
>>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> ---
>>  drivers/gpu/ipu-v3/ipu-common.c |   22 ++++++++++++++++++++--
>>  1 file changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
>> index f707d25..d3af206 100644
>> --- a/drivers/gpu/ipu-v3/ipu-common.c
>> +++ b/drivers/gpu/ipu-v3/ipu-common.c
>> @@ -46,11 +46,16 @@ static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
>>  
>>  void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
>>  {
>> +	unsigned long flags;
>>  	u32 val;
>>  
>> +	spin_lock_irqsave(&ipu->lock, flags);
>> +
>>  	val = ipu_cm_read(ipu, IPU_SRM_PRI2);
>>  	val |= 0x8;
>>  	ipu_cm_write(ipu, val, IPU_SRM_PRI2);
>> +
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>>  }
>>  EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
> This is the only place this register touched, only bit 3 is ever enabled
> by software. This lock is not needed.

yes, I verified that too. Never mind then.

>> @@ -451,8 +456,17 @@ int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
>>  {
>>  	struct ipu_soc *ipu = channel->ipu;
>>  	unsigned int chno = channel->num;
>> +	unsigned long flags;
>> +	int ret;
>> +
>> +	spin_lock_irqsave(&ipu->lock, flags);
>>  
>> -	return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
>> +	ret = (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ?
>> +		1 : 0;
>> +
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>> +
>> +	return ret;
> Dito. This register isn't written partially multiple times under the
> spinlock anywhere, so there is no gain from this lock around a register
> read.

Well, I was thinking get_current_buffer could race with
reset_current_buffer, but these functions are doing plain
readl() and writel() (i.e. not read-modify-write), so they
are atomic operations. So never mind this either.

>>  }
>>  EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
>>  
>> @@ -569,10 +583,14 @@ EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
>>  
>>  int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
>>  {
>> -	unsigned long timeout;
>> +	unsigned long flags, timeout;
>>  
>>  	timeout = jiffies + msecs_to_jiffies(ms);
>> +
>> +	spin_lock_irqsave(&ipu->lock, flags);
>>  	ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
>> +	spin_unlock_irqrestore(&ipu->lock, flags);
>> +
>>  	while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
>>  		if (time_after(jiffies, timeout))
>>  			return -ETIMEDOUT;
> This is a write to clear register, the only other place it is accessed
> is by the regmap irq handler. Can you think of a scenario where this
> lock would protect anything?

In this case I do see potential problems. What if thread A calls
ipu_wait_interrupt() while thread B is currently looping through
irq status bits in ipu_irq_handle()? A has now cleared an irq status
before B has had a chance to get to that status bit. Thus the irq
status is missed and the irq not handled. That being said this patch
will not fix the problem because ipu_wait_interrupt() and ipu_irq_handle()
are under different locks.

Maybe the solution is to verify ipu_wait_interrupt() is never called
on enabled irqs so that it doesn't interfere with irq handling. But I
don't know that that is true, is it?

Steve



-- 
Steve Longerbeam | Senior Embedded Engineer, ESD Services
Mentor Embedded(tm) | 46871 Bayside Parkway, Fremont, CA 94538
P 510.354.5838 | M 408.410.2735
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Fabio Estevam]

Hi Steve,

On Tue, Nov 4, 2014 at 11:20 PM, Steve Longerbeam
<steve_longerbeam@mentor.com> wrote:

> Well, if you think imx-drm is ready to be moved out of staging, then
> let's do that first. I will resubmit the imx-drm patches after the move
> is merged.
> The fixes that are important in terms of multi-display, upping channel
> priorities, stability (irq ordering, locking), and better video mode support
> are:

Yes, these are all very good material.

>
> ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
> gpu: ipu-v3: Implement use counter for ipu_dc_enable(), ipu_dc_disable()
> gpu: ipu-v3: Split out DI clock enable/disable
> gpu: ipu-v3: Protect more CM reg access with IPU lock
> gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
> gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
> gpu: ipu-di: Set rate of DI pre clock
> imx-drm: hdmi: rework irq request/free
> imx-drm: hdmi: set DI clock source to DI pre clock
> imx-drm: ipuv3-plane: Assign correct dmfc burst size
> imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
> imx-drm: ipuv3-plane: Enable 8 burst locking
>
>
> But in any case, I'd prefer if we just wait until imx-drm is moved
> and then I will resubmit the imx-drm patches, and in the meantime
> I will go ahead and resubmit only the IPU patches.

imx-drm has moved out of staging. Do you plan to re-submit this series?

Thanks,

Fabio Estevam
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Re: [PATCH 00/72] staging imx-drm new features and fixes

[Rob Clark]

On Fri, Oct 31, 2014 at 6:53 PM, Steve Longerbeam <slongerbeam@gmail.com> wrote:
> Hi, this affects only Freescale imx IPU and imx-drm staging drivers,
> except for two patches that affect drm core (patch 53 and 63, see below).
>
> New features for imx-drm staging driver:
>
> - Support for multi-display (HDMI and LVDS).
> - Support for global alpha and color-key properties for overlay plane.
> - Support for gamma correction.
> - The imx-drm crtc devices moved to device tree.
> - Support for defining custom display interface pixel mappings in the
>   device tree.
> - Implements encoder DPMS for LVDS.
> - YUV planar pixel formats supported for DRM framebuffers.
> - DDC support added for LVDS.
> - Page flip handling moved to imx plane driver and implemented with
>   IPU double-buffering.
> - Support page-flip in the overlay plane (patch 53 affects drm core).
> - Add support for parsing pixel clock edge select (patch 63 affects drm core).
> - Add LVDS connection detect via drm_probe_ddc().
> - Implement crtc mode_set_base using plane page-flip.
>
>
> Fixed issues:
>
> - HDMI and LVDS now use different PLL clock roots (part of multi-display
>   support).
> - Use counter added to IPU DC enable/disable (part of multi-display
>   support).
> - Fixed some HDMI timing issues.
> - Wider range of supported DI pixel clocks generated (all EDID modes
>   reported from HDMI displays now work).
> - Fix separate primary plane objects.
> - HDMI must select DI pre clock as DI clock parent during encoder prepare
>   (LVDS may have switched DI clock to LDB parent, part of multi-display
>   support).
> - Assign correct DMFC burst size.
> - Resolve some DI synchronous display error cases.
>

btw, I've seen some reports (on #fedora-arm) about various imx boards
(like wandboard) being finicky when it comes to probing edid.  It
looks like imx-drm just uses a SoC i2c for ddc channel, so maybe this
is more of an imx i2c issue.  Not sure if anyone is already aware of
this issue or debugging it.. but seems like I should let *someone*
know about it ;-)

BR,
-R


>
>
> George G. Davis (1):
>   ARM: dts: imx6qdl-sabreauto: Add HDMI device
>
> Jiada Wang (1):
>   gpu: ipu-v3: fix HDMI timing issues
>
> Steve Longerbeam (70):
>   ARM: dts: imx6qdl-sabrelite: Add HDMI device
>   ARM: dts: imx6qdl: Create imx-drm crtc nodes
>   ARM: i.MX6: use pll2_pfd0_352m as clock root of ipu_di
>   ARM: i.MX6: select pll3_usb_otg for ldb_di for rev 1.0 chip
>   gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()
>   gpu: ipu-v3: Add ipu_dp_set_chroma_key()
>   gpu: ipu-v3: Add ipu_dp_set_gamma_correction()
>   gpu: ipu-v3: Add support for dynamic DC interface pixel maps
>   gpu: ipu-v3: Add ipu_dc_uninit_sync()
>   gpu: ipu-v3: Pass struct ipu_dc to enable/disable
>   gpu: ipu-v3: Add ipu_dp_uninit_channel()
>   gpu: ipu-v3: Pass struct ipu_dp to enable/disable
>   gpu: ipu-v3: Implement use counter for ipu_dc_enable(),
>     ipu_dc_disable()
>   gpu: ipu-v3: Add DMFC/DP/DC/DI module enable/disable debug
>   gpu: ipu-v3: Add ipu_di_uninit_sync_panel()
>   gpu: ipu-v3: Split out DI clock enable/disable
>   gpu: ipu-v3: Protect more CM reg access with IPU lock
>   gpu: ipu-v3: Move DI waveform counter enable/disable to ipu-di
>   gpu: ipu-v3: Update DP sync SRM always in ipu_dp_enable_channel()
>   gpu: ipu-v3: Fix indent/ws in ipu-dmfc
>   gpu: ipu-v3: Allow burstsize of 20 in ipu_dmfc_setup_channel()
>   gpu: ipu-v3: Remove ipu_dmfc_init_channel()
>   gpu: ipu-v3: Consolidate mutex lock in ipu_dmfc_alloc_bandwidth()
>   gpu: ipu-v3: Enumerate the DC channel names
>   gpu: ipu-di: Move ipu pointer init
>   gpu: ipu-di: Add and improve debug/error messages
>   gpu: ipu-v3: Change signal names in struct ipu_di_signal_cfg
>   gpu: ipu-v3: Remove IPU client registration
>   gpu: ipu-di: Set rate of DI pre clock
>   gpu: ipu-v3: Add RGB666 interface pixel map
>   gpu: ipu-cpmem: Pass drm fourcc to ipu_cpmem_set_yuv_*
>   gpu: ipu-v3: Add ipu_drm_fourcc_is_planar()
>   gpu: ipu-v3: Add IDMA channel linking support
>   gpu: ipu-cpmem: Support YVU422
>   gpu: ipu-cpmem: Add ipu_cpmem_get_burstsize()
>   imx-drm: Crtcs moved to device tree
>   imx-drm: hdmi: optimize i2c write wait
>   imx-drm: parallel-display: Support RGB666 pixel fmt
>   imx-drm: imx-ldb: Add debug to connector/encoder entry points
>   imx-drm: imx-ldb: Implement imx_ldb_encoder_dpms()
>   imx-drm: parallel-display: Fix typo when setting mode type
>   imx-drm: ipuv3-plane: Fix planar formats
>   imx-drm: ipuv3-plane: Allow YUV space for background plane
>   imx-drm: ipuv3-plane: Add more supported pixel formats
>   imx-drm: ipuv3-plane: Implement global alpha and colorkey properties
>   imx-drm: hdmi: rework irq request/free
>   imx-drm: imx-ldb: Add DDC support
>   imx-drm: Fix separate primary plane objects
>   imx-drm: Move page flip handling to plane driver
>   imx-drm: Reset ipu unit pointers to NULL on errors
>   drm: implement page flipping support for planes
>   imx-drm: ipuv3-plane: Assign page_flip method to drm_plane_funcs
>   imx-drm: Implement DRM gamma set
>   imx-drm: Implement custom ioctl to set gamma
>   imx-drm: Add support for interface pixel maps
>   imx-drm: parallel-display: Add interface-pix-map DT property
>   imx-drm: hdmi: set DI clock source to DI pre clock
>   imx-drm: ipuv3-crtc: Set the crtc device name
>   imx-drm: hdmi: Save ipu/di mux for later iomux setup
>   imx-drm: ipuv3-plane: Assign correct dmfc burst size
>   drm_modes: videomode: add pos/neg pixel clock polarity flag
>   imx-drm: ipuv3-crtc: Use DRM mode flags to configure pixel clock
>     polarity
>   imx-drm: imx-ldb: Add all defined of video modes
>   imx-drm: parallel-display: Add all defined of video modes
>   imx-drm: ipuv3-crtc: Disable fb on crtc unbind
>   imx-drm: imx-ldb: Use DDC probe as connection detect
>   imx-drm: ipuv3-crtc: Implement mode_set_base
>   imx-drm: Cancel pending page flip events at preclose
>   imx-drm: ipuv3-crtc: Disable overlay plane during crtc disable
>   imx-drm: ipuv3-plane: Enable 8 burst locking
>
>  .../bindings/staging/imx-drm/fsl-imx-drm.txt       |   43 +-
>  arch/arm/boot/dts/imx6dl.dtsi                      |   10 +-
>  arch/arm/boot/dts/imx6q.dtsi                       |  128 +++--
>  arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           |    5 +
>  arch/arm/boot/dts/imx6qdl-sabrelite.dtsi           |   19 +
>  arch/arm/boot/dts/imx6qdl.dtsi                     |  125 ++---
>  arch/arm/mach-imx/clk-imx6q.c                      |   11 +-
>  drivers/gpu/drm/drm_crtc.c                         |  241 +++++----
>  drivers/gpu/drm/drm_ioctl.c                        |    1 +
>  drivers/gpu/drm/drm_modes.c                        |    4 +
>  drivers/gpu/ipu-v3/ipu-common.c                    |  303 +++++++-----
>  drivers/gpu/ipu-v3/ipu-cpmem.c                     |   99 ++--
>  drivers/gpu/ipu-v3/ipu-dc.c                        |  305 ++++++++----
>  drivers/gpu/ipu-v3/ipu-di.c                        |  300 +++++++++---
>  drivers/gpu/ipu-v3/ipu-dmfc.c                      |   94 ++--
>  drivers/gpu/ipu-v3/ipu-dp.c                        |  214 ++++++--
>  drivers/gpu/ipu-v3/ipu-prv.h                       |    1 +
>  drivers/staging/imx-drm/imx-drm-core.c             |  190 +++++---
>  drivers/staging/imx-drm/imx-drm.h                  |   26 +-
>  drivers/staging/imx-drm/imx-hdmi.c                 |   77 ++-
>  drivers/staging/imx-drm/imx-ldb.c                  |  268 ++++++----
>  drivers/staging/imx-drm/imx-tve.c                  |    5 +-
>  drivers/staging/imx-drm/ipuv3-crtc.c               |  515 ++++++++++++++------
>  drivers/staging/imx-drm/ipuv3-plane.c              |  399 +++++++++++++--
>  drivers/staging/imx-drm/ipuv3-plane.h              |   35 +-
>  drivers/staging/imx-drm/parallel-display.c         |   78 ++-
>  include/drm/drm_crtc.h                             |   11 +
>  include/uapi/drm/drm.h                             |    1 +
>  include/uapi/drm/drm_mode.h                        |   12 +
>  include/uapi/drm/imx_drm.h                         |   30 ++
>  include/video/imx-ipu-v3.h                         |   86 +++-
>  31 files changed, 2557 insertions(+), 1079 deletions(-)
>  create mode 100644 include/uapi/drm/imx_drm.h
>
> --
> 1.7.9.5
>
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