Re: [PATCH 0/7] Pinctrl support for Zynq

["Andreas Färber" <afaerber@suse.de>]

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Am 05.11.2014 um 18:03 schrieb Sören Brinkmann:
> On Wed, 2014-11-05 at 06:56AM +0100, Andreas Färber wrote:
>> I've tracked down all 54 MIO pins of the Parallella and cooked up the
>> equivalent DT patch. [...] For testing purposes I've configured a
>> heartbeat trigger for the USER_LED (CR10).
>>
>> To my disappointment these pinctrl additions did not fix one issue:
>> Whenever a write access to be handled by the bitstream (0x808f0f04) is
>> performed, the board hangs and the heartbeat stops. Would a bug in the
>> bitstream allow this to happen, or are more drivers missing to actually
>> make use of the PL in general? With a downstream ADI/Xilinx 3.12 kernel
>> that problem does not surface.
> 
> This doesn't sound like being related to pinctrl at all.
> Devices in the PL are just memory mapped on the AXI bus. There is
> nothing needed to access those. Hangs do in most cases indicate that the
> IP does not respond (properly). In my experience this is mostly caused
> by 
>  - level shifters not enabled
>  - IP kept in reset
>  - IP is clock gated
> With the clock gating being the culprit in most cases. Did you check
> those things?

Figured it out: zynq-7000.dtsi sets fclk-enable = <0>, i.e., all PL
clocks are disabled by default. When overriding that tiny property with
0xf it suddenly works as expected! I'll send a patch later in the day.

Are boards expected to use clocks = <&clkc 15>, ...; on individual nodes
relying on the PL? Or does enabling those clocks require actually
loading a bitstream so that it is not being done by default?

It seems ranger dangerous to me that a single MMIO write can freeze the
system - as a software developer I would've expected this to be caught
and handled as a SIGBUS.

Regards,
Andreas

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