* [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes
@ 2014-12-10 11:06 Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types Paolo Bonzini
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 11:06 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
Most processors were lacking the VME flags. Haswell and Broadwell were
lacking two more. And Ivy Bridge was missing altogether.
Family/model/stepping for a low-end Xeon E3 v2 found on the SETI@Home CPU
list (http://setiathome.berkeley.edu/cpu_list.php), they also match the
Ivy Bridge Core i7 processor on which I tested the patch. The following
bare-metal features are missing in the guest:
dts acpi ss ht tm pbe arch_perfmon pebs bts xtopology nonstop_tsc
aperfmperf dtes64 monitor ds_cpl vmx smx est tm2 xtpr pdcm ida
arat epb pln pts dtherm tpr_shadow vnmi flexpriority ept vpid
... the absence of none of which is surprising.
Paolo
v1->v2:
add pc_compat_2_2 call to pc_compat_2_1 (for both PC and Q35)
remove VME, do not add it, for 2.2 machines
remove F16C/RDRAND, do not add them, for 2.2 machines
do not touch model names for SandyBridge
Paolo Bonzini (4):
pc: add 2.3 machine types
target-i386: add VME to all CPUs
target-i386: add f16c and rdrand to Haswell and Broadwell
target-i386: add Ivy Bridge CPU model
hw/i386/pc_piix.c | 49 ++++++++++++++++++++++++++++++++++++++---
hw/i386/pc_q35.c | 45 ++++++++++++++++++++++++++++++++++---
target-i386/cpu.c | 66 +++++++++++++++++++++++++++++++++++++++++--------------
3 files changed, 137 insertions(+), 23 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types
2014-12-10 11:06 [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes Paolo Bonzini
@ 2014-12-10 11:06 ` Paolo Bonzini
2014-12-10 13:12 ` Eduardo Habkost
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 2/4] target-i386: add VME to all CPUs Paolo Bonzini
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 11:06 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
The next patch will differentiate them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_piix.c | 30 +++++++++++++++++++++++++++---
hw/i386/pc_q35.c | 26 +++++++++++++++++++++++---
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 741dffd..3a79c05 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -303,9 +303,15 @@ static void pc_init_pci(MachineState *machine)
pc_init1(machine, 1, 1);
}
+static void pc_compat_2_2(MachineState *machine)
+{
+}
+
static void pc_compat_2_1(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
+
+ pc_compat_2_2(machine);
smbios_uuid_encoded = false;
x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
@@ -380,6 +386,12 @@ static void pc_compat_1_2(MachineState *machine)
x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI);
}
+static void pc_init_pci_2_2(MachineState *machine)
+{
+ pc_compat_2_2(machine);
+ pc_init_pci(machine);
+}
+
static void pc_init_pci_2_1(MachineState *machine)
{
pc_compat_2_1(machine);
@@ -473,6 +485,19 @@ static void pc_xen_hvm_init(MachineState *machine)
.desc = "Standard PC (i440FX + PIIX, 1996)", \
.hot_add_cpu = pc_hot_add_cpu
+#define PC_I440FX_2_3_MACHINE_OPTIONS \
+ PC_I440FX_MACHINE_OPTIONS, \
+ .default_machine_opts = "firmware=bios-256k.bin", \
+ .default_display = "std"
+
+static QEMUMachine pc_i440fx_machine_v2_3 = {
+ PC_I440FX_2_3_MACHINE_OPTIONS,
+ .name = "pc-i440fx-2.3",
+ .alias = "pc",
+ .init = pc_init_pci,
+ .is_default = 1,
+};
+
#define PC_I440FX_2_2_MACHINE_OPTIONS \
PC_I440FX_MACHINE_OPTIONS, \
.default_machine_opts = "firmware=bios-256k.bin", \
@@ -481,9 +506,7 @@ static void pc_xen_hvm_init(MachineState *machine)
static QEMUMachine pc_i440fx_machine_v2_2 = {
PC_I440FX_2_2_MACHINE_OPTIONS,
.name = "pc-i440fx-2.2",
- .alias = "pc",
- .init = pc_init_pci,
- .is_default = 1,
+ .init = pc_init_pci_2_2,
};
#define PC_I440FX_2_1_MACHINE_OPTIONS \
@@ -923,6 +946,7 @@ static QEMUMachine xenfv_machine = {
static void pc_machine_init(void)
{
+ qemu_register_pc_machine(&pc_i440fx_machine_v2_3);
qemu_register_pc_machine(&pc_i440fx_machine_v2_2);
qemu_register_pc_machine(&pc_i440fx_machine_v2_1);
qemu_register_pc_machine(&pc_i440fx_machine_v2_0);
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index e9ba1a2..a40b939 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -282,10 +282,15 @@ static void pc_q35_init(MachineState *machine)
}
}
+static void pc_compat_2_2(MachineState *machine)
+{
+}
+
static void pc_compat_2_1(MachineState *machine)
{
PCMachineState *pcms = PC_MACHINE(machine);
+ pc_compat_2_2(machine);
pcms->enforce_aligned_dimm = false;
smbios_uuid_encoded = false;
x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0);
@@ -329,6 +334,12 @@ static void pc_compat_1_4(MachineState *machine)
x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
}
+static void pc_q35_init_2_2(MachineState *machine)
+{
+ pc_compat_2_2(machine);
+ pc_q35_init(machine);
+}
+
static void pc_q35_init_2_1(MachineState *machine)
{
pc_compat_2_1(machine);
@@ -372,16 +383,24 @@ static void pc_q35_init_1_4(MachineState *machine)
.hot_add_cpu = pc_hot_add_cpu, \
.units_per_default_bus = 1
-#define PC_Q35_2_2_MACHINE_OPTIONS \
+#define PC_Q35_2_3_MACHINE_OPTIONS \
PC_Q35_MACHINE_OPTIONS, \
.default_machine_opts = "firmware=bios-256k.bin", \
.default_display = "std"
+static QEMUMachine pc_q35_machine_v2_3 = {
+ PC_Q35_2_3_MACHINE_OPTIONS,
+ .name = "pc-q35-2.3",
+ .alias = "q35",
+ .init = pc_q35_init,
+};
+
+#define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS
+
static QEMUMachine pc_q35_machine_v2_2 = {
PC_Q35_2_2_MACHINE_OPTIONS,
.name = "pc-q35-2.2",
- .alias = "q35",
- .init = pc_q35_init,
+ .init = pc_q35_init_2_2,
};
#define PC_Q35_2_1_MACHINE_OPTIONS \
@@ -460,6 +479,7 @@ static QEMUMachine pc_q35_machine_v1_4 = {
static void pc_q35_machine_init(void)
{
+ qemu_register_pc_machine(&pc_q35_machine_v2_3);
qemu_register_pc_machine(&pc_q35_machine_v2_2);
qemu_register_pc_machine(&pc_q35_machine_v2_1);
qemu_register_pc_machine(&pc_q35_machine_v2_0);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 2/4] target-i386: add VME to all CPUs
2014-12-10 11:06 [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types Paolo Bonzini
@ 2014-12-10 11:06 ` Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini
3 siblings, 0 replies; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 11:06 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
vm86 mode extensions date back to the 486. All models should have
them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_piix.c | 15 +++++++++++++++
hw/i386/pc_q35.c | 15 +++++++++++++++
target-i386/cpu.c | 30 +++++++++++++++---------------
3 files changed, 45 insertions(+), 15 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 3a79c05..e273003 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -305,6 +305,21 @@ static void pc_init_pci(MachineState *machine)
static void pc_compat_2_2(MachineState *machine)
{
+ x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_VME);
}
static void pc_compat_2_1(MachineState *machine)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a40b939..70c025e 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -284,6 +284,21 @@ static void pc_q35_init(MachineState *machine)
static void pc_compat_2_2(MachineState *machine)
{
+ x86_cpu_compat_set_features("kvm64", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("kvm32", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_VME);
}
static void pc_compat_2_1(MachineState *machine)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ef7d71c..136c457 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -760,9 +760,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
.family = 15,
.model = 6,
.stepping = 1,
- /* Missing: CPUID_VME, CPUID_HT */
+ /* Missing: CPUID_HT */
.features[FEAT_1_EDX] =
- PPRO_FEATURES |
+ PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
@@ -802,7 +802,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
- PPRO_FEATURES |
+ PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
.features[FEAT_1_ECX] =
CPUID_EXT_SSE3,
@@ -928,7 +928,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 15,
.stepping = 3,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -950,7 +950,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 23,
.stepping = 3,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -973,7 +973,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 26,
.stepping = 3,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -996,7 +996,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 44,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1020,7 +1020,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 42,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1049,7 +1049,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 60,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1084,7 +1084,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 61,
.stepping = 2,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1120,7 +1120,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1145,7 +1145,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1173,7 +1173,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 6,
.stepping = 1,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1203,7 +1203,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 1,
.stepping = 2,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
@@ -1238,7 +1238,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model = 2,
.stepping = 0,
.features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell
2014-12-10 11:06 [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 2/4] target-i386: add VME to all CPUs Paolo Bonzini
@ 2014-12-10 11:06 ` Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini
3 siblings, 0 replies; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 11:06 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
Both were added in Ivy Bridge (for which we do not have a CPU model
yet!).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/i386/pc_piix.c | 4 ++++
hw/i386/pc_q35.c | 4 ++++
target-i386/cpu.c | 4 ++--
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e273003..0df9cf9 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -320,6 +320,10 @@ static void pc_compat_2_2(MachineState *machine)
x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_VME);
x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_VME);
x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
}
static void pc_compat_2_1(MachineState *machine)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 70c025e..4a198ee 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -299,6 +299,10 @@ static void pc_compat_2_2(MachineState *machine)
x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, CPUID_EXT_VME);
x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, CPUID_EXT_VME);
x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, CPUID_EXT_VME);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
+ x86_cpu_compat_set_features("Haswell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_F16C);
+ x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX, 0, CPUID_EXT_RDRAND);
}
static void pc_compat_2_1(MachineState *machine)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 136c457..b2bb9a4 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1060,7 +1060,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID,
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
@@ -1095,7 +1095,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID,
+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
.features[FEAT_8000_0001_EDX] =
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v2 4/4] target-i386: add Ivy Bridge CPU model
2014-12-10 11:06 [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes Paolo Bonzini
` (2 preceding siblings ...)
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini
@ 2014-12-10 11:06 ` Paolo Bonzini
3 siblings, 0 replies; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 11:06 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
This is the delta from SandyBridge:
model = 58
stepping = 9
features[FEAT_1_ECX] |=
CPUID_EXT_F16C | CPUID_EXT_RDRAND;
features[FEAT_7_0_EBX] |=
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS;
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b2bb9a4..b81ac5c 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1042,6 +1042,38 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
},
{
+ .name = "IvyBridge",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 58,
+ .stepping = 9,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
+ CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_ERMS,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ },
+ {
.name = "Haswell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types Paolo Bonzini
@ 2014-12-10 13:12 ` Eduardo Habkost
2014-12-10 15:08 ` Paolo Bonzini
0 siblings, 1 reply; 9+ messages in thread
From: Eduardo Habkost @ 2014-12-10 13:12 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On Wed, Dec 10, 2014 at 12:06:29PM +0100, Paolo Bonzini wrote:
[...]
pc_piix.c:
> +#define PC_I440FX_2_3_MACHINE_OPTIONS \
> + PC_I440FX_MACHINE_OPTIONS, \
> + .default_machine_opts = "firmware=bios-256k.bin", \
> + .default_display = "std"
> +
[...]
> #define PC_I440FX_2_2_MACHINE_OPTIONS \
> PC_I440FX_MACHINE_OPTIONS, \
> .default_machine_opts = "firmware=bios-256k.bin", \
pc_q35.c:
> -#define PC_Q35_2_2_MACHINE_OPTIONS \
> +#define PC_Q35_2_3_MACHINE_OPTIONS \
> PC_Q35_MACHINE_OPTIONS, \
> .default_machine_opts = "firmware=bios-256k.bin", \
> .default_display = "std"
[...]
> +#define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS
I don't know which approach I prefer (I would be happy with either), but
why the difference?
The patch is still correct either way, so:
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
--
Eduardo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types
2014-12-10 13:12 ` Eduardo Habkost
@ 2014-12-10 15:08 ` Paolo Bonzini
2014-12-10 15:48 ` Eduardo Habkost
0 siblings, 1 reply; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 15:08 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: qemu-devel
On 10/12/2014 14:12, Eduardo Habkost wrote:
>> > +#define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS
> I don't know which approach I prefer (I would be happy with either), but
> why the difference?
I'm just mimicking what's around:
#define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
Paolo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types
2014-12-10 15:08 ` Paolo Bonzini
@ 2014-12-10 15:48 ` Eduardo Habkost
2014-12-10 16:45 ` Paolo Bonzini
0 siblings, 1 reply; 9+ messages in thread
From: Eduardo Habkost @ 2014-12-10 15:48 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On Wed, Dec 10, 2014 at 04:08:38PM +0100, Paolo Bonzini wrote:
> On 10/12/2014 14:12, Eduardo Habkost wrote:
> >> > +#define PC_Q35_2_2_MACHINE_OPTIONS PC_Q35_2_3_MACHINE_OPTIONS
> > I don't know which approach I prefer (I would be happy with either), but
> > why the difference?
>
> I'm just mimicking what's around:
>
> #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
Whatever you see on pc_q35.c, it is also present on pc_piix.c:
#define PC_I440FX_2_0_MACHINE_OPTIONS PC_I440FX_2_1_MACHINE_OPTIONS
Both approaches are OK to me, I just don't see why you decided to make
pc_piix.c and pc_q35.c different.
--
Eduardo
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types
2014-12-10 15:48 ` Eduardo Habkost
@ 2014-12-10 16:45 ` Paolo Bonzini
0 siblings, 0 replies; 9+ messages in thread
From: Paolo Bonzini @ 2014-12-10 16:45 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: qemu-devel
On 10/12/2014 16:48, Eduardo Habkost wrote:
> Whatever you see on pc_q35.c, it is also present on pc_piix.c:
>
> #define PC_I440FX_2_0_MACHINE_OPTIONS PC_I440FX_2_1_MACHINE_OPTIONS
>
> Both approaches are OK to me, I just don't see why you decided to make
> pc_piix.c and pc_q35.c different.
Because I didn't notice it in pc_piix.c. I'll change to
#define PC_I440FX_2_2_MACHINE_OPTIONS PC_I440FX_2_3_MACHINE_OPTIONS
Thanks, and sorry for the confusion.
Paolo
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2014-12-10 16:45 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-10 11:06 [Qemu-devel] [PATCH v2 0/4] x86 CPU model fixes Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 1/4] pc: add 2.3 machine types Paolo Bonzini
2014-12-10 13:12 ` Eduardo Habkost
2014-12-10 15:08 ` Paolo Bonzini
2014-12-10 15:48 ` Eduardo Habkost
2014-12-10 16:45 ` Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 2/4] target-i386: add VME to all CPUs Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 3/4] target-i386: add f16c and rdrand to Haswell and Broadwell Paolo Bonzini
2014-12-10 11:06 ` [Qemu-devel] [PATCH v2 4/4] target-i386: add Ivy Bridge CPU model Paolo Bonzini
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.