* [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support.
@ 2014-12-20 0:33 David Daney
2014-12-20 0:33 ` David Daney
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: David Daney @ 2014-12-20 0:33 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: Leonid Yegoshin, David Daney
From: David Daney <david.daney@cavium.com>
The two patches reverted here break eXecute-Inhibit (XI) memory
protection support. Before the patches we get SIGSEGV when attempting
to execute in non-executable memory, after the patches we loop forever
in handle_tlbl.
It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think
the most prudent thing is to revert these patches, and then only reapply
something that works after it has been well tested.
David Daney (2):
Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI
exceptions"
Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions"
arch/mips/include/asm/mipsregs.h | 1 -
arch/mips/kernel/cpu-probe.c | 9 ---------
arch/mips/kernel/traps.c | 7 -------
arch/mips/mm/tlbex.c | 4 ++--
4 files changed, 2 insertions(+), 19 deletions(-)
--
1.7.11.7
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/2] Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions" @ 2014-12-20 0:33 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:33 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Leonid Yegoshin, David Daney, stable From: David Daney <david.daney@cavium.com> This reverts commit 5890f70f15c52d0204a578422f8da828a0ba1096. The patch was not tested, It sets PG_IEC in cpu-probe. But this value is clobbered in tlb_init() so the system is never configured to take the RIXI specific exceptions, and we end up in an endless loop in handle_tlbl because that code is not expecting the XI condition. Cc: <stable@vger.kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/kernel/traps.c | 7 ------- arch/mips/mm/tlbex.c | 4 ++-- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad3d203..722ed75 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -90,7 +90,6 @@ extern asmlinkage void handle_mt(void); extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern void tlb_do_page_fault_0(void); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); @@ -2205,12 +2204,6 @@ void __init trap_init(void) set_except_vector(15, handle_fpe); set_except_vector(16, handle_ftlb); - - if (cpu_has_rixiex) { - set_except_vector(19, tlb_do_page_fault_0); - set_except_vector(20, tlb_do_page_fault_0); - } - set_except_vector(21, handle_msa); set_except_vector(22, handle_mdmx); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 3978a3d..c9e0150 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1934,7 +1934,7 @@ static void build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (cpu_has_rixi && !cpu_has_rixiex) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -2001,7 +2001,7 @@ static void build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (cpu_has_rixi && !cpu_has_rixiex) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. -- 1.7.11.7 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions" @ 2014-12-20 0:33 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:33 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Leonid Yegoshin, David Daney, stable From: David Daney <david.daney@cavium.com> This reverts commit 5890f70f15c52d0204a578422f8da828a0ba1096. The patch was not tested, It sets PG_IEC in cpu-probe. But this value is clobbered in tlb_init() so the system is never configured to take the RIXI specific exceptions, and we end up in an endless loop in handle_tlbl because that code is not expecting the XI condition. Cc: <stable@vger.kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/kernel/traps.c | 7 ------- arch/mips/mm/tlbex.c | 4 ++-- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad3d203..722ed75 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -90,7 +90,6 @@ extern asmlinkage void handle_mt(void); extern asmlinkage void handle_dsp(void); extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); -extern void tlb_do_page_fault_0(void); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); @@ -2205,12 +2204,6 @@ void __init trap_init(void) set_except_vector(15, handle_fpe); set_except_vector(16, handle_ftlb); - - if (cpu_has_rixiex) { - set_except_vector(19, tlb_do_page_fault_0); - set_except_vector(20, tlb_do_page_fault_0); - } - set_except_vector(21, handle_msa); set_except_vector(22, handle_mdmx); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 3978a3d..c9e0150 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1934,7 +1934,7 @@ static void build_r4000_tlb_load_handler(void) if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); - if (cpu_has_rixi && !cpu_has_rixiex) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. @@ -2001,7 +2001,7 @@ static void build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); build_tlb_probe_entry(&p); - if (cpu_has_rixi && !cpu_has_rixiex) { + if (cpu_has_rixi) { /* * If the page is not _PAGE_VALID, RI or XI could not * have triggered it. Skip the expensive test.. -- 1.7.11.7 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" @ 2014-12-20 0:33 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:33 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Leonid Yegoshin, David Daney, stable From: David Daney <david.daney@cavium.com> This reverts commit 6575b1d4173eaeff6742a2c6dcbd835bb052952b. It sets PG_IEC in cpu-probe. But this value is clobbered in tlb_init() so the system is never configured to take the RIXI specific exceptions. Caos ensues. Cc: <stable@vger.kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/include/asm/mipsregs.h | 1 - arch/mips/kernel/cpu-probe.c | 9 --------- 2 files changed, 10 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5e4aef3..dfdca76 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -265,7 +265,6 @@ #define PG_XIE (_ULCAST_(1) << 30) #define PG_ELPA (_ULCAST_(1) << 29) #define PG_ESP (_ULCAST_(1) << 28) -#define PG_IEC (_ULCAST_(1) << 27) /* * R4x00 interrupt enable / cause bits diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5342674..63ace78 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -531,15 +531,6 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); - if (cpu_has_rixi) { - /* Enable the RIXI exceptions */ - write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); - back_to_back_c0_hazard(); - /* Verify the IEC bit is set */ - if (read_c0_pagegrain() & PG_IEC) - c->options |= MIPS_CPU_RIXIEX; - } - #ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2) { c->core = get_ebase_cpunum(); -- 1.7.11.7 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" @ 2014-12-20 0:33 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:33 UTC (permalink / raw) To: linux-mips, ralf; +Cc: Leonid Yegoshin, David Daney, stable From: David Daney <david.daney@cavium.com> This reverts commit 6575b1d4173eaeff6742a2c6dcbd835bb052952b. It sets PG_IEC in cpu-probe. But this value is clobbered in tlb_init() so the system is never configured to take the RIXI specific exceptions. Caos ensues. Cc: <stable@vger.kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/include/asm/mipsregs.h | 1 - arch/mips/kernel/cpu-probe.c | 9 --------- 2 files changed, 10 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5e4aef3..dfdca76 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -265,7 +265,6 @@ #define PG_XIE (_ULCAST_(1) << 30) #define PG_ELPA (_ULCAST_(1) << 29) #define PG_ESP (_ULCAST_(1) << 28) -#define PG_IEC (_ULCAST_(1) << 27) /* * R4x00 interrupt enable / cause bits diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5342674..63ace78 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -531,15 +531,6 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); - if (cpu_has_rixi) { - /* Enable the RIXI exceptions */ - write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); - back_to_back_c0_hazard(); - /* Verify the IEC bit is set */ - if (read_c0_pagegrain() & PG_IEC) - c->options |= MIPS_CPU_RIXIEX; - } - #ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2) { c->core = get_ebase_cpunum(); -- 1.7.11.7 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:43 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 0:43 UTC (permalink / raw) To: David Daney, linux-mips, ralf; +Cc: David Daney On 12/19/2014 04:33 PM, David Daney wrote: > From: David Daney <david.daney@cavium.com> > > The two patches reverted here break eXecute-Inhibit (XI) memory > protection support. Before the patches we get SIGSEGV when attempting > to execute in non-executable memory, after the patches we loop forever > in handle_tlbl. > > It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think > the most prudent thing is to revert these patches, and then only reapply > something that works after it has been well tested. > > David Daney (2): > Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI > exceptions" > Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" > > arch/mips/include/asm/mipsregs.h | 1 - > arch/mips/kernel/cpu-probe.c | 9 --------- > arch/mips/kernel/traps.c | 7 ------- > arch/mips/mm/tlbex.c | 4 ++-- > 4 files changed, 2 insertions(+), 19 deletions(-) > Well, it may be have sense just to fix tlb_init() instead. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:43 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 0:43 UTC (permalink / raw) To: David Daney, linux-mips, ralf; +Cc: David Daney On 12/19/2014 04:33 PM, David Daney wrote: > From: David Daney <david.daney@cavium.com> > > The two patches reverted here break eXecute-Inhibit (XI) memory > protection support. Before the patches we get SIGSEGV when attempting > to execute in non-executable memory, after the patches we loop forever > in handle_tlbl. > > It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think > the most prudent thing is to revert these patches, and then only reapply > something that works after it has been well tested. > > David Daney (2): > Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI > exceptions" > Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" > > arch/mips/include/asm/mipsregs.h | 1 - > arch/mips/kernel/cpu-probe.c | 9 --------- > arch/mips/kernel/traps.c | 7 ------- > arch/mips/mm/tlbex.c | 4 ++-- > 4 files changed, 2 insertions(+), 19 deletions(-) > Well, it may be have sense just to fix tlb_init() instead. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:49 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 0:49 UTC (permalink / raw) To: David Daney, linux-mips, ralf On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: > On 12/19/2014 04:33 PM, David Daney wrote: >> From: David Daney <david.daney@cavium.com> >> >> The two patches reverted here break eXecute-Inhibit (XI) memory >> protection support. Before the patches we get SIGSEGV when attempting >> to execute in non-executable memory, after the patches we loop forever >> in handle_tlbl. >> >> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think >> the most prudent thing is to revert these patches, and then only reapply >> something that works after it has been well tested. >> >> David Daney (2): >> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI >> exceptions" >> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >> >> arch/mips/include/asm/mipsregs.h | 1 - >> arch/mips/kernel/cpu-probe.c | 9 --------- >> arch/mips/kernel/traps.c | 7 ------- >> arch/mips/mm/tlbex.c | 4 ++-- >> 4 files changed, 2 insertions(+), 19 deletions(-) >> > Well, it may be have sense just to fix tlb_init() instead. diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index aa6e4b3b2fe2..ed18efd9374b 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) #ifdef CONFIG_64BIT pg |= PG_ELPA; #endif - write_c0_pagegrain(pg); + write_c0_pagegrain(pg | read_c0_pagegrain()); } mtc0_tlbw_hazard(); ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:49 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 0:49 UTC (permalink / raw) To: David Daney, linux-mips, ralf On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: > On 12/19/2014 04:33 PM, David Daney wrote: >> From: David Daney <david.daney@cavium.com> >> >> The two patches reverted here break eXecute-Inhibit (XI) memory >> protection support. Before the patches we get SIGSEGV when attempting >> to execute in non-executable memory, after the patches we loop forever >> in handle_tlbl. >> >> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think >> the most prudent thing is to revert these patches, and then only reapply >> something that works after it has been well tested. >> >> David Daney (2): >> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI >> exceptions" >> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >> >> arch/mips/include/asm/mipsregs.h | 1 - >> arch/mips/kernel/cpu-probe.c | 9 --------- >> arch/mips/kernel/traps.c | 7 ------- >> arch/mips/mm/tlbex.c | 4 ++-- >> 4 files changed, 2 insertions(+), 19 deletions(-) >> > Well, it may be have sense just to fix tlb_init() instead. diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index aa6e4b3b2fe2..ed18efd9374b 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) #ifdef CONFIG_64BIT pg |= PG_ELPA; #endif - write_c0_pagegrain(pg); + write_c0_pagegrain(pg | read_c0_pagegrain()); } mtc0_tlbw_hazard(); ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. 2014-12-20 0:49 ` Leonid Yegoshin (?) @ 2014-12-20 0:52 ` Ralf Baechle 2014-12-20 1:10 ` David Daney -1 siblings, 1 reply; 15+ messages in thread From: Ralf Baechle @ 2014-12-20 0:52 UTC (permalink / raw) To: Leonid Yegoshin; +Cc: David Daney, linux-mips On Fri, Dec 19, 2014 at 04:49:28PM -0800, Leonid Yegoshin wrote: > Date: Fri, 19 Dec 2014 16:49:28 -0800 > From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> > To: David Daney <ddaney.cavm@gmail.com>, linux-mips@linux-mips.org, > ralf@linux-mips.org > Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. > Content-Type: text/plain; charset="windows-1252"; format=flowed > > On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: > >On 12/19/2014 04:33 PM, David Daney wrote: > >>From: David Daney <david.daney@cavium.com> > >> > >>The two patches reverted here break eXecute-Inhibit (XI) memory > >>protection support. Before the patches we get SIGSEGV when attempting > >>to execute in non-executable memory, after the patches we loop forever > >>in handle_tlbl. > >> > >>It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think > >>the most prudent thing is to revert these patches, and then only reapply > >>something that works after it has been well tested. > >> > >>David Daney (2): > >> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI > >> exceptions" > >> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" > >> > >> arch/mips/include/asm/mipsregs.h | 1 - > >> arch/mips/kernel/cpu-probe.c | 9 --------- > >> arch/mips/kernel/traps.c | 7 ------- > >> arch/mips/mm/tlbex.c | 4 ++-- > >> 4 files changed, 2 insertions(+), 19 deletions(-) > >> > >Well, it may be have sense just to fix tlb_init() instead. > > diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c > index aa6e4b3b2fe2..ed18efd9374b 100644 > --- a/arch/mips/mm/tlb-r4k.c > +++ b/arch/mips/mm/tlb-r4k.c > @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) > #ifdef CONFIG_64BIT > pg |= PG_ELPA; > #endif > - write_c0_pagegrain(pg); > + write_c0_pagegrain(pg | read_c0_pagegrain()); Simpler: set_c0_pagegrain(pg); Ralf ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. 2014-12-20 0:52 ` Ralf Baechle @ 2014-12-20 1:10 ` David Daney 2014-12-20 1:19 ` Leonid Yegoshin 0 siblings, 1 reply; 15+ messages in thread From: David Daney @ 2014-12-20 1:10 UTC (permalink / raw) To: Ralf Baechle; +Cc: Leonid Yegoshin, linux-mips On 12/19/2014 04:52 PM, Ralf Baechle wrote: > On Fri, Dec 19, 2014 at 04:49:28PM -0800, Leonid Yegoshin wrote: >> Date: Fri, 19 Dec 2014 16:49:28 -0800 >> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> >> To: David Daney <ddaney.cavm@gmail.com>, linux-mips@linux-mips.org, >> ralf@linux-mips.org >> Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. >> Content-Type: text/plain; charset="windows-1252"; format=flowed >> >> On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: >>> On 12/19/2014 04:33 PM, David Daney wrote: >>>> From: David Daney <david.daney@cavium.com> >>>> >>>> The two patches reverted here break eXecute-Inhibit (XI) memory >>>> protection support. Before the patches we get SIGSEGV when attempting >>>> to execute in non-executable memory, after the patches we loop forever >>>> in handle_tlbl. >>>> >>>> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think >>>> the most prudent thing is to revert these patches, and then only reapply >>>> something that works after it has been well tested. >>>> >>>> David Daney (2): >>>> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI >>>> exceptions" >>>> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >>>> >>>> arch/mips/include/asm/mipsregs.h | 1 - >>>> arch/mips/kernel/cpu-probe.c | 9 --------- >>>> arch/mips/kernel/traps.c | 7 ------- >>>> arch/mips/mm/tlbex.c | 4 ++-- >>>> 4 files changed, 2 insertions(+), 19 deletions(-) >>>> >>> Well, it may be have sense just to fix tlb_init() instead. >> >> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c >> index aa6e4b3b2fe2..ed18efd9374b 100644 >> --- a/arch/mips/mm/tlb-r4k.c >> +++ b/arch/mips/mm/tlb-r4k.c >> @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) >> #ifdef CONFIG_64BIT >> pg |= PG_ELPA; >> #endif >> - write_c0_pagegrain(pg); >> + write_c0_pagegrain(pg | read_c0_pagegrain()); > > Simpler: > set_c0_pagegrain(pg); No. That is exactly how it was broken before. It is possible that you would want: if (cpu_has_rixiex) pg |= PG_IEC; set_c0_pagegrain(pg); But that wasn't really tested. It seems to work though. I will send another patch. David Daney > > Ralf > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 1:19 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 1:19 UTC (permalink / raw) To: David Daney, Ralf Baechle; +Cc: linux-mips On 12/19/2014 05:10 PM, David Daney wrote: > On 12/19/2014 04:52 PM, Ralf Baechle wrote: >> On Fri, Dec 19, 2014 at 04:49:28PM -0800, Leonid Yegoshin wrote: >>> Date: Fri, 19 Dec 2014 16:49:28 -0800 >>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> >>> To: David Daney <ddaney.cavm@gmail.com>, linux-mips@linux-mips.org, >>> ralf@linux-mips.org >>> Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. >>> Content-Type: text/plain; charset="windows-1252"; format=flowed >>> >>> On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: >>>> On 12/19/2014 04:33 PM, David Daney wrote: >>>>> From: David Daney <david.daney@cavium.com> >>>>> >>>>> The two patches reverted here break eXecute-Inhibit (XI) memory >>>>> protection support. Before the patches we get SIGSEGV when >>>>> attempting >>>>> to execute in non-executable memory, after the patches we loop >>>>> forever >>>>> in handle_tlbl. >>>>> >>>>> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I >>>>> think >>>>> the most prudent thing is to revert these patches, and then only >>>>> reapply >>>>> something that works after it has been well tested. >>>>> >>>>> David Daney (2): >>>>> Revert "MIPS: Use dedicated exception handler if CPU supports >>>>> RI/XI >>>>> exceptions" >>>>> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >>>>> >>>>> arch/mips/include/asm/mipsregs.h | 1 - >>>>> arch/mips/kernel/cpu-probe.c | 9 --------- >>>>> arch/mips/kernel/traps.c | 7 ------- >>>>> arch/mips/mm/tlbex.c | 4 ++-- >>>>> 4 files changed, 2 insertions(+), 19 deletions(-) >>>>> >>>> Well, it may be have sense just to fix tlb_init() instead. >>> >>> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c >>> index aa6e4b3b2fe2..ed18efd9374b 100644 >>> --- a/arch/mips/mm/tlb-r4k.c >>> +++ b/arch/mips/mm/tlb-r4k.c >>> @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) >>> #ifdef CONFIG_64BIT >>> pg |= PG_ELPA; >>> #endif >>> - write_c0_pagegrain(pg); >>> + write_c0_pagegrain(pg | read_c0_pagegrain()); >> >> Simpler: >> set_c0_pagegrain(pg); > > No. That is exactly how it was broken before. > > It is possible that you would want: > > if (cpu_has_rixiex) > pg |= PG_IEC; > set_c0_pagegrain(pg); > > But that wasn't really tested. It seems to work though. > > I will send another patch. > > David Daney Well, to honest, it is extensively tested on MIPS R6 because it have PG_IEC read-only == 1 (non-switchable OFF) And on other cores which has no PG_IEC at all, of course. As for your concern about set_c0_pagegrain(pg) - it sets 2 or 3 bits in pagegrain but doesn't clear the rest which was before with a single write_c0_pagegrain(pg) and any switchable bit comes down. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 1:19 ` Leonid Yegoshin 0 siblings, 0 replies; 15+ messages in thread From: Leonid Yegoshin @ 2014-12-20 1:19 UTC (permalink / raw) To: David Daney, Ralf Baechle; +Cc: linux-mips On 12/19/2014 05:10 PM, David Daney wrote: > On 12/19/2014 04:52 PM, Ralf Baechle wrote: >> On Fri, Dec 19, 2014 at 04:49:28PM -0800, Leonid Yegoshin wrote: >>> Date: Fri, 19 Dec 2014 16:49:28 -0800 >>> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> >>> To: David Daney <ddaney.cavm@gmail.com>, linux-mips@linux-mips.org, >>> ralf@linux-mips.org >>> Subject: Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. >>> Content-Type: text/plain; charset="windows-1252"; format=flowed >>> >>> On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: >>>> On 12/19/2014 04:33 PM, David Daney wrote: >>>>> From: David Daney <david.daney@cavium.com> >>>>> >>>>> The two patches reverted here break eXecute-Inhibit (XI) memory >>>>> protection support. Before the patches we get SIGSEGV when >>>>> attempting >>>>> to execute in non-executable memory, after the patches we loop >>>>> forever >>>>> in handle_tlbl. >>>>> >>>>> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I >>>>> think >>>>> the most prudent thing is to revert these patches, and then only >>>>> reapply >>>>> something that works after it has been well tested. >>>>> >>>>> David Daney (2): >>>>> Revert "MIPS: Use dedicated exception handler if CPU supports >>>>> RI/XI >>>>> exceptions" >>>>> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >>>>> >>>>> arch/mips/include/asm/mipsregs.h | 1 - >>>>> arch/mips/kernel/cpu-probe.c | 9 --------- >>>>> arch/mips/kernel/traps.c | 7 ------- >>>>> arch/mips/mm/tlbex.c | 4 ++-- >>>>> 4 files changed, 2 insertions(+), 19 deletions(-) >>>>> >>>> Well, it may be have sense just to fix tlb_init() instead. >>> >>> diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c >>> index aa6e4b3b2fe2..ed18efd9374b 100644 >>> --- a/arch/mips/mm/tlb-r4k.c >>> +++ b/arch/mips/mm/tlb-r4k.c >>> @@ -602,7 +602,7 @@ void __cpuinit tlb_init(void) >>> #ifdef CONFIG_64BIT >>> pg |= PG_ELPA; >>> #endif >>> - write_c0_pagegrain(pg); >>> + write_c0_pagegrain(pg | read_c0_pagegrain()); >> >> Simpler: >> set_c0_pagegrain(pg); > > No. That is exactly how it was broken before. > > It is possible that you would want: > > if (cpu_has_rixiex) > pg |= PG_IEC; > set_c0_pagegrain(pg); > > But that wasn't really tested. It seems to work though. > > I will send another patch. > > David Daney Well, to honest, it is extensively tested on MIPS R6 because it have PG_IEC read-only == 1 (non-switchable OFF) And on other cores which has no PG_IEC at all, of course. As for your concern about set_c0_pagegrain(pg) - it sets 2 or 3 bits in pagegrain but doesn't clear the rest which was before with a single write_c0_pagegrain(pg) and any switchable bit comes down. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:55 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:55 UTC (permalink / raw) To: Leonid Yegoshin; +Cc: David Daney, linux-mips, ralf, David Daney On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: > On 12/19/2014 04:33 PM, David Daney wrote: >> From: David Daney <david.daney@cavium.com> >> >> The two patches reverted here break eXecute-Inhibit (XI) memory >> protection support. Before the patches we get SIGSEGV when attempting >> to execute in non-executable memory, after the patches we loop forever >> in handle_tlbl. >> >> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think >> the most prudent thing is to revert these patches, and then only reapply >> something that works after it has been well tested. >> >> David Daney (2): >> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI >> exceptions" >> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >> >> arch/mips/include/asm/mipsregs.h | 1 - >> arch/mips/kernel/cpu-probe.c | 9 --------- >> arch/mips/kernel/traps.c | 7 ------- >> arch/mips/mm/tlbex.c | 4 ++-- >> 4 files changed, 2 insertions(+), 19 deletions(-) >> > Well, it may be have sense just to fix tlb_init() instead. I have more confidence in going back to a working configuration. My simple tests on OCTEON tell me that it is working again. Somebody adding working support for C0_Pagegrain[PG_IEC] would want to do much more testing across many different CPUs to be able to assert that it was tested and working. I would be happy to test any patches adding this support on a variety of different OCTEON CPU cores, but I don't have access to anything MIPS/img may have that supports this feature. David Daney. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support. @ 2014-12-20 0:55 ` David Daney 0 siblings, 0 replies; 15+ messages in thread From: David Daney @ 2014-12-20 0:55 UTC (permalink / raw) To: Leonid Yegoshin; +Cc: David Daney, linux-mips, ralf, David Daney On 12/19/2014 04:43 PM, Leonid Yegoshin wrote: > On 12/19/2014 04:33 PM, David Daney wrote: >> From: David Daney <david.daney@cavium.com> >> >> The two patches reverted here break eXecute-Inhibit (XI) memory >> protection support. Before the patches we get SIGSEGV when attempting >> to execute in non-executable memory, after the patches we loop forever >> in handle_tlbl. >> >> It is probably possible to make C0_Pagegrain[PG_IEC] work, but I think >> the most prudent thing is to revert these patches, and then only reapply >> something that works after it has been well tested. >> >> David Daney (2): >> Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI >> exceptions" >> Revert "MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions" >> >> arch/mips/include/asm/mipsregs.h | 1 - >> arch/mips/kernel/cpu-probe.c | 9 --------- >> arch/mips/kernel/traps.c | 7 ------- >> arch/mips/mm/tlbex.c | 4 ++-- >> 4 files changed, 2 insertions(+), 19 deletions(-) >> > Well, it may be have sense just to fix tlb_init() instead. I have more confidence in going back to a working configuration. My simple tests on OCTEON tell me that it is working again. Somebody adding working support for C0_Pagegrain[PG_IEC] would want to do much more testing across many different CPUs to be able to assert that it was tested and working. I would be happy to test any patches adding this support on a variety of different OCTEON CPU cores, but I don't have access to anything MIPS/img may have that supports this feature. David Daney. ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2014-12-20 1:20 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-12-20 0:33 [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support David Daney 2014-12-20 0:33 ` [PATCH 1/2] Revert "MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions" David Daney 2014-12-20 0:33 ` David Daney 2014-12-20 0:33 ` [PATCH 2/2] Revert "MIPS: kernel: cpu-probe: Detect unique " David Daney 2014-12-20 0:33 ` David Daney 2014-12-20 0:43 ` [PATCH 0/2] Revert broken C0_Pagegrain[PG_IEC] support Leonid Yegoshin 2014-12-20 0:43 ` Leonid Yegoshin 2014-12-20 0:49 ` Leonid Yegoshin 2014-12-20 0:49 ` Leonid Yegoshin 2014-12-20 0:52 ` Ralf Baechle 2014-12-20 1:10 ` David Daney 2014-12-20 1:19 ` Leonid Yegoshin 2014-12-20 1:19 ` Leonid Yegoshin 2014-12-20 0:55 ` David Daney 2014-12-20 0:55 ` David Daney
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