All of lore.kernel.org
 help / color / mirror / Atom feed
From: David Daney <ddaney.cavm@gmail.com>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
	Joshua Kinard <kumba@gentoo.org>,
	Linux MIPS List <linux-mips@linux-mips.org>
Subject: Re: [PATCH] MIPS: Display CPU byteorder in /proc/cpuinfo
Date: Mon, 26 Jan 2015 10:15:05 -0800	[thread overview]
Message-ID: <54C68429.4030701@gmail.com> (raw)
In-Reply-To: <alpine.LFD.2.11.1501261358540.28301@eddie.linux-mips.org>

On 01/26/2015 06:53 AM, Maciej W. Rozycki wrote:
> On Mon, 26 Jan 2015, Ralf Baechle wrote:
>
>>>   Well, several MIPS processors can reverse the user-mode endianness via
>>> the CP0.Status.RE bit; though as you may be aware it has never been
>>> implemented for Linux.  Otherwise it would obviously have to be a
>>> per-process property (and execve(2) could flip it back).
>>
>> As posted previously that was why I removed it from /proc/cpuinfo.  And
>> yes, I had a simple prototype to use the RE feature.  Even in the limited
>> form I had it was impressively ugly and it became clear it would never
>> be upstreamable.
>
>   Out of curiosity -- what was there that made it so ugly?  The need for
> case-by-case individual handling of byte-swapping the qualifying members
> of syscall and signal data structures such as `struct stat'?  Obviously
> not alignment trap fixups, these are trivial to handle.  And I think
> pretty much everything else is endianness-agnostic.
>

I think *nothing* is endianness-agnostic.  The instruction set reference 
manual (MD00087 MIPS® Architecture For Programmers Volume II-A: The 
MIPS64® Instruction Set, Revision 5.02) is a little cryptic, but I think 
looking at the LB instruction shows how it works.  OCTEON is known to 
implement this and has been verified to work this way.

aligned 64-bit loads and stores are endianness invariant.

32-bit loads and stores have even and odd words swapped in the opposite 
endianness (low order 3 address bits are XOR 4).

16-bit loads and stores half words scrambled in the opposite endianness 
(low order 3 address bits are XOR 6).

8-bit loads and stores are scrambled such that the low order 3 address 
bits are XOR 7 in the opposite endianness.

The result that all byte array data is scrambled when switching endianness.

This means that all read(), write() and similar calls could *not* access 
the user data in-place in the kernel.  The kernel would have to  swap 
around the bytes before using it.  mmap() of the same file in processes 
of opposite endianness would be impossible, as one of the processes 
would see scrambled data.

For this reason, it really only makes sense to have the kernel and 
user-space use the same endianness.

And because kernel and userspace must have the same endianness, the 
endianness can be probed in userspace without consulting the kernel.

David Daney

  reply	other threads:[~2015-01-26 18:15 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-19  9:02 [PATCH] MIPS: Display CPU byteorder in /proc/cpuinfo Joshua Kinard
2015-01-20 23:05 ` David Daney
2015-01-21  2:45   ` Joshua Kinard
2015-01-21  2:54     ` Joshua Kinard
2015-01-21 10:22       ` Markos Chandras
2015-01-21 11:26         ` Joshua Kinard
2015-01-21 13:49         ` Ralf Baechle
2015-01-21 18:18           ` David Daney
2015-01-21 18:38         ` Aaro Koskinen
2015-01-21 18:42           ` David Daney
2015-01-26  8:06     ` Maciej W. Rozycki
2015-01-26 13:16       ` Ralf Baechle
2015-01-26 14:53         ` Maciej W. Rozycki
2015-01-26 18:15           ` David Daney [this message]
2015-01-26 19:39             ` Maciej W. Rozycki
2015-01-26 20:13               ` David Daney
2015-01-27 16:15                 ` Maciej W. Rozycki
2015-01-27 19:57                   ` David Daney
2015-02-05 13:46                     ` Maciej W. Rozycki
2015-02-05 15:28                       ` Måns Rullgård
2015-02-05 16:12                         ` Maciej W. Rozycki
2015-02-05 19:36                           ` Måns Rullgård
2015-02-05 16:27                       ` David Daney
2015-02-05 21:02                         ` Maciej W. Rozycki
2015-01-21  6:50   ` Antony Pavlov
2015-02-12  4:16 ` Joshua Kinard

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=54C68429.4030701@gmail.com \
    --to=ddaney.cavm@gmail.com \
    --cc=kumba@gentoo.org \
    --cc=linux-mips@linux-mips.org \
    --cc=macro@linux-mips.org \
    --cc=ralf@linux-mips.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.