Re: [PATCH] MIPS: Display CPU byteorder in /proc/cpuinfo

[David Daney <ddaney.cavm@gmail.com>]

On 01/27/2015 08:15 AM, Maciej W. Rozycki wrote:
> On Mon, 26 Jan 2015, David Daney wrote:
>
>>>    Well, read(2), write(2) and similar calls operate on byte streams, these
>>> are endianness agnostic (like the text of this e-mail for example is --
>>> it's stored in memory of a byte-addressed computer the same way regardless
>>> of its processor's endianness).
>>
>> This is precisely the point I was attempting to make.  What you say here is
>> *not* correct with respect to MIPS as specified in the architecture reference
>> mentioned above.  The byte streams are scrambled up when viewed from contexts
>> of opposite endianness.
>>
>> Byte streams are *not* endian agnostic, but aligned 64-bit loads and stores
>> are.
>>
>> It is bizarre, and perhaps almost mind bending, but that seems to be how it is
>> specified.  Certainly the OCTEON implementation works this way.
>
>   Well, I think this observation:
>
> "2.2.2.2 Memory Operation Functions
>
> "Regardless of byte ordering (big- or little-endian), the address of a
> halfword, word, or doubleword is the smallest byte address of the bytes
> that form the object.  For big-endian ordering this is the
> most-significant byte; for a little-endian ordering this is the
> least-significant byte."
>
> contradicts your claim [...]

One can argue about the meaning of the text in the reference manual. 
But in the end, the behavior of real processors is what we are forced to 
deal with.

In the case of all existing OCTEON processors, there is no Status[RE] 
bit, but you can switch the endianess of the entire CPU under software 
control.  I am really making statements based on how they actually work, 
not assertions about the meaning of the specification.  However, I do 
believe that this is what is specified.

If you have access to processors with a working Status[RE] bit, you 
could empirically determine how they work.

David Daney