All of lore.kernel.org
 help / color / mirror / Atom feed
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/5] irqchip: gicv3-its: support safe initialization
Date: Thu, 05 Mar 2015 12:05:33 +0000	[thread overview]
Message-ID: <54F8468D.7090902@arm.com> (raw)
In-Reply-To: <1425439098-10708-6-git-send-email-wuyun.wu@huawei.com>

On 04/03/15 03:18, Yun Wu wrote:
> It's unsafe to change the configurations of an activated ITS directly
> since this will lead to unpredictable results. This patch guarantees
> the ITSes being initialized are quiescent.
> 
> Signed-off-by: Yun Wu <wuyun.wu@huawei.com>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index d13c24e..9e09aa0 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1320,6 +1320,34 @@ static const struct irq_domain_ops its_domain_ops = {
>  	.deactivate		= its_irq_domain_deactivate,
>  };
> 
> +static int its_check_quiesced(void __iomem *base)

Another nitpick: Rather than "its_check_quiesced", how about
"its_force_quiescent" instead? Because this does a lot more than just
checking.

> +{
> +	u32 count = 1000000;	/* 1s */
> +	u32 val;
> +
> +	val = readl_relaxed(base + GITS_CTLR);
> +	if (val & GITS_CTLR_QUIESCENT)
> +		return 0;
> +
> +	/* Disable the generation of all interrupts to this ITS */
> +	val &= ~GITS_CTLR_ENABLE;
> +	writel_relaxed(val, base + GITS_CTLR);
> +
> +	/* Poll GITS_CTLR and wait until ITS becomes quiescent */
> +	while (1) {
> +		val = readl_relaxed(base + GITS_CTLR);
> +		if (val & GITS_CTLR_QUIESCENT)
> +			return 0;
> +
> +		count--;
> +		if (!count)
> +			return -EBUSY;
> +
> +		cpu_relax();
> +		udelay(1);
> +	}
> +}
> +

I still dislike this repeated pattern, but I don't have a good solution
so far.

>  static int its_probe(struct device_node *node, struct irq_domain *parent)
>  {
>  	struct resource res;
> @@ -1348,6 +1376,13 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
>  		goto out_unmap;
>  	}
> 
> +	err = its_check_quiesced(its_base);
> +	if (err) {
> +		pr_warn("%s: failed to quiesce, giving up\n",
> +			node->full_name);
> +		goto out_unmap;
> +	}
> +
>  	pr_info("ITS: %s\n", node->full_name);
> 
>  	its = kzalloc(sizeof(*its), GFP_KERNEL);
> --
> 1.8.0
> 
> 
> 

Assuming you fix the above nitpick:

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Yun Wu <wuyun.wu@huawei.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"jason@lakedaemon.net" <jason@lakedaemon.net>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 5/5] irqchip: gicv3-its: support safe initialization
Date: Thu, 05 Mar 2015 12:05:33 +0000	[thread overview]
Message-ID: <54F8468D.7090902@arm.com> (raw)
In-Reply-To: <1425439098-10708-6-git-send-email-wuyun.wu@huawei.com>

On 04/03/15 03:18, Yun Wu wrote:
> It's unsafe to change the configurations of an activated ITS directly
> since this will lead to unpredictable results. This patch guarantees
> the ITSes being initialized are quiescent.
> 
> Signed-off-by: Yun Wu <wuyun.wu@huawei.com>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index d13c24e..9e09aa0 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1320,6 +1320,34 @@ static const struct irq_domain_ops its_domain_ops = {
>  	.deactivate		= its_irq_domain_deactivate,
>  };
> 
> +static int its_check_quiesced(void __iomem *base)

Another nitpick: Rather than "its_check_quiesced", how about
"its_force_quiescent" instead? Because this does a lot more than just
checking.

> +{
> +	u32 count = 1000000;	/* 1s */
> +	u32 val;
> +
> +	val = readl_relaxed(base + GITS_CTLR);
> +	if (val & GITS_CTLR_QUIESCENT)
> +		return 0;
> +
> +	/* Disable the generation of all interrupts to this ITS */
> +	val &= ~GITS_CTLR_ENABLE;
> +	writel_relaxed(val, base + GITS_CTLR);
> +
> +	/* Poll GITS_CTLR and wait until ITS becomes quiescent */
> +	while (1) {
> +		val = readl_relaxed(base + GITS_CTLR);
> +		if (val & GITS_CTLR_QUIESCENT)
> +			return 0;
> +
> +		count--;
> +		if (!count)
> +			return -EBUSY;
> +
> +		cpu_relax();
> +		udelay(1);
> +	}
> +}
> +

I still dislike this repeated pattern, but I don't have a good solution
so far.

>  static int its_probe(struct device_node *node, struct irq_domain *parent)
>  {
>  	struct resource res;
> @@ -1348,6 +1376,13 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
>  		goto out_unmap;
>  	}
> 
> +	err = its_check_quiesced(its_base);
> +	if (err) {
> +		pr_warn("%s: failed to quiesce, giving up\n",
> +			node->full_name);
> +		goto out_unmap;
> +	}
> +
>  	pr_info("ITS: %s\n", node->full_name);
> 
>  	its = kzalloc(sizeof(*its), GFP_KERNEL);
> --
> 1.8.0
> 
> 
> 

Assuming you fix the above nitpick:

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2015-03-05 12:05 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-04  3:18 [PATCH v3 0/5] enhance configuring an ITS Yun Wu
2015-03-04  3:18 ` Yun Wu
2015-03-04  3:18 ` [PATCH v3 1/5] irqchip: gicv3-its: zero itt before handling to hardware Yun Wu
2015-03-04  3:18   ` Yun Wu
2015-03-04  3:18 ` [PATCH v3 2/5] irqchip: gicv3-its: use 64KB page as default granule Yun Wu
2015-03-04  3:18   ` Yun Wu
2015-03-04  3:18 ` [PATCH v3 3/5] irqchip: gicv3-its: add limitation to page order Yun Wu
2015-03-04  3:18   ` Yun Wu
2015-03-05 11:22   ` Marc Zyngier
2015-03-05 11:22     ` Marc Zyngier
2015-03-04  3:18 ` [PATCH v3 4/5] irqchip: gicv3-its: define macros for GITS_CTLR fields Yun Wu
2015-03-04  3:18   ` Yun Wu
2015-03-05 11:59   ` Marc Zyngier
2015-03-05 11:59     ` Marc Zyngier
2015-03-04  3:18 ` [PATCH v3 5/5] irqchip: gicv3-its: support safe initialization Yun Wu
2015-03-04  3:18   ` Yun Wu
2015-03-05 12:05   ` Marc Zyngier [this message]
2015-03-05 12:05     ` Marc Zyngier
2015-03-06  1:34     ` Yun Wu (Abel)
2015-03-06  1:34       ` Yun Wu (Abel)
2015-03-05 12:12 ` [PATCH v3 0/5] enhance configuring an ITS Marc Zyngier
2015-03-05 12:12   ` Marc Zyngier
2015-03-06  1:36   ` Yun Wu (Abel)
2015-03-06  1:36     ` Yun Wu (Abel)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=54F8468D.7090902@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.