From: Markos Chandras <Markos.Chandras@imgtec.com>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Subject: Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes
Date: Mon, 9 Mar 2015 08:43:32 +0000 [thread overview]
Message-ID: <54FD5D34.7060201@imgtec.com> (raw)
In-Reply-To: <alpine.LFD.2.11.1503050245540.18344@eddie.linux-mips.org>
On 03/05/2015 01:46 PM, Maciej W. Rozycki wrote:
> On Tue, 3 Mar 2015, Markos Chandras wrote:
>
>> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
>> functions") added support for MIPS R6 cache flushes but it used the
>> wrong base address register to perform the flushes so the same lines
>> were flushed over and over. Moreover, replace the "addiu" instructions
>> with LONG_ADDIU so the correct base address is calculated for 64-bit
>> cores.
>
> Since this operates on addresses shouldn't PTR_ADDIU be used instead?
>
> Maciej
>
I don't know. I thought PTR_ADDIU should be used for pointers but the
arguments in these macros are "unsigned long".
--
markos
WARNING: multiple messages have this Message-ID (diff)
From: Markos Chandras <Markos.Chandras@imgtec.com>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes
Date: Mon, 9 Mar 2015 08:43:32 +0000 [thread overview]
Message-ID: <54FD5D34.7060201@imgtec.com> (raw)
Message-ID: <20150309084332.LDEpTvskEOd5Oyl4QwtIx9ZdJJ-sUU-KIim56Kghp3w@z> (raw)
In-Reply-To: <alpine.LFD.2.11.1503050245540.18344@eddie.linux-mips.org>
On 03/05/2015 01:46 PM, Maciej W. Rozycki wrote:
> On Tue, 3 Mar 2015, Markos Chandras wrote:
>
>> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll
>> functions") added support for MIPS R6 cache flushes but it used the
>> wrong base address register to perform the flushes so the same lines
>> were flushed over and over. Moreover, replace the "addiu" instructions
>> with LONG_ADDIU so the correct base address is calculated for 64-bit
>> cores.
>
> Since this operates on addresses shouldn't PTR_ADDIU be used instead?
>
> Maciej
>
I don't know. I thought PTR_ADDIU should be used for pointers but the
arguments in these macros are "unsigned long".
--
markos
next prev parent reply other threads:[~2015-03-09 8:43 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-03 18:48 [PATCH 0/4] MIPS R6 fixes for 4.0 Markos Chandras
2015-03-03 18:48 ` Markos Chandras
2015-03-03 18:48 ` [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes Markos Chandras
2015-03-03 18:48 ` Markos Chandras
2015-03-05 13:46 ` Maciej W. Rozycki
2015-03-09 8:43 ` Markos Chandras [this message]
2015-03-09 8:43 ` Markos Chandras
2015-03-23 20:40 ` Maciej W. Rozycki
2015-03-24 8:59 ` Markos Chandras
2015-03-24 8:59 ` Markos Chandras
2015-03-03 18:48 ` [PATCH 2/4] MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case Markos Chandras
2015-03-03 18:48 ` Markos Chandras
2015-03-03 18:48 ` [PATCH 3/4] MIPS: kernel: entry.S: Set correct ISA level for mips_ihb Markos Chandras
2015-03-03 18:48 ` Markos Chandras
2015-03-03 18:48 ` [PATCH 4/4] MIPS; asm: bitops: Add missing ISA levels for MIPS R6 Markos Chandras
2015-03-03 18:48 ` Markos Chandras
2015-03-09 15:24 ` Markos Chandras
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