* [PATCH 0/4] MIPS R6 fixes for 4.0
@ 2015-03-03 18:48 ` Markos Chandras
0 siblings, 0 replies; 17+ messages in thread
From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw)
To: linux-mips; +Cc: Markos Chandras
Hi,
A few R6 fixes for 4.0.
Please consider applying them in time for Linux 4.0
Markos Chandras (4):
MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache
flushes
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS; asm: bitops: Add missing ISA levels for MIPS R6
arch/mips/include/asm/bitops.h | 3 ++
arch/mips/include/asm/r4kcache.h | 88 ++++++++++++++++++++--------------------
arch/mips/include/asm/spinlock.h | 2 +-
arch/mips/kernel/entry.S | 3 +-
4 files changed, 50 insertions(+), 46 deletions(-)
--
2.3.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH 0/4] MIPS R6 fixes for 4.0 @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Hi, A few R6 fixes for 4.0. Please consider applying them in time for Linux 4.0 Markos Chandras (4): MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS; asm: bitops: Add missing ISA levels for MIPS R6 arch/mips/include/asm/bitops.h | 3 ++ arch/mips/include/asm/r4kcache.h | 88 ++++++++++++++++++++-------------------- arch/mips/include/asm/spinlock.h | 2 +- arch/mips/kernel/entry.S | 3 +- 4 files changed, 50 insertions(+), 46 deletions(-) -- 2.3.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores. Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/r4kcache.h | 88 ++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 1b22d2da88a1..d329f7328bd4 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -12,6 +12,7 @@ #ifndef _ASM_R4KCACHE_H #define _ASM_R4KCACHE_H +#include <linux/stringify.h> #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/compiler.h> @@ -344,7 +345,7 @@ static inline void invalidate_tcache_page(unsigned long addr) " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ - " addiu $1, $0, 0x100 \n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x010($1)\n" \ " cache %1, 0x020($1); cache %1, 0x030($1)\n" \ " cache %1, 0x040($1); cache %1, 0x050($1)\n" \ @@ -368,17 +369,17 @@ static inline void invalidate_tcache_page(unsigned long addr) " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ - " addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ - " addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ @@ -396,25 +397,25 @@ static inline void invalidate_tcache_page(unsigned long addr) " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " .set pop\n" \ @@ -429,39 +430,38 @@ static inline void invalidate_tcache_page(unsigned long addr) " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") added support for MIPS R6 cache flushes but it used the wrong base address register to perform the flushes so the same lines were flushed over and over. Moreover, replace the "addiu" instructions with LONG_ADDIU so the correct base address is calculated for 64-bit cores. Fixes: 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/r4kcache.h | 88 ++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 1b22d2da88a1..d329f7328bd4 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -12,6 +12,7 @@ #ifndef _ASM_R4KCACHE_H #define _ASM_R4KCACHE_H +#include <linux/stringify.h> #include <asm/asm.h> #include <asm/cacheops.h> #include <asm/compiler.h> @@ -344,7 +345,7 @@ static inline void invalidate_tcache_page(unsigned long addr) " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \ " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ - " addiu $1, $0, 0x100 \n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x010($1)\n" \ " cache %1, 0x020($1); cache %1, 0x030($1)\n" \ " cache %1, 0x040($1); cache %1, 0x050($1)\n" \ @@ -368,17 +369,17 @@ static inline void invalidate_tcache_page(unsigned long addr) " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \ " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ - " addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ - " addiu $1, $1, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \ " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ @@ -396,25 +397,25 @@ static inline void invalidate_tcache_page(unsigned long addr) " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \ " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ " .set pop\n" \ @@ -429,39 +430,38 @@ static inline void invalidate_tcache_page(unsigned long addr) " .set mips64r6\n" \ " .set noat\n" \ " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ - " addiu $1, %0, 0x100\n" \ + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ " .set pop\n" \ : \ : "r" (base), \ -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes 2015-03-03 18:48 ` Markos Chandras (?) @ 2015-03-05 13:46 ` Maciej W. Rozycki 2015-03-09 8:43 ` Markos Chandras -1 siblings, 1 reply; 17+ messages in thread From: Maciej W. Rozycki @ 2015-03-05 13:46 UTC (permalink / raw) To: Markos Chandras; +Cc: linux-mips On Tue, 3 Mar 2015, Markos Chandras wrote: > Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll > functions") added support for MIPS R6 cache flushes but it used the > wrong base address register to perform the flushes so the same lines > were flushed over and over. Moreover, replace the "addiu" instructions > with LONG_ADDIU so the correct base address is calculated for 64-bit > cores. Since this operates on addresses shouldn't PTR_ADDIU be used instead? Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-09 8:43 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-09 8:43 UTC (permalink / raw) To: Maciej W. Rozycki; +Cc: linux-mips On 03/05/2015 01:46 PM, Maciej W. Rozycki wrote: > On Tue, 3 Mar 2015, Markos Chandras wrote: > >> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll >> functions") added support for MIPS R6 cache flushes but it used the >> wrong base address register to perform the flushes so the same lines >> were flushed over and over. Moreover, replace the "addiu" instructions >> with LONG_ADDIU so the correct base address is calculated for 64-bit >> cores. > > Since this operates on addresses shouldn't PTR_ADDIU be used instead? > > Maciej > I don't know. I thought PTR_ADDIU should be used for pointers but the arguments in these macros are "unsigned long". -- markos ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-09 8:43 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-09 8:43 UTC (permalink / raw) To: Maciej W. Rozycki; +Cc: linux-mips On 03/05/2015 01:46 PM, Maciej W. Rozycki wrote: > On Tue, 3 Mar 2015, Markos Chandras wrote: > >> Commit 934c79231c1b("MIPS: asm: r4kcache: Add MIPS R6 cache unroll >> functions") added support for MIPS R6 cache flushes but it used the >> wrong base address register to perform the flushes so the same lines >> were flushed over and over. Moreover, replace the "addiu" instructions >> with LONG_ADDIU so the correct base address is calculated for 64-bit >> cores. > > Since this operates on addresses shouldn't PTR_ADDIU be used instead? > > Maciej > I don't know. I thought PTR_ADDIU should be used for pointers but the arguments in these macros are "unsigned long". -- markos ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes 2015-03-09 8:43 ` Markos Chandras (?) @ 2015-03-23 20:40 ` Maciej W. Rozycki 2015-03-24 8:59 ` Markos Chandras -1 siblings, 1 reply; 17+ messages in thread From: Maciej W. Rozycki @ 2015-03-23 20:40 UTC (permalink / raw) To: Markos Chandras; +Cc: linux-mips On Mon, 9 Mar 2015, Markos Chandras wrote: > > Since this operates on addresses shouldn't PTR_ADDIU be used instead? > > > > Maciej > > > > I don't know. I thought PTR_ADDIU should be used for pointers but the > arguments in these macros are "unsigned long". Hmm, good point. I think we should match the C data type used even though we have an assumption that sizeof(long) == sizeof(void *), so your change looks right to me as it stands. I think we have a convention to separate `linux' from `asm' inclusions by an empty line though, so I suggest that you add one here: > diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h > index 1b22d2da88a1..d329f7328bd4 100644 > --- a/arch/mips/include/asm/r4kcache.h > +++ b/arch/mips/include/asm/r4kcache.h > @@ -12,6 +12,7 @@ > #ifndef _ASM_R4KCACHE_H > #define _ASM_R4KCACHE_H > > +#include <linux/stringify.h> > #include <asm/asm.h> > #include <asm/cacheops.h> > #include <asm/compiler.h> as well. I can offer you my review tag if you repost the change with this trivial update. Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-24 8:59 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-24 8:59 UTC (permalink / raw) To: Maciej W. Rozycki; +Cc: linux-mips On 03/23/2015 08:40 PM, Maciej W. Rozycki wrote: > On Mon, 9 Mar 2015, Markos Chandras wrote: > >>> Since this operates on addresses shouldn't PTR_ADDIU be used instead? >>> >>> Maciej >>> >> >> I don't know. I thought PTR_ADDIU should be used for pointers but the >> arguments in these macros are "unsigned long". > > Hmm, good point. I think we should match the C data type used even > though we have an assumption that sizeof(long) == sizeof(void *), so your > change looks right to me as it stands. > > I think we have a convention to separate `linux' from `asm' inclusions by > an empty line though, so I suggest that you add one here: > >> diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h >> index 1b22d2da88a1..d329f7328bd4 100644 >> --- a/arch/mips/include/asm/r4kcache.h >> +++ b/arch/mips/include/asm/r4kcache.h >> @@ -12,6 +12,7 @@ >> #ifndef _ASM_R4KCACHE_H >> #define _ASM_R4KCACHE_H >> >> +#include <linux/stringify.h> >> #include <asm/asm.h> >> #include <asm/cacheops.h> >> #include <asm/compiler.h> > > as well. I can offer you my review tag if you repost the change with this > trivial update. > > Maciej > Hi, I believe Ralf can fix this trivial change whenever he gets to apply these patches. If not, I will post it again. -- markos ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes @ 2015-03-24 8:59 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-24 8:59 UTC (permalink / raw) To: Maciej W. Rozycki; +Cc: linux-mips On 03/23/2015 08:40 PM, Maciej W. Rozycki wrote: > On Mon, 9 Mar 2015, Markos Chandras wrote: > >>> Since this operates on addresses shouldn't PTR_ADDIU be used instead? >>> >>> Maciej >>> >> >> I don't know. I thought PTR_ADDIU should be used for pointers but the >> arguments in these macros are "unsigned long". > > Hmm, good point. I think we should match the C data type used even > though we have an assumption that sizeof(long) == sizeof(void *), so your > change looks right to me as it stands. > > I think we have a convention to separate `linux' from `asm' inclusions by > an empty line though, so I suggest that you add one here: > >> diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h >> index 1b22d2da88a1..d329f7328bd4 100644 >> --- a/arch/mips/include/asm/r4kcache.h >> +++ b/arch/mips/include/asm/r4kcache.h >> @@ -12,6 +12,7 @@ >> #ifndef _ASM_R4KCACHE_H >> #define _ASM_R4KCACHE_H >> >> +#include <linux/stringify.h> >> #include <asm/asm.h> >> #include <asm/cacheops.h> >> #include <asm/compiler.h> > > as well. I can offer you my review tag if you repost the change with this > trivial update. > > Maciej > Hi, I believe Ralf can fix this trivial change whenever he gets to apply these patches. If not, I will post it again. -- markos ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/4] MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case. Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/spinlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index b4548690ade9..1fca2e0793dc 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) if (R10000_LLSC_WAR) { __asm__ __volatile__( "1: ll %1, %2 # arch_read_unlock \n" - " addiu %1, 1 \n" + " addiu %1, -1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu") replaced the "sub" instruction with addiu but it did not update the immediate value in the R10000_LLSC_WAR case. Fixes: 5753762cbd1c("MIPS: asm: spinlock: Replace "sub" instruction with "addiu"") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/spinlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index b4548690ade9..1fca2e0793dc 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -263,7 +263,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw) if (R10000_LLSC_WAR) { __asm__ __volatile__( "1: ll %1, %2 # arch_read_unlock \n" - " addiu %1, 1 \n" + " addiu %1, -1 \n" " sc %1, %0 \n" " beqzl %1, 1b \n" : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp) -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] MIPS: kernel: entry.S: Set correct ISA level for mips_ihb @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") added the MIPSR6 definition but it did not update the ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro. Fixes: 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/kernel/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index af41ba6db960..7791840cf22c 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -10,6 +10,7 @@ #include <asm/asm.h> #include <asm/asmmacro.h> +#include <asm/compiler.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/stackframe.h> @@ -185,7 +186,7 @@ syscall_exit_work: * For C code use the inline version named instruction_hazard(). */ LEAF(mips_ihb) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW jr.hb ra nop END(mips_ihb) -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/4] MIPS: kernel: entry.S: Set correct ISA level for mips_ihb @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") added the MIPSR6 definition but it did not update the ISA level of the actual assembly code so a pre-MIPSR6 jr.hb instruction was generated instead. Fix this by using the MISP_ISA_LEVEL_RAW macro. Fixes: 6ebb496ffc7e("MIPS: kernel: entry.S: Add MIPS R6 related definitions") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/kernel/entry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index af41ba6db960..7791840cf22c 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -10,6 +10,7 @@ #include <asm/asm.h> #include <asm/asmmacro.h> +#include <asm/compiler.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/stackframe.h> @@ -185,7 +186,7 @@ syscall_exit_work: * For C code use the inline version named instruction_hazard(). */ LEAF(mips_ihb) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW jr.hb ra nop END(mips_ihb) -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] MIPS; asm: bitops: Add missing ISA levels for MIPS R6 @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 87a927eff4da("MIPS: asm: bitops: update ISA constraints for MIPS R6 support") replaced hardcoded ISA levels in order to support MIPS R6 new opcodes but it missed a few cases. Fixes: 87a927eff4da("MIPS: asm: bitops: update ISA constraints for MIPS R6 support") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/bitops.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 9f935f6aa996..077bc8b9dcc5 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -85,6 +85,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # set_bit \n" " " __INS "%0, %3, %2, 1 \n" " " __SC "%0, %1 \n" @@ -137,6 +138,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # clear_bit \n" " " __INS "%0, $0, %2, 1 \n" " " __SC "%0, %1 \n" @@ -365,6 +367,7 @@ static inline int test_and_clear_bit(unsigned long nr, do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # test_and_clear_bit \n" " " __EXT "%2, %0, %3, 1 \n" " " __INS "%0, $0, %3, 1 \n" -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] MIPS; asm: bitops: Add missing ISA levels for MIPS R6 @ 2015-03-03 18:48 ` Markos Chandras 0 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-03 18:48 UTC (permalink / raw) To: linux-mips; +Cc: Markos Chandras Commit 87a927eff4da("MIPS: asm: bitops: update ISA constraints for MIPS R6 support") replaced hardcoded ISA levels in order to support MIPS R6 new opcodes but it missed a few cases. Fixes: 87a927eff4da("MIPS: asm: bitops: update ISA constraints for MIPS R6 support") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> --- arch/mips/include/asm/bitops.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 9f935f6aa996..077bc8b9dcc5 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -85,6 +85,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # set_bit \n" " " __INS "%0, %3, %2, 1 \n" " " __SC "%0, %1 \n" @@ -137,6 +138,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) } else if (kernel_uses_llsc && __builtin_constant_p(bit)) { do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # clear_bit \n" " " __INS "%0, $0, %2, 1 \n" " " __SC "%0, %1 \n" @@ -365,6 +367,7 @@ static inline int test_and_clear_bit(unsigned long nr, do { __asm__ __volatile__( + " .set "MIPS_ISA_ARCH_LEVEL" \n" " " __LL "%0, %1 # test_and_clear_bit \n" " " __EXT "%2, %0, %3, 1 \n" " " __INS "%0, $0, %3, 1 \n" -- 2.3.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] MIPS; asm: bitops: Add missing ISA levels for MIPS R6 2015-03-03 18:48 ` Markos Chandras (?) @ 2015-03-09 15:24 ` Markos Chandras -1 siblings, 0 replies; 17+ messages in thread From: Markos Chandras @ 2015-03-09 15:24 UTC (permalink / raw) To: linux-mips@linux-mips.org On 03/03/2015 06:48 PM, Markos Chandras wrote: > Commit 87a927eff4da("MIPS: asm: bitops: update ISA constraints for > MIPS R6 support") replaced hardcoded ISA levels in order to support > MIPS R6 new opcodes but it missed a few cases. > > Fixes: 87a927eff4da("MIPS: asm: bitops: update ISA constraints for MIPS R6 support") > Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> > --- This patch is not needed since it introduced new ".set" statements for no good reason. I marked it as rejected in patchwork. -- markos ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2015-03-24 9:00 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-03-03 18:48 [PATCH 0/4] MIPS R6 fixes for 4.0 Markos Chandras 2015-03-03 18:48 ` Markos Chandras 2015-03-03 18:48 ` [PATCH 1/4] MIPS: asm: r4kcache: Use correct base register for MIPS R6 cache flushes Markos Chandras 2015-03-03 18:48 ` Markos Chandras 2015-03-05 13:46 ` Maciej W. Rozycki 2015-03-09 8:43 ` Markos Chandras 2015-03-09 8:43 ` Markos Chandras 2015-03-23 20:40 ` Maciej W. Rozycki 2015-03-24 8:59 ` Markos Chandras 2015-03-24 8:59 ` Markos Chandras 2015-03-03 18:48 ` [PATCH 2/4] MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case Markos Chandras 2015-03-03 18:48 ` Markos Chandras 2015-03-03 18:48 ` [PATCH 3/4] MIPS: kernel: entry.S: Set correct ISA level for mips_ihb Markos Chandras 2015-03-03 18:48 ` Markos Chandras 2015-03-03 18:48 ` [PATCH 4/4] MIPS; asm: bitops: Add missing ISA levels for MIPS R6 Markos Chandras 2015-03-03 18:48 ` Markos Chandras 2015-03-09 15:24 ` Markos Chandras
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