Re: [PATCH] pci: octeon: Remove udelay() causing huge IRQ latency

[David Daney <ddaney@caviumnetworks.com>]

On 03/18/2015 06:05 AM, Alexander Sverdlin wrote:
> udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon
> platforms because these operations are called from PCI_OP_READ() and
> PCI_OP_WRITE() under raw_spin_lock_irqsave().
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>

Can you say how it was tested.  In principle I have no objections, but 
it would be nice to know how it was validated.

Thanks,
David Daney


> ---
>   arch/mips/include/asm/octeon/pci-octeon.h |    3 ---
>   arch/mips/pci/pci-octeon.c                |    6 ------
>   arch/mips/pci/pcie-octeon.c               |    8 --------
>   3 files changed, 0 insertions(+), 17 deletions(-)
>
> diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
> index 64ba56a..1884609 100644
> --- a/arch/mips/include/asm/octeon/pci-octeon.h
> +++ b/arch/mips/include/asm/octeon/pci-octeon.h
> @@ -11,9 +11,6 @@
>
>   #include <linux/pci.h>
>
> -/* Some PCI cards require delays when accessing config space. */
> -#define PCI_CONFIG_SPACE_DELAY 10000
> -
>   /*
>    * The physical memory base mapped by BAR1.  256MB at the end of the
>    * first 4GB.
> diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
> index a04af55..01c604a 100644
> --- a/arch/mips/pci/pci-octeon.c
> +++ b/arch/mips/pci/pci-octeon.c
> @@ -271,9 +271,6 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
>   	pci_addr.s.func = devfn & 0x7;
>   	pci_addr.s.reg = reg;
>
> -#if PCI_CONFIG_SPACE_DELAY
> -	udelay(PCI_CONFIG_SPACE_DELAY);
> -#endif
>   	switch (size) {
>   	case 4:
>   		*val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
> @@ -308,9 +305,6 @@ static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
>   	pci_addr.s.func = devfn & 0x7;
>   	pci_addr.s.reg = reg;
>
> -#if PCI_CONFIG_SPACE_DELAY
> -	udelay(PCI_CONFIG_SPACE_DELAY);
> -#endif
>   	switch (size) {
>   	case 4:
>   		cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
> diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
> index 1bb0b2b..99f3db4 100644
> --- a/arch/mips/pci/pcie-octeon.c
> +++ b/arch/mips/pci/pcie-octeon.c
> @@ -1762,14 +1762,6 @@ static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
>   	default:
>   		return PCIBIOS_FUNC_NOT_SUPPORTED;
>   	}
> -#if PCI_CONFIG_SPACE_DELAY
> -	/*
> -	 * Delay on writes so that devices have time to come up. Some
> -	 * bridges need this to allow time for the secondary busses to
> -	 * work
> -	 */
> -	udelay(PCI_CONFIG_SPACE_DELAY);
> -#endif
>   	return PCIBIOS_SUCCESSFUL;
>   }
>
>