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* [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us?
@ 2015-04-16 11:30 Zhoupeng
  0 siblings, 0 replies; 5+ messages in thread
From: Zhoupeng @ 2015-04-16 11:30 UTC (permalink / raw)
  To: xenomai

I'm using Rtnet with 82583 ethernet card.
It takes about 2us to send AF_PACKET using rt_dev_sendmsg(), about 200 bytes of data.

It is pretty fast, but I want to find what takes so long.
At last I find that "writel(tx_ring->tail)" spend above 1us to complete.

This is just MMIO write to 82583, of course MMIO is uncache.
And PCIE ASPM is disabled, so L0s is not the problem.

I think PCIE Memory Write TLPs is fast enough, but why spend so much time?

thanks,

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us?
@ 2015-04-16 12:26 Mariusz Janiak
  2015-04-16 14:39 ` Zhoupeng
  0 siblings, 1 reply; 5+ messages in thread
From: Mariusz Janiak @ 2015-04-16 12:26 UTC (permalink / raw)
  To: Zhoupeng; +Cc: xenomai

Dnia Czwartek, 16 Kwietnia 2015 13:30 Zhoupeng <zhoupeng1982@qq.com> napisał(a) 
> I'm using Rtnet with 82583 ethernet card.
> It takes about 2us to send AF_PACKET using rt_dev_sendmsg(), about 200 bytes of data.
> 
> It is pretty fast, but I want to find what takes so long.
> At last I find that "writel(tx_ring-&gt;tail)" spend above 1us to complete.
> 
> This is just MMIO write to 82583, of course MMIO is uncache.
> And PCIE ASPM is disabled, so L0s is not the problem.
> 
> I think PCIE Memory Write TLPs is fast enough, but why spend so much time?

Hi,

There is an interesting article that may be relevant to this issue

"PCI Express as a Killer of Software-based Real-Time Ethernet"

You can find copy in the attachment. 

Best
Mariusz


 
> thanks,
> _______________________________________________
> Xenomai mailing list
> Xenomai@xenomai.org
> http://www.xenomai.org/mailman/listinfo/xenomai

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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us?
  2015-04-16 12:26 [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us? Mariusz Janiak
@ 2015-04-16 14:39 ` Zhoupeng
  2015-04-16 14:46   ` Gilles Chanteperdrix
  2015-04-16 19:15   ` Gilles Chanteperdrix
  0 siblings, 2 replies; 5+ messages in thread
From: Zhoupeng @ 2015-04-16 14:39 UTC (permalink / raw)
  To: Mariusz Janiak; +Cc: xenomai

&gt;&gt; This is just MMIO write to 82583, of course MMIO is uncache.
&gt;&gt; And PCIE ASPM is disabled, so L0s is not the problem.
&gt;&gt; 
&gt;&gt; I think PCIE Memory Write TLPs is fast enough, but why spend so much time?

&gt;There is an interesting article that may be relevant to this issue
&gt;
&gt;"PCI Express as a Killer of Software-based Real-Time Ethernet"

I have read the article carefully.
The author don't mention PCIE ASPM, Latency will be better by disable it.

Every rt_dev_sendmsg will trigger one writel(tx_ring-&gt;tail) in Rtnet.
As the "writel" is time expensive, improvement may be done to Rtnet:
using rtskb to buffer multiple packets, and using one IOCTL to trigger "writel".

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us?
  2015-04-16 14:39 ` Zhoupeng
@ 2015-04-16 14:46   ` Gilles Chanteperdrix
  2015-04-16 19:15   ` Gilles Chanteperdrix
  1 sibling, 0 replies; 5+ messages in thread
From: Gilles Chanteperdrix @ 2015-04-16 14:46 UTC (permalink / raw)
  To: Zhoupeng; +Cc: xenomai

On Thu, Apr 16, 2015 at 10:39:59PM +0800, Zhoupeng wrote:
> &gt;&gt; This is just MMIO write to 82583, of course MMIO is uncache.
> &gt;&gt; And PCIE ASPM is disabled, so L0s is not the problem.
> &gt;&gt; 
> &gt;&gt; I think PCIE Memory Write TLPs is fast enough, but why spend so much time?
> 
> &gt;There is an interesting article that may be relevant to this issue
> &gt;
> &gt;"PCI Express as a Killer of Software-based Real-Time Ethernet"
> 
> I have read the article carefully.
> The author don't mention PCIE ASPM, Latency will be better by disable it.
> 
> Every rt_dev_sendmsg will trigger one writel(tx_ring-&gt;tail) in Rtnet.
> As the "writel" is time expensive, improvement may be done to Rtnet:
> using rtskb to buffer multiple packets, and using one IOCTL to trigger "writel".

Patches welcome.

-- 
					    Gilles.


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us?
  2015-04-16 14:39 ` Zhoupeng
  2015-04-16 14:46   ` Gilles Chanteperdrix
@ 2015-04-16 19:15   ` Gilles Chanteperdrix
  1 sibling, 0 replies; 5+ messages in thread
From: Gilles Chanteperdrix @ 2015-04-16 19:15 UTC (permalink / raw)
  To: Zhoupeng; +Cc: xenomai

On Thu, Apr 16, 2015 at 10:39:59PM +0800, Zhoupeng wrote:
> &gt;&gt; This is just MMIO write to 82583, of course MMIO is uncache.
> &gt;&gt; And PCIE ASPM is disabled, so L0s is not the problem.
> &gt;&gt; 
> &gt;&gt; I think PCIE Memory Write TLPs is fast enough, but why spend so much time?
> 
> &gt;There is an interesting article that may be relevant to this issue
> &gt;
> &gt;"PCI Express as a Killer of Software-based Real-Time Ethernet"
> 
> I have read the article carefully.
> The author don't mention PCIE ASPM, Latency will be better by disable it.
> 
> Every rt_dev_sendmsg will trigger one writel(tx_ring-&gt;tail) in Rtnet.
> As the "writel" is time expensive, improvement may be done to Rtnet:
> using rtskb to buffer multiple packets, and using one IOCTL to trigger "writel".

This optimization increases bandwidth at the expense of latency,
exactly the contrary to what RTnet is trying to achieve. So, patch
not welcome in fact. Or would be welcome a very careful patch which
does sends lone packets immediately, not queue them for sending them
later with a timeout or something.

-- 
					    Gilles.


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2015-04-16 19:15 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2015-04-16 12:26 [Xenomai] Rtnet e1000e 82583: slow writel(tx_ring->tail), takes above 1us? Mariusz Janiak
2015-04-16 14:39 ` Zhoupeng
2015-04-16 14:46   ` Gilles Chanteperdrix
2015-04-16 19:15   ` Gilles Chanteperdrix
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2015-04-16 11:30 Zhoupeng

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