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From: Yongbok Kim <yongbok.kim@imgtec.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Leon Alrae <Leon.Alrae@imgtec.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 3/3] target-mips: Misaligned Memory Accesses for MSA
Date: Fri, 1 May 2015 16:55:08 +0100	[thread overview]
Message-ID: <5543A1DC.4040303@imgtec.com> (raw)
In-Reply-To: <CAFEAcA-t1TAg-CzmjDxbt+z1m9QcJWiq2jkrDkcQJzH=+2QqEw@mail.gmail.com>

On 01/05/2015 16:43, Peter Maydell wrote:
> On 1 May 2015 at 16:24, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
>> MIPS SIMD Architecture vector loads and stores require misalignment support.
>> MSA Memory access should work as an atomic operation. Therefore, it has to
>> check validity of all the addresses for the operation.
>>
>> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
>> ---
>>  target-mips/op_helper.c |   30 ++++++++++++++++++++++++++++++
>>  1 files changed, 30 insertions(+), 0 deletions(-)
>>
>> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
>> index dacc92b..89a7de6 100644
>> --- a/target-mips/op_helper.c
>> +++ b/target-mips/op_helper.c
>> @@ -3571,6 +3571,24 @@ FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
>>  /* Element-by-element access macros */
>>  #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
>>
>> +#if !defined(CONFIG_USER_ONLY)
>> +static bool cpu_mips_validate_msa_block_access(CPUMIPSState *env,
>> +                                        target_ulong address, int df, int rw)
>> +{
>> +    int i;
>> +    for (i = 0; i < DF_ELEMENTS(df); i++) {
>> +        if (!cpu_mips_validate_access(env, address + (i << df),
>> +            address, (1 << df), rw)) {
>> +            CPUState *cs = CPU(mips_env_get_cpu(env));
>> +            helper_raise_exception_err(env, cs->exception_index,
>> +                                       env->error_code);
> I was wondering if this would get the correct PC in the exception
> case, but we always call save_cpu_state() before calling the
> msa_ld/st_df helpers, so it will.
>
> -- PMM
Yes it does because of the save_cpu_state(). Actually I have considered to use
cpu_restore_state() with GETRA() but it looks like using save_cpu_state() is quite
common in the target-mips. It would be good such clean-up for all the cases in the future work.
But this patch I would follow existing style for the consistency.

Regards,
Yongbok

  reply	other threads:[~2015-05-01 15:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-01 15:24 [Qemu-devel] [PATCH 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-01 15:24 ` [Qemu-devel] [PATCH 1/3] softmmu: Add size argument to do_unaligned_access() Yongbok Kim
2015-05-01 15:24 ` [Qemu-devel] [PATCH 2/3] target-mips: Misaligned Memory Accesses for R6 Yongbok Kim
2015-05-01 15:39   ` Peter Maydell
2015-05-01 15:24 ` [Qemu-devel] [PATCH 3/3] target-mips: Misaligned Memory Accesses for MSA Yongbok Kim
2015-05-01 15:43   ` Peter Maydell
2015-05-01 15:55     ` Yongbok Kim [this message]
2015-05-05 14:51     ` Leon Alrae
2015-05-05 19:54   ` Leon Alrae

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