Re: [PATCH v4 3/3] xen/iommu: arm: Use p2m_ipa_bits as stage2 input size

[Julien Grall <julien.grall@citrix.com>]

Hi Ian,

On 05/05/15 14:24, Ian Campbell wrote:
> On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote:
>> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>>
>> The Stage2 input-size must match what the CPU uses because
>> the SMMU and the CPU share page-tables.
>>
>> Test that the SMMU supports the P2M IPA bit size, use it if
>> supported or bail out if not.
>>
>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>> ---
>>  xen/drivers/passthrough/arm/smmu.c | 10 ++++++++--
>>  1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c
>> index 8a9b58b..d9f3931 100644
>> --- a/xen/drivers/passthrough/arm/smmu.c
>> +++ b/xen/drivers/passthrough/arm/smmu.c
>> @@ -2230,8 +2230,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>>  	size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
>>  	smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
>>  
>> -	/* Xen: Stage-2 input size is not restricted */
>> -	smmu->s2_input_size = size;
>> +	/* Xen: Stage-2 input size has to match p2m_ipa_bits.  */
>> +	if (size < p2m_ipa_bits) {
> 
> Referencing my question on 0/3, what if size > p2m_ipa_bits?

The would require more work because we would need to restrict the P2M
which would cause other trouble (see my answer on 0/3) such as the 1:1
mapping in dom0.

> Do we need to also check that we are configuring the same number of
> levels of PT etc, or is that already handled?

The SMMU only care about the number of IPA bits.

Regards,

-- 
Julien Grall