* [PATCH] nv50/ir: only enable mul saturate on G200+
@ 2015-05-09 7:31 Ilia Mirkin
[not found] ` <1431156678-1981-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2015-05-09 15:12 ` [Nouveau] " Tobias Klausmann
0 siblings, 2 replies; 3+ messages in thread
From: Ilia Mirkin @ 2015-05-09 7:31 UTC (permalink / raw)
To: mesa-dev; +Cc: nouveau, mesa-stable
Commit 44673512a84 enabled support for saturating fmul. However
experimentally this does not seem to work on the older chips. Restrict
the feature to G200 (NVA0) and later.
Reported-by: Pierre Moreau <pierre.morrow@free.fr>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90350
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
index 70180eb..ca545a6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
@@ -84,7 +84,7 @@ static const struct opProperties _initProps[] =
// neg abs not sat c[] s[], a[], imm
{ OP_ADD, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
{ OP_SUB, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
- { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
+ { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
{ OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
{ OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
{ OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
@@ -188,6 +188,9 @@ void TargetNV50::initOpInfo()
if (prop->mSat & 8)
opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
}
+
+ if (chipset >= 0xa0)
+ opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
}
unsigned int
--
2.3.6
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] nv50/ir: only enable mul saturate on G200+
[not found] ` <1431156678-1981-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
@ 2015-05-09 7:41 ` Pierre Moreau
0 siblings, 0 replies; 3+ messages in thread
From: Pierre Moreau @ 2015-05-09 7:41 UTC (permalink / raw)
To: Ilia Mirkin
Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
mesa-stable-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Tested-by: Pierre Moreau <pierre.morrow@free.fr>
----- Mail original -----
> Commit 44673512a84 enabled support for saturating fmul. However
> experimentally this does not seem to work on the older chips.
> Restrict
> the feature to G200 (NVA0) and later.
>
> Reported-by: Pierre Moreau <pierre.morrow@free.fr>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90350
> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
> Cc: mesa-stable@lists.freedesktop.org
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 5
> ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git
> a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> index 70180eb..ca545a6 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> @@ -84,7 +84,7 @@ static const struct opProperties _initProps[] =
> // neg abs not sat c[] s[], a[], imm
> { OP_ADD, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> { OP_SUB, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> - { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> + { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
> { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
> { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
> { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special
> constraint
> @@ -188,6 +188,9 @@ void TargetNV50::initOpInfo()
> if (prop->mSat & 8)
> opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
> }
> +
> + if (chipset >= 0xa0)
> + opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
> }
>
> unsigned int
> --
> 2.3.6
>
> _______________________________________________
> Nouveau mailing list
> Nouveau@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/nouveau
>
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Nouveau] [PATCH] nv50/ir: only enable mul saturate on G200+
2015-05-09 7:31 [PATCH] nv50/ir: only enable mul saturate on G200+ Ilia Mirkin
[not found] ` <1431156678-1981-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
@ 2015-05-09 15:12 ` Tobias Klausmann
1 sibling, 0 replies; 3+ messages in thread
From: Tobias Klausmann @ 2015-05-09 15:12 UTC (permalink / raw)
To: Ilia Mirkin, mesa-dev; +Cc: nouveau, mesa-stable
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
On 09.05.2015 09:31, Ilia Mirkin wrote:
> Commit 44673512a84 enabled support for saturating fmul. However
> experimentally this does not seem to work on the older chips. Restrict
> the feature to G200 (NVA0) and later.
>
> Reported-by: Pierre Moreau <pierre.morrow@free.fr>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90350
> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
> Cc: mesa-stable@lists.freedesktop.org
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> index 70180eb..ca545a6 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp
> @@ -84,7 +84,7 @@ static const struct opProperties _initProps[] =
> // neg abs not sat c[] s[], a[], imm
> { OP_ADD, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> { OP_SUB, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> - { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x1, 0x1, 0x2 },
> + { OP_MUL, 0x3, 0x0, 0x0, 0x0, 0x2, 0x1, 0x1, 0x2 },
> { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
> { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 },
> { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x1, 0x1, 0x0 }, // special constraint
> @@ -188,6 +188,9 @@ void TargetNV50::initOpInfo()
> if (prop->mSat & 8)
> opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
> }
> +
> + if (chipset >= 0xa0)
> + opInfo[OP_MUL].dstMods = NV50_IR_MOD_SAT;
> }
>
> unsigned int
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-05-09 15:12 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-05-09 7:31 [PATCH] nv50/ir: only enable mul saturate on G200+ Ilia Mirkin
[not found] ` <1431156678-1981-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2015-05-09 7:41 ` Pierre Moreau
2015-05-09 15:12 ` [Nouveau] " Tobias Klausmann
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.