From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling
Date: Thu, 25 Jun 2015 14:35:51 -0700 [thread overview]
Message-ID: <558C7437.2090306@codeaurora.org> (raw)
In-Reply-To: <558C72EB.8010502@oracle.com>
On 06/25/2015 02:30 PM, santosh shilimkar wrote:
> On 6/25/2015 2:02 PM, Stephen Boyd wrote:
>> On 06/25/2015 08:04 AM, santosh shilimkar wrote:
>>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote:
>>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error
>>>> handling
>>>> for Keystone devices
>>>>
>>>> Change Log
>>>>
>>>> v2:
>>>> - removing unused and sorting headers of keystone.c are moved to a
>>>> separate
>>>> patch.
>>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate
>>>> patches
>>>> - removed unused headers from keystone_ecc.c
>>>> - platsmp.c removed from the patch.
>>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler
>>>> - checked and handled existing echttps://lwn.net/Articles/593336/c
>>>> error before enabling ddr3 interrupt
>>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware
>>>> and
>>>> there is no reason to handle it by software
>>>>
>>> This version looks good to me. As already commented, I would have liked
>>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more
>>> time for others to come back. Otherwise I will queue this up for next
>>> window.
>>
>> Why not make this into an edac driver? I sent out an L1/L2 error
>> detection edac driver for Krait processors a year ago, but it stalled
>> due to some DT binding stuff[1]. This looks fairly similar.
>>
> Indeed the error detection part is very similar(expected as well
> considering the same processor L2 regs). I am not sure we need
> full driver only for that but at least the IRQ error handler
> related code can reside together. Lets see what RMK thinks
> on this.
>
There's an existing one for highbank (drivers/edac/highbank_l2_edac.c)
and there was a patch set for the pl310 as well[1]. I don't think we
want any architecture specific code for this, just use the EDAC framework.
[1] https://lkml.org/lkml/2014/3/2/87
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: santosh shilimkar
<santosh.shilimkar-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>,
Vitaly Andrianov <vitalya-l0cyMroinI0@public.gmane.org>,
ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
pawel.moll-5wv7dgnIgG8@public.gmane.org,
mark.rutland-5wv7dgnIgG8@public.gmane.org,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling
Date: Thu, 25 Jun 2015 14:35:51 -0700 [thread overview]
Message-ID: <558C7437.2090306@codeaurora.org> (raw)
In-Reply-To: <558C72EB.8010502-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
On 06/25/2015 02:30 PM, santosh shilimkar wrote:
> On 6/25/2015 2:02 PM, Stephen Boyd wrote:
>> On 06/25/2015 08:04 AM, santosh shilimkar wrote:
>>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote:
>>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error
>>>> handling
>>>> for Keystone devices
>>>>
>>>> Change Log
>>>>
>>>> v2:
>>>> - removing unused and sorting headers of keystone.c are moved to a
>>>> separate
>>>> patch.
>>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate
>>>> patches
>>>> - removed unused headers from keystone_ecc.c
>>>> - platsmp.c removed from the patch.
>>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler
>>>> - checked and handled existing echttps://lwn.net/Articles/593336/c
>>>> error before enabling ddr3 interrupt
>>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware
>>>> and
>>>> there is no reason to handle it by software
>>>>
>>> This version looks good to me. As already commented, I would have liked
>>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more
>>> time for others to come back. Otherwise I will queue this up for next
>>> window.
>>
>> Why not make this into an edac driver? I sent out an L1/L2 error
>> detection edac driver for Krait processors a year ago, but it stalled
>> due to some DT binding stuff[1]. This looks fairly similar.
>>
> Indeed the error detection part is very similar(expected as well
> considering the same processor L2 regs). I am not sure we need
> full driver only for that but at least the IRQ error handler
> related code can reside together. Lets see what RMK thinks
> on this.
>
There's an existing one for highbank (drivers/edac/highbank_l2_edac.c)
and there was a patch set for the pl310 as well[1]. I don't think we
want any architecture specific code for this, just use the EDAC framework.
[1] https://lkml.org/lkml/2014/3/2/87
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd@codeaurora.org>
To: santosh shilimkar <santosh.shilimkar@oracle.com>,
Vitaly Andrianov <vitalya@ti.com>,
ssantosh@kernel.org, linux@arm.linux.org.uk,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling
Date: Thu, 25 Jun 2015 14:35:51 -0700 [thread overview]
Message-ID: <558C7437.2090306@codeaurora.org> (raw)
In-Reply-To: <558C72EB.8010502@oracle.com>
On 06/25/2015 02:30 PM, santosh shilimkar wrote:
> On 6/25/2015 2:02 PM, Stephen Boyd wrote:
>> On 06/25/2015 08:04 AM, santosh shilimkar wrote:
>>> On 6/25/2015 7:31 AM, Vitaly Andrianov wrote:
>>>> This patch series adds support for arm L1/L2 ecc and ddr3 ecc error
>>>> handling
>>>> for Keystone devices
>>>>
>>>> Change Log
>>>>
>>>> v2:
>>>> - removing unused and sorting headers of keystone.c are moved to a
>>>> separate
>>>> patch.
>>>> - l1l2 ecc and ddr3 ecc error handling are split it to separate
>>>> patches
>>>> - removed unused headers from keystone_ecc.c
>>>> - platsmp.c removed from the patch.
>>>> - return IRQ_HANDLED for 1 bit error in l1l2 ecc handler
>>>> - checked and handled existing echttps://lwn.net/Articles/593336/c
>>>> error before enabling ddr3 interrupt
>>>> - 1 bit ddr3 interrupt is disabled, because it is handled by hardware
>>>> and
>>>> there is no reason to handle it by software
>>>>
>>> This version looks good to me. As already commented, I would have liked
>>> the patch 2/3(L2 ECC) code in ARM generic code so will give some more
>>> time for others to come back. Otherwise I will queue this up for next
>>> window.
>>
>> Why not make this into an edac driver? I sent out an L1/L2 error
>> detection edac driver for Krait processors a year ago, but it stalled
>> due to some DT binding stuff[1]. This looks fairly similar.
>>
> Indeed the error detection part is very similar(expected as well
> considering the same processor L2 regs). I am not sure we need
> full driver only for that but at least the IRQ error handler
> related code can reside together. Lets see what RMK thinks
> on this.
>
There's an existing one for highbank (drivers/edac/highbank_l2_edac.c)
and there was a patch set for the pl310 as well[1]. I don't think we
want any architecture specific code for this, just use the EDAC framework.
[1] https://lkml.org/lkml/2014/3/2/87
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-06-25 21:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-25 14:31 [PATCH v2 0/3] ARM: keystone: add ecc error interrupt handling Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` [PATCH v2 1/3] ARM: keystone: clean and sort keystone.c headers Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` [PATCH v2 2/3] ARM: keystone: ecc: add ARM L1/L2 ecc interrupt handling Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` [PATCH v2 3/3] ARM: keystone: ecc: add DDR3 " Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 14:31 ` Vitaly Andrianov
2015-06-25 15:04 ` [PATCH v2 0/3] ARM: keystone: add ecc error " santosh shilimkar
2015-06-25 15:04 ` santosh shilimkar
2015-06-25 21:02 ` Stephen Boyd
2015-06-25 21:02 ` Stephen Boyd
2015-06-25 21:02 ` Stephen Boyd
2015-06-25 21:30 ` santosh shilimkar
2015-06-25 21:30 ` santosh shilimkar
2015-06-25 21:30 ` santosh shilimkar
2015-06-25 21:35 ` Stephen Boyd [this message]
2015-06-25 21:35 ` Stephen Boyd
2015-06-25 21:35 ` Stephen Boyd
2015-06-26 12:20 ` Vitaly Andrianov
2015-06-26 12:20 ` Vitaly Andrianov
2015-06-26 12:20 ` Vitaly Andrianov
2015-07-02 0:14 ` Stephen Boyd
2015-07-02 0:14 ` Stephen Boyd
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