All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Andreas Färber" <afaerber@suse.de>
To: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>, qemu-devel@nongnu.org
Cc: chen.fan.fnst@cn.fujitsu.com, Paolo Bonzini <pbonzini@redhat.com>,
	izumi.taku@jp.fujitsu.com, ehabkost@redhat.com,
	imammedo@redhat.com
Subject: Re: [Qemu-devel] [RESEND PATCH v8 2/4] hw: add a wrapper for registering reset handler
Date: Tue, 30 Jun 2015 12:24:22 +0200	[thread overview]
Message-ID: <55926E56.7060505@suse.de> (raw)
In-Reply-To: <559237D6.8000602@cn.fujitsu.com>

Am 30.06.2015 um 08:31 schrieb Zhu Guihua:
> On 06/26/2015 01:28 AM, Andreas Färber wrote:
>> Am 25.06.2015 um 19:00 schrieb Paolo Bonzini:
>>> On 25/06/2015 04:17, Zhu Guihua wrote:
>>>> Add a wrapper to specify reset order when registering reset handler,
>>>> instead of non-obvious initiazation code ordering.
>>>>
>>>> Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
>>> I'm sorry, this is not really acceptable.  The initialization code
>>> ordering is good because it should be okay to run reset handlers in the
>>> same order as code is run.  If there are dependencies between reset
>>> handlers, a random integer is not a maintainable way to maintain them.
>>>
>>> Instead, you should have a single reset handler that calls the reset
>>> handlers in the right order; for example a qdev bus such as icc_bus
>>> always resets children before parents.
>>>
>>> Are you sure that you want to remove the icc_bus?... What are you
>>> gaining exactly by doing so?
>> >From my view we would be gaining by making the APIC an integral part
>> (child<>) of the CPU in a follow-up step (there's a TODO to make things
>> link<>s).
>>
>> But either way the CPU's existing reset handler should be able to handle
>> CPU/APIC interdependencies just fine, somehow. Which is what Eduardo
>> said on v6 and v7. (Another alternative he raised was a machine init
>> notifier, but I see no code for that after its mention on v7?)
> 
> According to Eduardo's suggestions on v7, the simpler way is to add a
> ordering parameter
> to qemu_register_reset(), so that we can ensure the order of apic reset
> handler(apic reset
> must be after the other devices' reset on x86).

That is a very general statement. Surely the APIC does not need to be
reset after *all* other devices but after some particular device(s).
Which one is that if not the X86CPU?

> This way will  not influence the initialization code ordering expect
> apic reset.

And exactly that's the criticism: You're introducing a generic mechanism
to address a single very specific problem.

sPAPR already has the MachineClass::reset() callback to order CPU vs.
device reset. So if you want a new mechanism you'll need to explain in
detail why that is needed and not just say that it solves your issue.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB
21284 (AG Nürnberg)

  parent reply	other threads:[~2015-06-30 10:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-25  2:17 [Qemu-devel] [RESEND PATCH v8 0/4] remove icc bus/bridge Zhu Guihua
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 1/4] apic: map APIC's MMIO region at each CPU's address space Zhu Guihua
2015-06-25 16:00   ` Andreas Färber
2015-06-25 16:02     ` Paolo Bonzini
2015-06-25 16:10       ` Andreas Färber
2015-06-25 17:02         ` Paolo Bonzini
2015-06-25 17:08           ` Andreas Färber
2015-06-25 17:27             ` Paolo Bonzini
2015-06-25 17:32               ` Peter Maydell
2015-06-25 17:39                 ` Paolo Bonzini
2015-06-26  9:01               ` Igor Mammedov
2015-06-26  9:05                 ` Paolo Bonzini
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 2/4] hw: add a wrapper for registering reset handler Zhu Guihua
2015-06-25 16:57   ` Andreas Färber
2015-06-25 17:00   ` Paolo Bonzini
2015-06-25 17:28     ` Andreas Färber
2015-06-26  9:19       ` Igor Mammedov
2015-06-26 10:05         ` Paolo Bonzini
2015-06-30  6:31       ` Zhu Guihua
2015-06-30  9:21         ` Igor Mammedov
2015-06-30 10:50           ` Zhu Guihua
2015-06-30 10:55             ` Peter Maydell
2015-06-30 18:38               ` Eduardo Habkost
2015-06-30 10:24         ` Andreas Färber [this message]
2015-06-30 18:30           ` Eduardo Habkost
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 3/4] cpu/apic: drop icc bus/bridge Zhu Guihua
2015-06-25 16:44   ` Andreas Färber
2015-06-25  2:17 ` [Qemu-devel] [RESEND PATCH v8 4/4] icc_bus: drop the unused files Zhu Guihua

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=55926E56.7060505@suse.de \
    --to=afaerber@suse.de \
    --cc=chen.fan.fnst@cn.fujitsu.com \
    --cc=ehabkost@redhat.com \
    --cc=imammedo@redhat.com \
    --cc=izumi.taku@jp.fujitsu.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=zhugh.fnst@cn.fujitsu.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.