[PATCH 1/8 v3] mtd: spi-nor: fsl-quadspi: Fix qspi irq handler complete exception

[PATCH 1/8 v3] mtd: spi-nor: fsl-quadspi: Fix qspi irq handler complete exception

[Haikun Wang]

In case of interrupt arrive immediately after requesting irq,
kernel will panic due to uninitialized variable.

Fix below exception on LS1021AQDS:
Unable to handle kernel NULL pointer dereference at virtual address
00000000
pgd = 80003000
[00000000] *pgd=80000080004003, *pmd=00000000
Internal error: Oops: 206 [#1] SMP THUMB2
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.0-rc5+ #2
Hardware name: Freescale LS1021A
task: 80526f30 ti: 80522000 task.ti: 80522000
PC is at __wake_up_common+0x14/0x46
LR is at __wake_up_locked+0xb/0x10
pc : [<800388ae>]    lr : [<800388eb>]    psr: 400001b3
sp : 80523e78  ip : 00000008  fp : 00000001
r10: 00000000  r9 : 00000003  r8 : ee008000
r7 : 00000001  r6 : 80000193  r5 : 00000000  r4 : ee0c0bd0
r3 : 00000000  r2 : 00000001  r1 : 00000003  r0 : fffffff4
Flags: nZcv  IRQs off  FIQs on  Mode SVC_32  ISA Thumb  Segment kernel
Control: 70c5387d  Table: 80003000  DAC: fddff9d7
Process swapper/0 (pid: 0, stack limit = 0x80522210)
Stack: (0x80523e78 to 0x80524000)
3e60:                                                       00000000
ee0c0bcc
3e80: ee0c0bc8 80000193 00000000 ee0cb480 805532ff 800388eb 00000000
00000003
3ea0: 00000001 80038d7f ee0c0010 08010001 00000000 80211587 80211553
cf81af00
3ec0: 00000017 8003e199 ee0cb480 cf81af00 ee0cb480 80532ec0 6e2b4000
00000000
3ee0: ee008000 00000001 803326d0 8003e265 00000000 ee0cb480 80532ec0
8003ff6b
3f00: 8003ff09 00000017 8051ebc4 8003dc77 00000000 8003de47 80523f48
f0002000
3f20: 80523f48 805247d4 80523f7c 8051d384 8051fca0 8000924b 8000db28
40000133
3f40: ffffffff 8032df1b 00000001 00000000 00000000 80017be1 80522000
00000000
3f60: 00000000 80523f98 8051d384 8051fca0 803326d0 00000001 00000008
80523f90
3f80: 8000db27 8000db28 40000133 ffffffff 00000000 80038fd7 00000001
00000000
3fa0: 00000002 80556000 00000000 804eb933 ffffffff ffffffff 804eb545
00000000
3fc0: ffffffff 00000000 00000000 80512590 00000000 80556294 80524460
8051258c
3fe0: 80528050 80003010 410fc075 00000000 00000000 8000808f 00000000
	00000000
[<800388ae>] (__wake_up_common) from [<800388eb>]
	(__wake_up_locked+0xb/0x10)
[<800388eb>] (__wake_up_locked) from [<80038d7f>] (complete+0x1f/0x2a)
[<80038d7f>] (complete) from [<80211587>] (fsl_qspi_irq_handler+0x35/0x38)
[<80211587>] (fsl_qspi_irq_handler) from [<8003e199>]
	(handle_irq_event_percpu+0x1b/0xb6)
[<8003e199>] (handle_irq_event_percpu) from [<8003e265>]
	(handle_irq_event+0x31/0x48)
[<8003e265>] (handle_irq_event) from [<8003ff6b>]
	(handle_fasteoi_irq+0x63/0xb8)
[<8003ff6b>] (handle_fasteoi_irq) from [<8003dc77>]
	(generic_handle_irq+0x13/0x1c)
[<8003dc77>] (generic_handle_irq) from [<8003de47>]
	(__handle_domain_irq+0x53/0x74)
[<8003de47>] (__handle_domain_irq) from [<8000924b>]
	(gic_handle_irq+0x27/0x40)
[<8000924b>] (gic_handle_irq) from [<8032df1b>] (__irq_svc+0x3b/0x5c)
Exception stack(0x80523f48 to 0x80523f90)
3f40:                   00000001 00000000 00000000 80017be1 80522000
00000000
3f60: 00000000 80523f98 8051d384 8051fca0 803326d0 00000001 00000008
80523f90
3f80: 8000db27 8000db28 40000133 ffffffff
[<8032df1b>] (__irq_svc) from [<8000db28>] (arch_cpu_idle+0x14/0x20)
[<8000db28>] (arch_cpu_idle) from [<80038fd7>]
	(cpu_startup_entry+0x187/0x1c4)
[<80038fd7>] (cpu_startup_entry) from [<804eb933>]
	(start_kernel+0x27b/0x2e4)
[<804eb933>] (start_kernel) from [<8000808f>] (0x8000808f)
Code: 4617 469a f1a5 000c (682d) 3d0c
---[ end trace 420f2b58e4270f57 ]---
Kernel panic - not syncing: Fatal exception in interrupt
CPU1: stopping
CPU: 1 PID: 0 Comm: swapper/1 Tainted: G      D         4.1.0-rc5+ #2
Hardware name: Freescale LS1021A
[<80011937>] (unwind_backtrace) from [<8000f4e7>] (show_stack+0xb/0xc)
[<8000f4e7>] (show_stack) from [<8032ad55>] (dump_stack+0x51/0x64)
[<8032ad55>] (dump_stack) from [<80010ff9>] (handle_IPI+0x7d/0xf8)
[<80010ff9>] (handle_IPI) from [<8000925b>] (gic_handle_irq+0x37/0x40)
[<8000925b>] (gic_handle_irq) from [<8032df1b>] (__irq_svc+0x3b/0x5c)
Exception stack(0xee079f90 to 0xee079fd8)
9f80:                                     00000001 00000000 00000000
80017be1
9fa0: ee078000 00000000 00000000 ee079fe0 8051d384 8051fca0 803326d0
00000001
9fc0: 00000008 ee079fd8 8000db27 8000db28 40000133 ffffffff
[<8032df1b>] (__irq_svc) from [<8000db28>] (arch_cpu_idle+0x14/0x20)
[<8000db28>] (arch_cpu_idle) from [<80038fd7>]
	(cpu_startup_entry+0x187/0x1c4)
[<80038fd7>] (cpu_startup_entry) from [<80009311>] (__enable_mmu+0x1/0x10)
---[ end Kernel panic - not syncing: Fatal exception in interrupt

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v3:
- Rebase

Changes in v2:
- Remove 'init_completion'

 drivers/mtd/spi-nor/fsl-quadspi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 4fe13dd..7e74567 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -637,6 +637,10 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
 			base + QUADSPI_MCR);
 
+	/* clear flag register before enable the interrupt */
+	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
+
 	/* enable the interrupt */
 	writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
 
-- 
2.1.0.27.g96db324

[PATCH 2/8 v4] mtd: spi-nor: fsl-quadspi: Enable LS1021 support

[Haikun Wang]

Add LS1021 QSPI chip special information

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v4:
- Rebase with l2-mtd.git

Changes in v3:
- Rebase with l2-mtd.git

Changes in v2:
- Fix compile issue
- Add ahb_buf_size initialization
 drivers/mtd/spi-nor/fsl-quadspi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 7e74567..685ac97 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -195,6 +195,7 @@
 enum fsl_qspi_devtype {
 	FSL_QUADSPI_VYBRID,
 	FSL_QUADSPI_IMX6SX,
+	FSL_QUADSPI_LS1,
 };
 
 struct fsl_qspi_devtype_data {
@@ -218,6 +219,13 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
 	.ahb_buf_size = 1024
 };
 
+static struct fsl_qspi_devtype_data ls1_data = {
+	.devtype = FSL_QUADSPI_LS1,
+	.rxfifo = 128,
+	.txfifo = 64,
+	.ahb_buf_size = 1024
+};
+
 #define FSL_QSPI_MAX_CHIP	4
 struct fsl_qspi {
 	struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
@@ -671,6 +679,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
 static const struct of_device_id fsl_qspi_dt_ids[] = {
 	{ .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
 	{ .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
+	{ .compatible = "fsl,ls1-qspi", .data = (void *)&ls1_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
-- 
2.1.0.27.g96db324

[PATCH 3/8 v2] mtd: spi-nor: fsl-quadspi: Add a variable in struct fsl_qspi_devtype_data to specify platform specail feature

[Haikun Wang]

Add a variable "driver_data" in struct fsl_qspi_devtype_data.
Add a flag to indicate that driver need swap endian when access registers
using the new variable.
Enable this flag for LS1021A.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v2:
- Update commit messgae

 drivers/mtd/spi-nor/fsl-quadspi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 685ac97..ac2a607 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -192,6 +192,9 @@
 #define SEQID_EN4B		10
 #define SEQID_BRWR		11
 
+/* Controller needs swap endian when access registers */
+#define QUADSPI_QUIRK_REGMAP_BE    (1 << 5)
+
 enum fsl_qspi_devtype {
 	FSL_QUADSPI_VYBRID,
 	FSL_QUADSPI_IMX6SX,
@@ -203,6 +206,7 @@ struct fsl_qspi_devtype_data {
 	int rxfifo;
 	int txfifo;
 	int ahb_buf_size;
+	int driver_data;
 };
 
 static struct fsl_qspi_devtype_data vybrid_data = {
@@ -223,7 +227,8 @@ static struct fsl_qspi_devtype_data ls1_data = {
 	.devtype = FSL_QUADSPI_LS1,
 	.rxfifo = 128,
 	.txfifo = 64,
-	.ahb_buf_size = 1024
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_REGMAP_BE
 };
 
 #define FSL_QSPI_MAX_CHIP	4
-- 
2.1.0.27.g96db324

[PATCH 4/8 v2] mtd: spi-nor: fsl-quadspi: Wrap writel/readl with qspi_writel/qspi_readl

[Haikun Wang]

Wrap writel/readl with qspi_writel/qspi_readl in order to add platform
special operations, such as endianness swap.
This patch just wrap the functions, doesn't add any operation.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v2:
-Rebase

 drivers/mtd/spi-nor/fsl-quadspi.c | 132 ++++++++++++++++++++++----------------
 1 file changed, 75 insertions(+), 57 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index ac2a607..ec23a74 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -260,6 +260,16 @@ static inline int is_imx6sx_qspi(struct fsl_qspi *q)
 	return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
 }
 
+static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
+{
+	writel(val, addr);
+}
+
+static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
+{
+	return	readl(addr);
+}
+
 /*
  * An IC bug makes us to re-arrange the 32-bit data.
  * The following chips, such as IMX6SLX, have fixed this bug.
@@ -271,14 +281,14 @@ static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
 
 static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
 {
-	writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-	writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
 {
-	writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
-	writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
+	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
+	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
 }
 
 static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
@@ -287,8 +297,8 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
 	u32 reg;
 
 	/* clear interrupt */
-	reg = readl(q->iobase + QUADSPI_FR);
-	writel(reg, q->iobase + QUADSPI_FR);
+	reg = qspi_readl(q, q->iobase + QUADSPI_FR);
+	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
 	if (reg & QUADSPI_FR_TFF_MASK)
 		complete(&q->c);
@@ -309,7 +319,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 
 	/* Clear all the LUT table */
 	for (i = 0; i < QUADSPI_LUT_NUM; i++)
-		writel(0, base + QUADSPI_LUT_BASE + i * 4);
+		qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
 
 	/* Quad Read */
 	lut_base = SEQID_QUAD_READ * 4;
@@ -325,14 +335,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 		dummy = 8;
 	}
 
-	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
 			base + QUADSPI_LUT(lut_base));
-	writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
+	qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
 			base + QUADSPI_LUT(lut_base + 1));
 
 	/* Write enable */
 	lut_base = SEQID_WREN * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
+		    base + QUADSPI_LUT(lut_base));
 
 	/* Page Program */
 	lut_base = SEQID_PP * 4;
@@ -346,13 +357,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 		addrlen = ADDR32BIT;
 	}
 
-	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
 			base + QUADSPI_LUT(lut_base));
-	writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
+	qspi_writel(q, LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
 
 	/* Read Status */
 	lut_base = SEQID_RDSR * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
 			base + QUADSPI_LUT(lut_base));
 
 	/* Erase a sector */
@@ -367,40 +378,43 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 		addrlen = ADDR32BIT;
 	}
 
-	writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
+	qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
 			base + QUADSPI_LUT(lut_base));
 
 	/* Erase the whole chip */
 	lut_base = SEQID_CHIP_ERASE * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
 			base + QUADSPI_LUT(lut_base));
 
 	/* READ ID */
 	lut_base = SEQID_RDID * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
 			base + QUADSPI_LUT(lut_base));
 
 	/* Write Register */
 	lut_base = SEQID_WRSR * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
 			base + QUADSPI_LUT(lut_base));
 
 	/* Read Configuration Register */
 	lut_base = SEQID_RDCR * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
 			base + QUADSPI_LUT(lut_base));
 
 	/* Write disable */
 	lut_base = SEQID_WRDI * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
+		    base + QUADSPI_LUT(lut_base));
 
 	/* Enter 4 Byte Mode (Micron) */
 	lut_base = SEQID_EN4B * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
+		    base + QUADSPI_LUT(lut_base));
 
 	/* Enter 4 Byte Mode (Spansion) */
 	lut_base = SEQID_BRWR * 4;
-	writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
+	qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
+		    base + QUADSPI_LUT(lut_base));
 
 	fsl_qspi_lock_lut(q);
 }
@@ -453,15 +467,16 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
 			q->chip_base_addr, addr, len, cmd);
 
 	/* save the reg */
-	reg = readl(base + QUADSPI_MCR);
+	reg = qspi_readl(q, base + QUADSPI_MCR);
 
-	writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
-	writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
+	qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
+		    base + QUADSPI_SFAR);
+	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
 			base + QUADSPI_RBCT);
-	writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
+	qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
 
 	do {
-		reg2 = readl(base + QUADSPI_SR);
+		reg2 = qspi_readl(q, base + QUADSPI_SR);
 		if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
 			udelay(1);
 			dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
@@ -472,21 +487,22 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
 
 	/* trigger the LUT now */
 	seqid = fsl_qspi_get_seqid(q, cmd);
-	writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
+	qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
+		    base + QUADSPI_IPCR);
 
 	/* Wait for the interrupt. */
 	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000))) {
 		dev_err(q->dev,
 			"cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
-			cmd, addr, readl(base + QUADSPI_FR),
-			readl(base + QUADSPI_SR));
+			cmd, addr, qspi_readl(q, base + QUADSPI_FR),
+			qspi_readl(q, base + QUADSPI_SR));
 		err = -ETIMEDOUT;
 	} else {
 		err = 0;
 	}
 
 	/* restore the MCR */
-	writel(reg, base + QUADSPI_MCR);
+	qspi_writel(q, reg, base + QUADSPI_MCR);
 
 	return err;
 }
@@ -498,7 +514,7 @@ static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
 	int i = 0;
 
 	while (len > 0) {
-		tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
+		tmp = qspi_readl(q, q->iobase + QUADSPI_RBDR + i * 4);
 		tmp = fsl_qspi_endian_xchg(q, tmp);
 		dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
 				q->chip_base_addr, tmp);
@@ -526,9 +542,9 @@ static inline void fsl_qspi_invalid(struct fsl_qspi *q)
 {
 	u32 reg;
 
-	reg = readl(q->iobase + QUADSPI_MCR);
+	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
 	reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
-	writel(reg, q->iobase + QUADSPI_MCR);
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 
 	/*
 	 * The minimum delay : 1 AHB + 2 SFCK clocks.
@@ -537,7 +553,7 @@ static inline void fsl_qspi_invalid(struct fsl_qspi *q)
 	udelay(1);
 
 	reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
-	writel(reg, q->iobase + QUADSPI_MCR);
+	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
 }
 
 static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
@@ -551,13 +567,13 @@ static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
 		q->chip_base_addr, to, count);
 
 	/* clear the TX FIFO. */
-	tmp = readl(q->iobase + QUADSPI_MCR);
-	writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
+	tmp = qspi_readl(q, q->iobase + QUADSPI_MCR);
+	qspi_writel(q, tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
 
 	/* fill the TX data to the FIFO */
 	for (j = 0, i = ((count + 3) / 4); j < i; j++) {
 		tmp = fsl_qspi_endian_xchg(q, *txbuf);
-		writel(tmp, q->iobase + QUADSPI_TBDR);
+		qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
 		txbuf++;
 	}
 
@@ -575,10 +591,10 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
 	int nor_size = q->nor_size;
 	void __iomem *base = q->iobase;
 
-	writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
-	writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
-	writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
-	writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
+	qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
+	qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
+	qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
+	qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
 }
 
 /*
@@ -600,24 +616,26 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
 	int seqid;
 
 	/* AHB configuration for access buffer 0/1/2 .*/
-	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
-	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
-	writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
+	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
+	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
+	qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
 	/*
 	 * Set ADATSZ with the maximum AHB buffer size to improve the
 	 * read performance.
 	 */
-	writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
-			<< QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
+	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+			((q->devtype_data->ahb_buf_size / 8)
+			<< QUADSPI_BUF3CR_ADATSZ_SHIFT),
+			base + QUADSPI_BUF3CR);
 
 	/* We only use the buffer3 */
-	writel(0, base + QUADSPI_BUF0IND);
-	writel(0, base + QUADSPI_BUF1IND);
-	writel(0, base + QUADSPI_BUF2IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF0IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF1IND);
+	qspi_writel(q, 0, base + QUADSPI_BUF2IND);
 
 	/* Set the default lut sequence for AHB Read. */
 	seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
-	writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
+	qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
 		q->iobase + QUADSPI_BFGENCR);
 }
 
@@ -637,17 +655,17 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	fsl_qspi_init_lut(q);
 
 	/* Disable the module */
-	writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
+	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
 			base + QUADSPI_MCR);
 
-	reg = readl(base + QUADSPI_SMPR);
-	writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
+	reg = qspi_readl(q, base + QUADSPI_SMPR);
+	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
 			| QUADSPI_SMPR_FSPHS_MASK
 			| QUADSPI_SMPR_HSENA_MASK
 			| QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
 
 	/* Enable the module */
-	writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
+	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
 			base + QUADSPI_MCR);
 
 	/* clear flag register before enable the interrupt */
@@ -655,7 +673,7 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q)
 	qspi_writel(q, reg, q->iobase + QUADSPI_FR);
 
 	/* enable the interrupt */
-	writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
+	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
 
 	return 0;
 }
@@ -1001,8 +1019,8 @@ static int fsl_qspi_remove(struct platform_device *pdev)
 	}
 
 	/* disable the hardware */
-	writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
-	writel(0x0, q->iobase + QUADSPI_RSER);
+	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
+	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);
 
 	mutex_destroy(&q->lock);
 	clk_unprepare(q->clk);
-- 
2.1.0.27.g96db324

[PATCH 5/8 v5] mtd: spi-nor: fsl-quadspi: Enable support big endian registers

[Haikun Wang]

QSPI registers are big endian on LS1021A.
This patch check endianness before accessing register and
swap the data if QSPI register is big endian.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v5:
- Rebase with l2-mtd.git

Changes in v4:
- Split into three patches:
 1. mtd: spi-nor: fsl-quadspi: Add a variable in struct fsl_qspi_devtype_data to specify platform specail feature
 2. mtd: spi-nor: fsl-quadspi: Wrap writel/readl with qspi_writel/qspi_readl
 3. mtd: spi-nor: fsl-quadspi: Enable support big endian registers

Changes in v3:
- Rebase with l2-mtd.git

Changes in v2:
- Fix compile issue

 drivers/mtd/spi-nor/fsl-quadspi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index ec23a74..283e157 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -262,12 +262,14 @@ static inline int is_imx6sx_qspi(struct fsl_qspi *q)
 
 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
 {
-	writel(val, addr);
+	q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		writel(cpu_to_be32(val), addr) : writel(val, addr);
 }
 
 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
 {
-	return	readl(addr);
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		cpu_to_be32(readl(addr)) : readl(addr);
 }
 
 /*
-- 
2.1.0.27.g96db324

[PATCH 6/8 v2] mtd: spi-nor: fsl-quadspi: Add QSPI dts node for LS1021A

[Haikun Wang]

Add QSPI dts node for LS1021AQDS and LS1021ATWR boards.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v2:
- Rebase

 arch/arm/boot/dts/ls1021a-qds.dts | 16 ++++++++++++++++
 arch/arm/boot/dts/ls1021a-twr.dts | 13 +++++++++++++
 arch/arm/boot/dts/ls1021a.dtsi    | 15 +++++++++++++++
 3 files changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..15bf07f 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -238,3 +238,19 @@
 &uart1 {
 	status = "okay";
 };
+
+&qspi {
+	num-cs = <2>;
+	bus-num = <0>;
+	fsl,spi-num-chipselects = <2>;
+	fsl,spi-flash-chipselects = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		compatible = "spansion,s25fl128s";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..b72f6ee 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -125,3 +125,16 @@
 &uart1 {
 	status = "okay";
 };
+
+&qspi {
+	num-cs = <2>;
+	status = "okay";
+
+	qflash0: n25q128a13@0 {
+		compatible = "micron,n25q128a13";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..09f1a33 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -127,6 +127,21 @@
 			big-endian;
 		};
 
+		qspi: quadspi@1550000 {
+			compatible = "fsl,ls1-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "qspi_en", "qspi";
+			clocks = <&platform_clk 1>, <&platform_clk 1>;
+			big-endian;
+			amba-base = <0x40000000>;
+			status = "disabled";
+		};
+
 		esdhc: esdhc@1560000 {
 			compatible = "fsl,esdhc";
 			reg = <0x0 0x1560000 0x0 0x10000>;
-- 
2.1.0.27.g96db324

[PATCH 7/8 v2] mtd: spi-nor: fsl-quadspi: Update bindings documentation

[Haikun Wang]

Add QuadSPI slave properties description.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v2:
- Rebase

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 4461dc7..6627893 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -1,6 +1,6 @@
 * Freescale Quad Serial Peripheral Interface(QuadSPI)
 
-Required properties:
+QuadSPI master required properties:
   - compatible : Should be "fsl,vf610-qspi" or "fsl,imx6sx-qspi"
   - reg : the first contains the register location and length,
           the second contains the memory mapping address and length
@@ -18,6 +18,13 @@ Optional properties:
 			      bus, you should enable this property.
 			      (Please check the board's schematic.)
 
+QuadSPI slave required properties:
+  - compatible : Should be the manufacturer and the name of the chip,
+		 like "spansion,s25fl128s", "micron,n25q128a13"...
+		 See the "spi_nor_ids" table in drivers/mtd/spi-nor/spi-nor.c
+		 for the list of supported chips.
+  - spi-max-frequency : Maximum SPI clocking speed of device in Hz
+
 Example:
 
 qspi0: quadspi@40044000 {
-- 
2.1.0.27.g96db324

[PATCH 8/8 v2] mtd: spi-nor: fsl-quadspi: Add compatible string "fsl, ls1-qspi" in bindings documentation

[Haikun Wang]

Freescale LS1021A SOC also has QSPI controller and it has platform special
features than other platforms.
Add "fsl,ls1-qspi" in the valid compatible string list.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v2:
- Rebase

 Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
index 6627893..42c2954 100644
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
@@ -1,7 +1,7 @@
 * Freescale Quad Serial Peripheral Interface(QuadSPI)
 
 QuadSPI master required properties:
-  - compatible : Should be "fsl,vf610-qspi" or "fsl,imx6sx-qspi"
+  - compatible : Should be "fsl,vf610-qspi", "fsl,ls1-qspi" or "fsl,imx6sx-qspi"
   - reg : the first contains the register location and length,
           the second contains the memory mapping address and length
   - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
-- 
2.1.0.27.g96db324

Re: [PATCH 6/8 v2] mtd: spi-nor: fsl-quadspi: Add QSPI dts node for LS1021A

[Cory Tusar]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 07/07/2015 04:38 AM, Haikun Wang wrote:
> Add QSPI dts node for LS1021AQDS and LS1021ATWR boards.
> 
> Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
> ---
> Changes in v2:
> - Rebase
> 
>  arch/arm/boot/dts/ls1021a-qds.dts | 16 ++++++++++++++++
>  arch/arm/boot/dts/ls1021a-twr.dts | 13 +++++++++++++
>  arch/arm/boot/dts/ls1021a.dtsi    | 15 +++++++++++++++
>  3 files changed, 44 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..15bf07f 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -238,3 +238,19 @@
>  &uart1 {
>  	status = "okay";
>  };
> +
> +&qspi {
> +	num-cs = <2>;
> +	bus-num = <0>;
> +	fsl,spi-num-chipselects = <2>;
> +	fsl,spi-flash-chipselects = <0>;

I don't believe the above 4 properties are used by the fsl-quadspi
driver.

> +	status = "okay";
> +
> +	qflash0: s25fl128s@0 {
> +		compatible = "spansion,s25fl128s";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..b72f6ee 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -125,3 +125,16 @@
>  &uart1 {
>  	status = "okay";
>  };
> +
> +&qspi {
> +	num-cs = <2>;

I don't believe the above property is used by the fsl-quadspi driver.

> +	status = "okay";
> +
> +	qflash0: n25q128a13@0 {
> +		compatible = "micron,n25q128a13";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <20000000>;
> +		reg = <0>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..09f1a33 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -127,6 +127,21 @@
>  			big-endian;
>  		};
>  
> +		qspi: quadspi@1550000 {
> +			compatible = "fsl,ls1-qspi";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x1550000 0x0 0x10000>,
> +				<0x0 0x40000000 0x0 0x4000000>;
> +			reg-names = "QuadSPI", "QuadSPI-memory";
> +			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "qspi_en", "qspi";
> +			clocks = <&platform_clk 1>, <&platform_clk 1>;
> +			big-endian;
> +			amba-base = <0x40000000>;
> +			status = "disabled";
> +		};
> +
>  		esdhc: esdhc@1560000 {
>  			compatible = "fsl,esdhc";
>  			reg = <0x0 0x1560000 0x0 0x10000>;
> 


- -- 
Cory Tusar
Principal
PID 1 Solutions, Inc.


"There are two ways of constructing a software design.  One way is to
 make it so simple that there are obviously no deficiencies, and the
 other way is to make it so complicated that there are no obvious
 deficiencies."  --Sir Charles Anthony Richard Hoare

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