[U-Boot] [PATCH v2 0/4] lpc32xx: devkit3250 board update

[U-Boot] [PATCH v2 0/4] lpc32xx: devkit3250 board update

[Vladimir Zapolskiy]

This changeset improves support of Timll DevKit3250 board:
* added LPC32xx MAC and SMSC RMII phy support, this dependends on
  - http://patchwork.ozlabs.org/patch/489100/
  - http://patchwork.ozlabs.org/patch/489190/
  - http://patchwork.ozlabs.org/patch/491419/
  - http://patchwork.ozlabs.org/patch/491420/
* added GPIO, SPI, I2C support, works good, many thanks to Albert,
* added LPC32xx SLC NAND driver, testing of 50 MiB data raw reading
  shows 1 MiB/s speed, the same change has been sent to the mailing
  list separately, here it is duplicated as a build dependency:
  - http://patchwork.ozlabs.org/patch/495247/
  - http://patchwork.ozlabs.org/patch/495250/
* added an option to pass DTB to an operating system,
* changed serial console to commonly used as default UART5,
* boot delay is set to 1 for convenience,
* extended predefined environment variables and reserved space on NAND,
* added an option to build SPL image for the board, by default SPL
  downloads U-boot image from NAND (offset 0x40000, size 0x60000).

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver,
  see patch v2 2/4,
* added Tegra and TI maintainers to Cc list to review/ack a change 1/4
  in simple NAND SPL framework, which potentially (very unlikely)
  may cause a regression in NAND SPL on Tegra, TI OMAP or TI DaVinci
  platforms.

Previous version of the change and discussion can be found here:
  http://lists.denx.de/pipermail/u-boot/2015-July/219253.html

Albert, from commit logs I noticed that WORK92105 has SLC NAND chip,
but it is managed by MLC controller, if you have any plans to test
LPC32xx SLC NAND driver from the series, please *be aware* of
different OOB layouts, I found it is quite easy to screw up the chip,
if SLC and MLC are interchanged, so that only "nand scrub" helps.
FWIW this SLC NAND driver uses a default OOB layout, the same one
is found in Linux LPC32xx SLC NAND driver.

Vladimir Zapolskiy (4):
  spl: nand: simple: replace readb() with chip specific read_buf()
  nand: lpc32xx: add SLC NAND controller support
  lpc32xx: devkit3250: update of board configuration
  lpc32xx: devkit3250: add spl build support

 arch/arm/Kconfig                              |   1 +
 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 board/timll/devkit3250/Makefile               |   1 +
 board/timll/devkit3250/devkit3250.c           |  31 ++++-
 board/timll/devkit3250/devkit3250_spl.c       |  68 ++++++++++
 configs/devkit3250_defconfig                  |   4 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 drivers/mtd/nand/nand_spl_simple.c            |   7 +-
 include/configs/devkit3250.h                  | 145 ++++++++++++++++++++-
 12 files changed, 435 insertions(+), 8 deletions(-)
 create mode 100644 board/timll/devkit3250/devkit3250_spl.c
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

-- 
2.1.4

[U-Boot] [PATCH v2 1/4] spl: nand: simple: replace readb() with chip specific read_buf()

[Vladimir Zapolskiy]

Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
---
Changes from v1 to v2:
* no changes, added Tom and Tom to Cc list for review and/or regression
  testing on Tegra, TI OMAP and TI DaVinci platforms

Previous discussion can be found here:
  http://lists.denx.de/pipermail/u-boot/2015-July/219250.html

 drivers/mtd/nand/nand_spl_simple.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 700ca32..e69f662 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -115,6 +115,7 @@ static int nand_command(int block, int page, uint32_t offs,
 static int nand_is_bad_block(int block)
 {
 	struct nand_chip *this = mtd.priv;
+	u_char bb_data[2];
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);
@@ -123,10 +124,12 @@ static int nand_is_bad_block(int block)
 	 * Read one byte (or two if it's a 16 bit chip).
 	 */
 	if (this->options & NAND_BUSWIDTH_16) {
-		if (readw(this->IO_ADDR_R) != 0xffff)
+		this->read_buf(&mtd, bb_data, 2);
+		if (bb_data[0] != 0xff || bb_data[1] != 0xff)
 			return 1;
 	} else {
-		if (readb(this->IO_ADDR_R) != 0xff)
+		this->read_buf(&mtd, bb_data, 1);
+		if (bb_data[0] != 0xff)
 			return 1;
 	}
 
-- 
2.1.4

[U-Boot] [PATCH v2 1/4] spl: nand: simple: replace readb() with chip specific read_buf()

[Scott Wood]

On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> Some NAND controllers define custom functions to read data out,
> respect this in order to correctly support bad block handling in
> simple SPL NAND framework.
> 
> NAND controller specific read_buf() is used even to read 1 byte in
> case of connected 8-bit NAND device, it turns out that read_byte()
> may become outdated.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Tom Warren <twarren@nvidia.com>
> ---
> Changes from v1 to v2:
> * no changes, added Tom and Tom to Cc list for review and/or regression
>   testing on Tegra, TI OMAP and TI DaVinci platforms
> 
> Previous discussion can be found here:
>   http://lists.denx.de/pipermail/u-boot/2015-July/219250.html
> 
>  drivers/mtd/nand/nand_spl_simple.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Scott Wood <scottwood@freescale.com>

-Scott

[U-Boot] [U-Boot, v2, 1/4] spl: nand: simple: replace readb() with chip specific read_buf()

[Tom Rini]

On Sat, Jul 18, 2015 at 01:47:08AM +0300, Vladimir Zapolskiy wrote:

> Some NAND controllers define custom functions to read data out,
> respect this in order to correctly support bad block handling in
> simple SPL NAND framework.
> 
> NAND controller specific read_buf() is used even to read 1 byte in
> case of connected 8-bit NAND device, it turns out that read_byte()
> may become outdated.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: Tom Warren <twarren@nvidia.com>
> Acked-by: Scott Wood <scottwood@freescale.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
  - removed unnecessary uint32_t casts in write_buf()/write_byte(),
  - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
    and generally not needed for custom defined PIO interfaces in
    U-boot (with exception of simple NAND SPL, addressed by 1/4),
  - removed leftover declarations of HW ECC related bit fields,
    this should be added along with HW ECC support,
  - improved description of a reason why software ECC is selected,
    if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
  http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
  http://lists.denx.de/pipermail/u-boot/2015-July/219254.html

 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 5a453e3..b0287be 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 9449869..010211a 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index c3d890d..0845f83 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 347ea62..e2dc99a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
new file mode 100644
index 0000000..bc2fb8e
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -0,0 +1,176 @@
+/*
+ * LPC32xx SLC NAND flash controller driver
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+
+struct lpc32xx_nand_slc_registers {
+	u32 data;
+	u32 addr;
+	u32 cmd;
+	u32 stop;
+	u32 ctrl;
+	u32 cfg;
+	u32 stat;
+	u32 int_stat;
+	u32 ien;
+	u32 isr;
+	u32 icr;
+	u32 tac;
+	u32 tc;
+	u32 ecc;
+	u32 dma_data;
+};
+
+/* CFG register */
+#define CFG_CE_LOW		(1 << 5)
+
+/* CTRL register */
+#define CTRL_SW_RESET		(1 << 2)
+
+/* STAT register */
+#define STAT_NAND_READY		(1 << 0)
+
+/* INT_STAT register */
+#define INT_STAT_TC		(1 << 1)
+#define INT_STAT_RDY		(1 << 0)
+
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n)		(max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n)		(max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_registers __iomem *lpc32xx_nand_slc_registers
+	= (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;
+
+static void lpc32xx_nand_init(void)
+{
+	uint32_t hclk = get_hclk_clk_rate();
+
+	/* Reset SLC NAND controller */
+	writel(CTRL_SW_RESET, &lpc32xx_nand_slc_registers->ctrl);
+
+	/* 8-bit bus, no DMA, no ECC, ordinary CE signal */
+	writel(0, &lpc32xx_nand_slc_registers->cfg);
+
+	/* Interrupts disabled and cleared */
+	writel(0, &lpc32xx_nand_slc_registers->ien);
+	writel(INT_STAT_TC | INT_STAT_RDY,
+	       &lpc32xx_nand_slc_registers->icr);
+
+	/* Configure NAND flash timings */
+	writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
+	       TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
+	       TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
+	       TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
+	       TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
+	       TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
+	       TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
+	       TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
+	       &lpc32xx_nand_slc_registers->tac);
+}
+
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+				  int cmd, unsigned int ctrl)
+{
+	debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+	if (ctrl & NAND_NCE)
+		setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+	else
+		clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
+	else /* if (ctrl & NAND_ALE) */
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
+}
+
+static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
+{
+	return readl(&lpc32xx_nand_slc_registers->stat) & STAT_NAND_READY;
+}
+
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		*buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+	return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		writel(*buf++, &lpc32xx_nand_slc_registers->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+	writel(byte, &lpc32xx_nand_slc_registers->data);
+}
+
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+	lpc32xx_chip->cmd_ctrl	= lpc32xx_nand_cmd_ctrl;
+	lpc32xx_chip->dev_ready	= lpc32xx_nand_dev_ready;
+
+	/*
+	 * Hardware ECC calculation is not supported by the driver,
+	 * because it requires DMA support, see LPC32x0 User Manual,
+	 * note after SLC_ECC register description (UM10326, p.198)
+	 */
+	lpc32xx_chip->ecc.mode	= NAND_ECC_SOFT;
+
+	/*
+	 * The implementation of these functions is quite common, but
+	 * they MUST be defined, because access to data register
+	 * is strictly 32-bit aligned.
+	 */
+	lpc32xx_chip->read_buf	= lpc32xx_read_buf;
+	lpc32xx_chip->read_byte	= lpc32xx_read_byte;
+	lpc32xx_chip->write_buf	= lpc32xx_write_buf;
+	lpc32xx_chip->write_byte	= lpc32xx_write_byte;
+
+	/*
+	 * Use default ECC layout, but these values are predefined
+	 * for both small and large page NAND flash devices.
+	 */
+	lpc32xx_chip->ecc.size	= 256;
+	lpc32xx_chip->ecc.bytes	= 3;
+	lpc32xx_chip->ecc.strength	= 1;
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+	lpc32xx_chip->bbt_options	|= NAND_BBT_USE_FLASH;
+#endif
+
+	/* Initialize NAND interface */
+	lpc32xx_nand_init();
+
+	return 0;
+}
-- 
2.1.4

[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Scott Wood]

On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> +/* TAC register bits, be aware of overflows */
> +#define TAC_W_RDY(n)         (max_t(uint32_t, (n), 0xF) << 28)
> +#define TAC_W_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 24)
> +#define TAC_W_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 20)
> +#define TAC_W_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 16)
> +#define TAC_R_RDY(n)         (max_t(uint32_t, (n), 0xF) << 12)
> +#define TAC_R_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 8)
> +#define TAC_R_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 4)
> +#define TAC_R_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 0)
> +
> +static struct lpc32xx_nand_slc_registers __iomem 
> *lpc32xx_nand_slc_registers
> +     = (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;

s/registers/regs/ might help the formatting here...

> +static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
> +                               int cmd, unsigned int ctrl)
> +{
> +     debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
> +
> +     if (ctrl & NAND_NCE)
> +             setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
> +     else
> +             clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
> +
> +     if (cmd == NAND_CMD_NONE)
> +             return;
> +
> +     if (ctrl & NAND_CLE)
> +             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
> +     else /* if (ctrl & NAND_ALE) */
> +             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
> +}

Why is "if (ctrl & NAND_ALE())" commented out?  I think it'd be better if 
wrong uses of this function didn't silently cause address cycles (which could 
hide a bug if ALE is what was desired).

> +static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> +     while (len-- > 0)
> +             *buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
> +}
> +
> +static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
> +{
> +     return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
> +}

You've still got a couple unneeded casts here.

> +/*
> + * LPC32xx has only one SLC NAND controller, don't utilize
> + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
> + * both in SPL NAND and U-boot images.
> + */
> +int board_nand_init(struct nand_chip *lpc32xx_chip)
> +{
> +     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
> +     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
> +
> +     /*
> +      * Hardware ECC calculation is not supported by the driver,
> +      * because it requires DMA support, see LPC32x0 User Manual,
> +      * note after SLC_ECC register description (UM10326, p.198)
> +      */
> +     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
> +
> +     /*
> +      * The implementation of these functions is quite common, but
> +      * they MUST be defined, because access to data register
> +      * is strictly 32-bit aligned.
> +      */
> +     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
> +     lpc32xx_chip->read_byte = lpc32xx_read_byte;
> +     lpc32xx_chip->write_buf = lpc32xx_write_buf;
> +     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
> +
> +     /*
> +      * Use default ECC layout, but these values are predefined
> +      * for both small and large page NAND flash devices.
> +      */
> +     lpc32xx_chip->ecc.size  = 256;
> +     lpc32xx_chip->ecc.bytes = 3;
> +     lpc32xx_chip->ecc.strength      = 1;

Please use a space before '=', not a tab.  This doesn't even line up right, 
if that's what you were trying to do...

> +
> +#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
> +     lpc32xx_chip->bbt_options       |= NAND_BBT_USE_FLASH;
> +#endif

Likewise

-Scott

[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

Hello Scott,

On 18.07.2015 02:12, Scott Wood wrote:
> On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
>> +/* TAC register bits, be aware of overflows */
>> +#define TAC_W_RDY(n)         (max_t(uint32_t, (n), 0xF) << 28)
>> +#define TAC_W_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 24)
>> +#define TAC_W_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 20)
>> +#define TAC_W_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 16)
>> +#define TAC_R_RDY(n)         (max_t(uint32_t, (n), 0xF) << 12)
>> +#define TAC_R_WIDTH(n)               (max_t(uint32_t, (n), 0xF) << 8)
>> +#define TAC_R_HOLD(n)                (max_t(uint32_t, (n), 0xF) << 4)
>> +#define TAC_R_SETUP(n)               (max_t(uint32_t, (n), 0xF) << 0)
>> +
>> +static struct lpc32xx_nand_slc_registers __iomem 
>> *lpc32xx_nand_slc_registers
>> +     = (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;
> 
> s/registers/regs/ might help the formatting here...

it didn't noticeably help, but I changed the name.

>> +static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
>> +                               int cmd, unsigned int ctrl)
>> +{
>> +     debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
>> +
>> +     if (ctrl & NAND_NCE)
>> +             setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
>> +     else
>> +             clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
>> +
>> +     if (cmd == NAND_CMD_NONE)
>> +             return;
>> +
>> +     if (ctrl & NAND_CLE)
>> +             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
>> +     else /* if (ctrl & NAND_ALE) */
>> +             writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
>> +}
> 
> Why is "if (ctrl & NAND_ALE())" commented out?  I think it'd be better if 
> wrong uses of this function didn't silently cause address cycles (which could 
> hide a bug if ALE is what was desired).

well, wrong users are expected to be fixed out of this scope, but okay,
for sake of clarity and sanity testing and at the acceptable cost of one
more instruction let me uncomment the second condition.

>> +static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> +     while (len-- > 0)
>> +             *buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
>> +}
>> +
>> +static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
>> +{
>> +     return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
>> +}
> 
> You've still got a couple unneeded casts here.

My fault, fixed now.

>> +/*
>> + * LPC32xx has only one SLC NAND controller, don't utilize
>> + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
>> + * both in SPL NAND and U-boot images.
>> + */
>> +int board_nand_init(struct nand_chip *lpc32xx_chip)
>> +{
>> +     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
>> +     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
>> +
>> +     /*
>> +      * Hardware ECC calculation is not supported by the driver,
>> +      * because it requires DMA support, see LPC32x0 User Manual,
>> +      * note after SLC_ECC register description (UM10326, p.198)
>> +      */
>> +     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
>> +
>> +     /*
>> +      * The implementation of these functions is quite common, but
>> +      * they MUST be defined, because access to data register
>> +      * is strictly 32-bit aligned.
>> +      */
>> +     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
>> +     lpc32xx_chip->read_byte = lpc32xx_read_byte;
>> +     lpc32xx_chip->write_buf = lpc32xx_write_buf;
>> +     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
>> +
>> +     /*
>> +      * Use default ECC layout, but these values are predefined
>> +      * for both small and large page NAND flash devices.
>> +      */
>> +     lpc32xx_chip->ecc.size  = 256;
>> +     lpc32xx_chip->ecc.bytes = 3;
>> +     lpc32xx_chip->ecc.strength      = 1;
> 
> Please use a space before '=', not a tab.  This doesn't even line up right, 
> if that's what you were trying to do...

Right, that's my intention. I have no objection to non-leading spaces.

>> +
>> +#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
>> +     lpc32xx_chip->bbt_options       |= NAND_BBT_USE_FLASH;
>> +#endif
> 
> Likewise
> 

Done.

I'd like to send the updated version v3 as a reply to this email,
hopefully this is fine for you, otherwise please let me know.

Thank you for momentary review.

--
With best wishes,
Vladimir

[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Scott Wood]

On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
> Hello Scott,
> 
> On 18.07.2015 02:12, Scott Wood wrote:
> > On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> > > +/*
> > > + * LPC32xx has only one SLC NAND controller, don't utilize
> > > + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
> > > + * both in SPL NAND and U-boot images.
> > > + */
> > > +int board_nand_init(struct nand_chip *lpc32xx_chip)
> > > +{
> > > +     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
> > > +     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
> > > +
> > > +     /*
> > > +      * Hardware ECC calculation is not supported by the driver,
> > > +      * because it requires DMA support, see LPC32x0 User Manual,
> > > +      * note after SLC_ECC register description (UM10326, p.198)
> > > +      */
> > > +     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
> > > +
> > > +     /*
> > > +      * The implementation of these functions is quite common, but
> > > +      * they MUST be defined, because access to data register
> > > +      * is strictly 32-bit aligned.
> > > +      */
> > > +     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
> > > +     lpc32xx_chip->read_byte = lpc32xx_read_byte;
> > > +     lpc32xx_chip->write_buf = lpc32xx_write_buf;
> > > +     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
> > > +
> > > +     /*
> > > +      * Use default ECC layout, but these values are predefined
> > > +      * for both small and large page NAND flash devices.
> > > +      */
> > > +     lpc32xx_chip->ecc.size  = 256;
> > > +     lpc32xx_chip->ecc.bytes = 3;
> > > +     lpc32xx_chip->ecc.strength      = 1;
> > 
> > Please use a space before '=', not a tab.  This doesn't even line up 
> > right, 
> > if that's what you were trying to do...
> 
> Right, that's my intention. I have no objection to non-leading spaces.

It looks the same in v3.

-Scott

[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Scott Wood]

On Fri, 2015-07-17 at 18:53 -0500, Scott Wood wrote:
> On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
> > Hello Scott,
> > 
> > On 18.07.2015 02:12, Scott Wood wrote:
> > > On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
> > > > +/*
> > > > + * LPC32xx has only one SLC NAND controller, don't utilize
> > > > + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
> > > > + * both in SPL NAND and U-boot images.
> > > > + */
> > > > +int board_nand_init(struct nand_chip *lpc32xx_chip)
> > > > +{
> > > > +     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
> > > > +     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
> > > > +
> > > > +     /*
> > > > +      * Hardware ECC calculation is not supported by the driver,
> > > > +      * because it requires DMA support, see LPC32x0 User Manual,
> > > > +      * note after SLC_ECC register description (UM10326, p.198)
> > > > +      */
> > > > +     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
> > > > +
> > > > +     /*
> > > > +      * The implementation of these functions is quite common, but
> > > > +      * they MUST be defined, because access to data register
> > > > +      * is strictly 32-bit aligned.
> > > > +      */
> > > > +     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
> > > > +     lpc32xx_chip->read_byte = lpc32xx_read_byte;
> > > > +     lpc32xx_chip->write_buf = lpc32xx_write_buf;
> > > > +     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
> > > > +
> > > > +     /*
> > > > +      * Use default ECC layout, but these values are predefined
> > > > +      * for both small and large page NAND flash devices.
> > > > +      */
> > > > +     lpc32xx_chip->ecc.size  = 256;
> > > > +     lpc32xx_chip->ecc.bytes = 3;
> > > > +     lpc32xx_chip->ecc.strength      = 1;
> > > 
> > > Please use a space before '=', not a tab.  This doesn't even line up 
> > > right, 
> > > if that's what you were trying to do...
> > 
> > Right, that's my intention. I have no objection to non-leading spaces.
> 
> It looks the same in v3.

Actually, v3 looks just like v2 except for the revision log...

-Scott

[U-Boot] [PATCH v2 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

On 18.07.2015 02:53, Scott Wood wrote:
> On Sat, 2015-07-18 at 02:38 +0300, Vladimir Zapolskiy wrote:
>> Hello Scott,
>>
>> On 18.07.2015 02:12, Scott Wood wrote:
>>> On Sat, 2015-07-18 at 01:47 +0300, Vladimir Zapolskiy wrote:
>>>> +/*
>>>> + * LPC32xx has only one SLC NAND controller, don't utilize
>>>> + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
>>>> + * both in SPL NAND and U-boot images.
>>>> + */
>>>> +int board_nand_init(struct nand_chip *lpc32xx_chip)
>>>> +{
>>>> +     lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
>>>> +     lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
>>>> +
>>>> +     /*
>>>> +      * Hardware ECC calculation is not supported by the driver,
>>>> +      * because it requires DMA support, see LPC32x0 User Manual,
>>>> +      * note after SLC_ECC register description (UM10326, p.198)
>>>> +      */
>>>> +     lpc32xx_chip->ecc.mode  = NAND_ECC_SOFT;
>>>> +
>>>> +     /*
>>>> +      * The implementation of these functions is quite common, but
>>>> +      * they MUST be defined, because access to data register
>>>> +      * is strictly 32-bit aligned.
>>>> +      */
>>>> +     lpc32xx_chip->read_buf  = lpc32xx_read_buf;
>>>> +     lpc32xx_chip->read_byte = lpc32xx_read_byte;
>>>> +     lpc32xx_chip->write_buf = lpc32xx_write_buf;
>>>> +     lpc32xx_chip->write_byte        = lpc32xx_write_byte;
>>>> +
>>>> +     /*
>>>> +      * Use default ECC layout, but these values are predefined
>>>> +      * for both small and large page NAND flash devices.
>>>> +      */
>>>> +     lpc32xx_chip->ecc.size  = 256;
>>>> +     lpc32xx_chip->ecc.bytes = 3;
>>>> +     lpc32xx_chip->ecc.strength      = 1;
>>>
>>> Please use a space before '=', not a tab.  This doesn't even line up 
>>> right, 
>>> if that's what you were trying to do...
>>
>> Right, that's my intention. I have no objection to non-leading spaces.
> 
> It looks the same in v3.
> 

I'm so sorry for confusion. Seems that "git format-patch" produces an
old change, if it is called in the middle of "git rebase"...

--
With best wishes,
Vladimir

[U-Boot] [PATCH v3 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v2 to v3:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
  - removed unnecessary uint32_t casts in write_buf()/write_byte(),
  - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
    and generally not needed for custom defined PIO interfaces in
    U-boot (with exception of simple NAND SPL, addressed by 1/4),
  - removed leftover declarations of HW ECC related bit fields,
    this should be added along with HW ECC support,
  - improved description of a reason why software ECC is selected,
    if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:

  v1:
    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html

  v2:
    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 5a453e3..b0287be 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 9449869..010211a 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index c3d890d..0845f83 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 347ea62..e2dc99a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
new file mode 100644
index 0000000..bc2fb8e
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -0,0 +1,176 @@
+/*
+ * LPC32xx SLC NAND flash controller driver
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+
+struct lpc32xx_nand_slc_registers {
+	u32 data;
+	u32 addr;
+	u32 cmd;
+	u32 stop;
+	u32 ctrl;
+	u32 cfg;
+	u32 stat;
+	u32 int_stat;
+	u32 ien;
+	u32 isr;
+	u32 icr;
+	u32 tac;
+	u32 tc;
+	u32 ecc;
+	u32 dma_data;
+};
+
+/* CFG register */
+#define CFG_CE_LOW		(1 << 5)
+
+/* CTRL register */
+#define CTRL_SW_RESET		(1 << 2)
+
+/* STAT register */
+#define STAT_NAND_READY		(1 << 0)
+
+/* INT_STAT register */
+#define INT_STAT_TC		(1 << 1)
+#define INT_STAT_RDY		(1 << 0)
+
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n)		(max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n)		(max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_registers __iomem *lpc32xx_nand_slc_registers
+	= (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE;
+
+static void lpc32xx_nand_init(void)
+{
+	uint32_t hclk = get_hclk_clk_rate();
+
+	/* Reset SLC NAND controller */
+	writel(CTRL_SW_RESET, &lpc32xx_nand_slc_registers->ctrl);
+
+	/* 8-bit bus, no DMA, no ECC, ordinary CE signal */
+	writel(0, &lpc32xx_nand_slc_registers->cfg);
+
+	/* Interrupts disabled and cleared */
+	writel(0, &lpc32xx_nand_slc_registers->ien);
+	writel(INT_STAT_TC | INT_STAT_RDY,
+	       &lpc32xx_nand_slc_registers->icr);
+
+	/* Configure NAND flash timings */
+	writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
+	       TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
+	       TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
+	       TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
+	       TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
+	       TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
+	       TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
+	       TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
+	       &lpc32xx_nand_slc_registers->tac);
+}
+
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+				  int cmd, unsigned int ctrl)
+{
+	debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+	if (ctrl & NAND_NCE)
+		setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+	else
+		clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW);
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd);
+	else /* if (ctrl & NAND_ALE) */
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr);
+}
+
+static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
+{
+	return readl(&lpc32xx_nand_slc_registers->stat) & STAT_NAND_READY;
+}
+
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		*buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+	return (uint8_t)readl(&lpc32xx_nand_slc_registers->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		writel(*buf++, &lpc32xx_nand_slc_registers->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+	writel(byte, &lpc32xx_nand_slc_registers->data);
+}
+
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+	lpc32xx_chip->cmd_ctrl	= lpc32xx_nand_cmd_ctrl;
+	lpc32xx_chip->dev_ready	= lpc32xx_nand_dev_ready;
+
+	/*
+	 * Hardware ECC calculation is not supported by the driver,
+	 * because it requires DMA support, see LPC32x0 User Manual,
+	 * note after SLC_ECC register description (UM10326, p.198)
+	 */
+	lpc32xx_chip->ecc.mode	= NAND_ECC_SOFT;
+
+	/*
+	 * The implementation of these functions is quite common, but
+	 * they MUST be defined, because access to data register
+	 * is strictly 32-bit aligned.
+	 */
+	lpc32xx_chip->read_buf	= lpc32xx_read_buf;
+	lpc32xx_chip->read_byte	= lpc32xx_read_byte;
+	lpc32xx_chip->write_buf	= lpc32xx_write_buf;
+	lpc32xx_chip->write_byte	= lpc32xx_write_byte;
+
+	/*
+	 * Use default ECC layout, but these values are predefined
+	 * for both small and large page NAND flash devices.
+	 */
+	lpc32xx_chip->ecc.size	= 256;
+	lpc32xx_chip->ecc.bytes	= 3;
+	lpc32xx_chip->ecc.strength	= 1;
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+	lpc32xx_chip->bbt_options	|= NAND_BBT_USE_FLASH;
+#endif
+
+	/* Initialize NAND interface */
+	lpc32xx_nand_init();
+
+	return 0;
+}
-- 
2.1.4

[U-Boot] [PATCH v4 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v3 to v4:
* renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
* replaced non-leading tabs with spaces to get columned assignments,
* removed leftover redundant type casts,
* lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).

Changes from v2 to v3:
* no changes, sent a non-rebased version by mistake.

Changes from v1 to v2:
* addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
  - removed unnecessary uint32_t casts in write_buf()/write_byte(),
  - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
    and generally not needed for custom defined PIO interfaces in
    U-boot (with exception of simple NAND SPL, addressed by 1/4),
  - removed leftover declarations of HW ECC related bit fields,
    this should be added along with HW ECC support,
  - improved description of a reason why software ECC is selected,
    if DMA is unavailable (explicit reference to User Manual from NXP).

Previous review can be found here:
  v3:
    http://lists.denx.de/pipermail/u-boot/2015-July/219431.html

  v2:
    http://lists.denx.de/pipermail/u-boot/2015-July/219422.html

  v1:
    http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
    http://lists.denx.de/pipermail/u-boot/2015-July/219254.html

 arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
 arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
 arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
 drivers/mtd/nand/Makefile                     |   1 +
 drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
 5 files changed, 186 insertions(+)
 create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 5a453e3..b0287be 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void)
 	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
 }
 
+void lpc32xx_slc_nand_init(void)
+{
+	/* Enable SLC NAND interface */
+	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
+}
+
 void lpc32xx_i2c_init(unsigned int devnum)
 {
 	/* Enable I2C interface */
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 9449869..010211a 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -153,7 +153,9 @@ struct clk_pm_regs {
 #define CLK_DMA_ENABLE			(1 << 0)
 
 /* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
 #define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
 #define CLK_NAND_MLC_INT		(1 << 5)
 
 /* SSP Clock Control Register bits */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index c3d890d..0845f83 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -12,6 +12,7 @@
 void lpc32xx_uart_init(unsigned int uart_id);
 void lpc32xx_mac_init(void);
 void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
 void lpc32xx_i2c_init(unsigned int devnum);
 void lpc32xx_ssp_init(void);
 #if defined(CONFIG_SPL_BUILD)
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 347ea62..e2dc99a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
+obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
 obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
new file mode 100644
index 0000000..719a74d
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -0,0 +1,176 @@
+/*
+ * LPC32xx SLC NAND flash controller driver
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+
+struct lpc32xx_nand_slc_regs {
+	u32 data;
+	u32 addr;
+	u32 cmd;
+	u32 stop;
+	u32 ctrl;
+	u32 cfg;
+	u32 stat;
+	u32 int_stat;
+	u32 ien;
+	u32 isr;
+	u32 icr;
+	u32 tac;
+	u32 tc;
+	u32 ecc;
+	u32 dma_data;
+};
+
+/* CFG register */
+#define CFG_CE_LOW		(1 << 5)
+
+/* CTRL register */
+#define CTRL_SW_RESET		(1 << 2)
+
+/* STAT register */
+#define STAT_NAND_READY		(1 << 0)
+
+/* INT_STAT register */
+#define INT_STAT_TC		(1 << 1)
+#define INT_STAT_RDY		(1 << 0)
+
+/* TAC register bits, be aware of overflows */
+#define TAC_W_RDY(n)		(max_t(uint32_t, (n), 0xF) << 28)
+#define TAC_W_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 24)
+#define TAC_W_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 20)
+#define TAC_W_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 16)
+#define TAC_R_RDY(n)		(max_t(uint32_t, (n), 0xF) << 12)
+#define TAC_R_WIDTH(n)		(max_t(uint32_t, (n), 0xF) << 8)
+#define TAC_R_HOLD(n)		(max_t(uint32_t, (n), 0xF) << 4)
+#define TAC_R_SETUP(n)		(max_t(uint32_t, (n), 0xF) << 0)
+
+static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
+	= (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
+
+static void lpc32xx_nand_init(void)
+{
+	uint32_t hclk = get_hclk_clk_rate();
+
+	/* Reset SLC NAND controller */
+	writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
+
+	/* 8-bit bus, no DMA, no ECC, ordinary CE signal */
+	writel(0, &lpc32xx_nand_slc_regs->cfg);
+
+	/* Interrupts disabled and cleared */
+	writel(0, &lpc32xx_nand_slc_regs->ien);
+	writel(INT_STAT_TC | INT_STAT_RDY,
+	       &lpc32xx_nand_slc_regs->icr);
+
+	/* Configure NAND flash timings */
+	writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
+	       TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
+	       TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
+	       TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
+	       TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
+	       TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
+	       TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
+	       TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
+	       &lpc32xx_nand_slc_regs->tac);
+}
+
+static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
+				  int cmd, unsigned int ctrl)
+{
+	debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
+
+	if (ctrl & NAND_NCE)
+		setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
+	else
+		clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
+
+	if (cmd == NAND_CMD_NONE)
+		return;
+
+	if (ctrl & NAND_CLE)
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
+	else if (ctrl & NAND_ALE)
+		writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
+}
+
+static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
+{
+	return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
+}
+
+static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		*buf++ = readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+	return readl(&lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+	while (len-- > 0)
+		writel(*buf++, &lpc32xx_nand_slc_regs->data);
+}
+
+static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
+{
+	writel(byte, &lpc32xx_nand_slc_regs->data);
+}
+
+/*
+ * LPC32xx has only one SLC NAND controller, don't utilize
+ * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
+ * both in SPL NAND and U-boot images.
+ */
+int board_nand_init(struct nand_chip *lpc32xx_chip)
+{
+	lpc32xx_chip->cmd_ctrl  = lpc32xx_nand_cmd_ctrl;
+	lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
+
+	/*
+	 * Hardware ECC calculation is not supported by the driver,
+	 * because it requires DMA support, see LPC32x0 User Manual,
+	 * note after SLC_ECC register description (UM10326, p.198)
+	 */
+	lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
+
+	/*
+	 * The implementation of these functions is quite common, but
+	 * they MUST be defined, because access to data register
+	 * is strictly 32-bit aligned.
+	 */
+	lpc32xx_chip->read_buf   = lpc32xx_read_buf;
+	lpc32xx_chip->read_byte  = lpc32xx_read_byte;
+	lpc32xx_chip->write_buf  = lpc32xx_write_buf;
+	lpc32xx_chip->write_byte = lpc32xx_write_byte;
+
+	/*
+	 * Use default ECC layout, but these values are predefined
+	 * for both small and large page NAND flash devices.
+	 */
+	lpc32xx_chip->ecc.size     = 256;
+	lpc32xx_chip->ecc.bytes    = 3;
+	lpc32xx_chip->ecc.strength = 1;
+
+#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
+	lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
+
+	/* Initialize NAND interface */
+	lpc32xx_nand_init();
+
+	return 0;
+}
-- 
2.1.4

[U-Boot] [PATCH v4 2/4] nand: lpc32xx: add SLC NAND controller support

[Vladimir Zapolskiy]

Hello Scott,

On 18.07.2015 03:07, Vladimir Zapolskiy wrote:
> The change adds support of LPC32xx SLC NAND controller.
> 
> LPC32xx SoC has two different mutually exclusive NAND controllers to
> communicate with single and multiple layer chips.
> 
> This simple driver allows to specify NAND chip timings and defines
> custom read_buf()/write_buf() operations, because access to 8-bit data
> register must be 32-bit aligned.
> 
> Support of hardware ECC calculation is not implemented (data
> correction is always done by software), since it requires a working
> DMA engine.
> 
> The driver can be included to an SPL image.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v3 to v4:
> * renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
> * replaced non-leading tabs with spaces to get columned assignments,
> * removed leftover redundant type casts,
> * lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).
> 
> Changes from v2 to v3:
> * no changes, sent a non-rebased version by mistake.
> 
> Changes from v1 to v2:
> * addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
>   - removed unnecessary uint32_t casts in write_buf()/write_byte(),
>   - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
>     and generally not needed for custom defined PIO interfaces in
>     U-boot (with exception of simple NAND SPL, addressed by 1/4),
>   - removed leftover declarations of HW ECC related bit fields,
>     this should be added along with HW ECC support,
>   - improved description of a reason why software ECC is selected,
>     if DMA is unavailable (explicit reference to User Manual from NXP).
> 
> Previous review can be found here:
>   v3:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219431.html
> 
>   v2:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219422.html
> 
>   v1:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
>     http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
> 
>  arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
>  arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
>  arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
>  drivers/mtd/nand/Makefile                     |   1 +
>  drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 ++++++++++++++++++++++++++
>  5 files changed, 186 insertions(+)
>  create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
> 

please let me know, if this change is ready for inclusion to the next
U-boot release. The following changes from the series to a board file
(NAND and SPL build) depend on this one, if this SLC NAND change is
accepted I hope Albert may find time to include board specific changes
as well.

Thank you in advance.

--
With best wishes,
Vladimir

[U-Boot] [PATCH v4 2/4] nand: lpc32xx: add SLC NAND controller support

[Scott Wood]

On Sat, 2015-07-18 at 03:07 +0300, Vladimir Zapolskiy wrote:
> The change adds support of LPC32xx SLC NAND controller.
> 
> LPC32xx SoC has two different mutually exclusive NAND controllers to
> communicate with single and multiple layer chips.
> 
> This simple driver allows to specify NAND chip timings and defines
> custom read_buf()/write_buf() operations, because access to 8-bit data
> register must be 32-bit aligned.
> 
> Support of hardware ECC calculation is not implemented (data
> correction is always done by software), since it requires a working
> DMA engine.
> 
> The driver can be included to an SPL image.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v3 to v4:
> * renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
> * replaced non-leading tabs with spaces to get columned assignments,
> * removed leftover redundant type casts,
> * lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).
> 
> Changes from v2 to v3:
> * no changes, sent a non-rebased version by mistake.
> 
> Changes from v1 to v2:
> * addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
>   - removed unnecessary uint32_t casts in write_buf()/write_byte(),
>   - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
>     and generally not needed for custom defined PIO interfaces in
>     U-boot (with exception of simple NAND SPL, addressed by 1/4),
>   - removed leftover declarations of HW ECC related bit fields,
>     this should be added along with HW ECC support,
>   - improved description of a reason why software ECC is selected,
>     if DMA is unavailable (explicit reference to User Manual from NXP).
> 
> Previous review can be found here:
>   v3:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219431.html
> 
>   v2:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219422.html
> 
>   v1:
>     http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
>     http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
> 
>  arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
>  arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
>  arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
>  drivers/mtd/nand/Makefile                     |   1 +
>  drivers/mtd/nand/lpc32xx_nand_slc.c           | 176 
> ++++++++++++++++++++++++++
>  5 files changed, 186 insertions(+)
>  create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c

Acked-by: Scott Wood <scottwood@freescale.com>

-Scott

[U-Boot] [PATCH v4 2/4] nand: lpc32xx: add SLC NAND controller support

[LEMIEUX, SYLVAIN]

> From: Scott Wood [mailto:scottwood at freescale.com]
> Sent: 27-Jul-15 9:24 PM
>
> On Sat, 2015-07-18 at 03:07 +0300, Vladimir Zapolskiy wrote:
> > The change adds support of LPC32xx SLC NAND controller.
> >
> > LPC32xx SoC has two different mutually exclusive NAND controllers to
> > communicate with single and multiple layer chips.
> >
> > This simple driver allows to specify NAND chip timings and defines
> > custom read_buf()/write_buf() operations, because access to 8-bit data
> > register must be 32-bit aligned.
> >
> > Support of hardware ECC calculation is not implemented (data
> > correction is always done by software), since it requires a working
> > DMA engine.
> >
> > The driver can be included to an SPL image.
> >
> > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> > ---
> > Changes from v3 to v4:
> > * renamed "lpc32xx_nand_slc_registers" to "lpc32xx_nand_slc_regs",
> > * replaced non-leading tabs with spaces to get columned assignments,
> > * removed leftover redundant type casts,
> > * lpc32xx_nand_cmd_ctrl() sets address register iff (ctrl & NAND_ALE).
> >
> > Changes from v2 to v3:
> > * no changes, sent a non-rebased version by mistake.
> >
> > Changes from v1 to v2:
> > * addressed Albert's and Scott's comments to LPC32xx SLC NAND driver:
> >   - removed unnecessary uint32_t casts in write_buf()/write_byte(),
> >   - removed IO_ADDR_[RW] assignment, this is done in nand.c for SPL
> >     and generally not needed for custom defined PIO interfaces in
> >     U-boot (with exception of simple NAND SPL, addressed by 1/4),
> >   - removed leftover declarations of HW ECC related bit fields,
> >     this should be added along with HW ECC support,
> >   - improved description of a reason why software ECC is selected,
> >     if DMA is unavailable (explicit reference to User Manual from NXP).
> >
> > Previous review can be found here:
> >   v3:
> >     http://lists.denx.de/pipermail/u-boot/2015-July/219431.html
> >
> >   v2:
> >     http://lists.denx.de/pipermail/u-boot/2015-July/219422.html
> >
> >   v1:
> >     http://lists.denx.de/pipermail/u-boot/2015-July/219095.html
> >     http://lists.denx.de/pipermail/u-boot/2015-July/219254.html
> >
> >  arch/arm/cpu/arm926ejs/lpc32xx/devices.c      |   6 +
> >  arch/arm/include/asm/arch-lpc32xx/clk.h       |   2 +
> >  arch/arm/include/asm/arch-lpc32xx/sys_proto.h |   1 +
> >  drivers/mtd/nand/Makefile                     |   1 +
> >  drivers/mtd/nand/lpc32xx_nand_slc.c           | 176
> > ++++++++++++++++++++++++++
> >  5 files changed, 186 insertions(+)
> >  create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c
>
> Acked-by: Scott Wood <scottwood@freescale.com>
>
> -Scott

Tested for large page NAND.
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>


________________________________

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[U-Boot] [U-Boot, v4, 2/4] nand: lpc32xx: add SLC NAND controller support

[Tom Rini]

On Sat, Jul 18, 2015 at 03:07:52AM +0300, Vladimir Zapolskiy wrote:

> The change adds support of LPC32xx SLC NAND controller.
> 
> LPC32xx SoC has two different mutually exclusive NAND controllers to
> communicate with single and multiple layer chips.
> 
> This simple driver allows to specify NAND chip timings and defines
> custom read_buf()/write_buf() operations, because access to 8-bit data
> register must be 32-bit aligned.
> 
> Support of hardware ECC calculation is not implemented (data
> correction is always done by software), since it requires a working
> DMA engine.
> 
> The driver can be included to an SPL image.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Acked-by: Scott Wood <scottwood@freescale.com>
> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH v2 3/4] lpc32xx: devkit3250: update of board configuration

[Vladimir Zapolskiy]

This change adds more peripherals to Timll DevKit3250 board, namely
MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.

Also the default serial console is changed to UART5, added an option
to pass device tree blob by means of bootm, predefined environment
variables are slightly extended and reserved space on NAND to store
user defined U-boot environment.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* no changes

Previous review and discussion can be found here:
  http://lists.denx.de/pipermail/u-boot/2015-July/219252.html

 board/timll/devkit3250/devkit3250.c | 31 ++++++++++++-
 configs/devkit3250_defconfig        |  3 ++
 include/configs/devkit3250.h        | 92 +++++++++++++++++++++++++++++++++++--
 3 files changed, 120 insertions(+), 6 deletions(-)

diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 6acc416..4b3c94e 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c
@@ -1,23 +1,52 @@
 /*
  * Embest/Timll DevKit3250 board support
  *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/emc.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_periph(void)
+{
+	/* This function resets peripherals by triggering RESOUT_N */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+	writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
+	udelay(300);
+
+	writel(0, &wdt->mctrl);
+	clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* Such a long delay is needed to initialize SMSC phy */
+	udelay(10000);
+}
 
 int board_early_init_f(void)
 {
 	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	lpc32xx_i2c_init(1);
+	lpc32xx_i2c_init(2);
+	lpc32xx_ssp_init();
+	lpc32xx_mac_init();
+
+	/*
+	 * nWP may be controlled by GPO19, but unpopulated by default R23
+	 * makes no sense to configure this GPIO level, nWP is always high
+	 */
+	lpc32xx_slc_nand_init();
 
 	return 0;
 }
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index f0c4ee1..56d719f 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,3 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DEVKIT3250=y
+# CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 4f35234..b8218b5 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -1,7 +1,7 @@
 /*
  * Embest/Timll DevKit3250 board configuration file
  *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -43,10 +43,44 @@
 /*
  * Serial Driver
  */
-#define CONFIG_SYS_LPC32XX_UART		2   /* UART2 */
+#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 */
 #define CONFIG_BAUDRATE			115200
 
 /*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_LPC32XX
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+
+/*
+ * GPIO
+ */
+#define CONFIG_LPC32XX_GPIO
+#define CONFIG_CMD_GPIO
+
+/*
+ * SSP/SPI
+ */
+#define CONFIG_LPC32XX_SSP
+#define CONFIG_LPC32XX_SSP_TIMEOUT	100000
+#define CONFIG_CMD_SPI
+
+/*
+ * Ethernet
+ */
+#define CONFIG_RMII
+#define CONFIG_PHY_SMSC
+#define CONFIG_LPC32XX_ETH
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0x1F
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/*
  * NOR Flash
  */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
@@ -56,6 +90,29 @@
 #define CONFIG_SYS_FLASH_CFI
 
 /*
+ * NAND controller
+ */
+#define CONFIG_NAND_LPC32XX_SLC
+#define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+
+/*
+ * NAND chip timings
+ */
+#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS	14
+#define CONFIG_LPC32XX_NAND_SLC_WWIDTH		66666666
+#define CONFIG_LPC32XX_NAND_SLC_WHOLD		200000000
+#define CONFIG_LPC32XX_NAND_SLC_WSETUP		50000000
+#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS	14
+#define CONFIG_LPC32XX_NAND_SLC_RWIDTH		66666666
+#define CONFIG_LPC32XX_NAND_SLC_RHOLD		200000000
+#define CONFIG_LPC32XX_NAND_SLC_RSETUP		50000000
+
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
+/*
  * U-Boot General Configurations
  */
 #define CONFIG_SYS_LONGHELP
@@ -71,8 +128,33 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_ENV_IS_NOWHERE
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND		1
 #define CONFIG_ENV_SIZE			SZ_128K
+#define CONFIG_ENV_OFFSET		0x000A0000
+
+#define CONFIG_BOOTCOMMAND			\
+	"dhcp; "				\
+	"tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "		\
+	"tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "	\
+	"setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "	\
+	"setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "			\
+	"bootm ${loadaddr} - ${dtbaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"autoload=no\0"				\
+	"ethaddr=00:01:90:00:C0:81\0"		\
+	"dtbaddr=0x81000000\0"			\
+	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"	\
+	"tftpdir=vladimir/oe/devkit3250\0"	\
+	"userargs=oops=panic\0"
 
 /*
  * U-Boot Commands
@@ -85,10 +167,10 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTDELAY		1
 
 #define CONFIG_BOOTFILE			"uImage"
-#define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
+#define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
 #define CONFIG_LOADADDR			0x80008000
 
 /*
-- 
2.1.4

[U-Boot] [U-Boot, v2, 3/4] lpc32xx: devkit3250: update of board configuration

[Tom Rini]

On Sat, Jul 18, 2015 at 01:47:10AM +0300, Vladimir Zapolskiy wrote:
> This change adds more peripherals to Timll DevKit3250 board, namely

> MAC and SMSC phy, SLC NAND, GPIO, SPI and I2C.
> 
> Also the default serial console is changed to UART5, added an option
> to pass device tree blob by means of bootm, predefined environment
> variables are slightly extended and reserved space on NAND to store
> user defined U-boot environment.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH v2 4/4] lpc32xx: devkit3250: add spl build support

[Vladimir Zapolskiy]

The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.

All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
---
Changes from v1 to v2:
* no changes

The same version of the change can be found here
  http://lists.denx.de/pipermail/u-boot/2015-July/219251.html

 arch/arm/Kconfig                        |  1 +
 board/timll/devkit3250/Makefile         |  1 +
 board/timll/devkit3250/devkit3250_spl.c | 68 +++++++++++++++++++++++++++++++++
 configs/devkit3250_defconfig            |  1 +
 include/configs/devkit3250.h            | 53 +++++++++++++++++++++++++
 5 files changed, 124 insertions(+)
 create mode 100644 board/timll/devkit3250/devkit3250_spl.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 506463c..95b15bc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -121,6 +121,7 @@ config TARGET_MAXBCM
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
 
 config TARGET_WORK_92105
 	bool "Support work_92105"
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
index 4722986..74d5cd3 100644
--- a/board/timll/devkit3250/Makefile
+++ b/board/timll/devkit3250/Makefile
@@ -6,3 +6,4 @@
 #
 
 obj-y	:= devkit3250.o
+obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
new file mode 100644
index 0000000..bf52698
--- /dev/null
+++ b/board/timll/devkit3250/devkit3250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Timll DevKit3250 board support, SPL board configuration
+ *
+ * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+#include <asm/arch-lpc32xx/gpio.h>
+#include <spl.h>
+
+static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+/*
+ * SDRAM K4S561632N-LC60 settings are selected in assumption that
+ * SDRAM clock may be set up to 166 MHz, however at the moment
+ * it is 104 MHz. Most delay values are converted to be a multiple of
+ * base clock, and precise pinned values are not needed here.
+ */
+struct emc_dram_settings dram_64mb = {
+	.cmddelay	= 0x0001C000,
+	.config0	= 0x00005682,
+	.rascas0	= 0x00000302,
+	.rdconfig	= 0x00000011,	/* undocumented but crucial value */
+
+	.trp	= 83333333,
+	.tras	= 23809524,
+	.tsrex	= 12500000,
+	.twr	= 83000000,		/* tWR = tRDL = 2 CLK */
+	.trc	= 15384616,
+	.trfc	= 15384616,
+	.txsr	= 12500000,
+	.trrd	= 1,
+	.tmrd	= 1,
+	.tcdlr	= 0,
+
+	.refresh	= 130000,	/* 800 clock cycles */
+
+	.mode	= 0x00018000,
+	.emode	= 0x02000000,
+};
+
+void spl_board_init(void)
+{
+	/* First of all silence buzzer controlled by GPO_20 */
+	writel((1 << 20), &gpio->p3_outp_clr);
+
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+	preloader_console_init();
+
+	ddr_init(&dram_64mb);
+
+	/*
+	 * NAND initialization is done by nand_init(),
+	 * here just enable NAND SLC clocks
+	 */
+	lpc32xx_slc_nand_init();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 56d719f..7246da5 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DEVKIT3250=y
+CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_DM=y
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index b8218b5..cc6a53e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -21,7 +21,9 @@
 
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
+#if !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 #define CONFIG_BOARD_EARLY_INIT_F
 
 /*
@@ -174,6 +176,57 @@
 #define CONFIG_LOADADDR			0x80008000
 
 /*
+ * SPL specific defines
+ */
+/* SPL will be executed at offset 0 */
+#define CONFIG_SPL_TEXT_BASE		0x00000000
+
+/* SPL will use SRAM as stack */
+#define CONFIG_SPL_STACK		0x0000FFF8
+#define CONFIG_SPL_BOARD_INIT
+
+/* Use the framework and generic lib */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* SPL will use serial */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* SPL loads an image from NAND */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_ECCSIZE		0x100
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SPL_MAX_SIZE		0x20000
+#define CONFIG_SPL_PAD_TO		CONFIG_SPL_MAX_SIZE
+
+/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+
+/* See common/spl/spl.c  spl_set_header_raw_uboot() */
+#define CONFIG_SYS_MONITOR_LEN		CONFIG_SYS_NAND_U_BOOT_SIZE
+
+/*
  * Include SoC specific configuration
  */
 #include <asm/arch/config.h>
-- 
2.1.4

[U-Boot] [U-Boot, v2, 4/4] lpc32xx: devkit3250: add spl build support

[Tom Rini]

On Sat, Jul 18, 2015 at 01:47:11AM +0300, Vladimir Zapolskiy wrote:

> The change adds SPL build support to Timll DevKit3250 board, the
> generated SPL image can be uploaded over UART5, JTAG or stored on
> NAND. SPL is designed to load U-boot image from NAND.
> 
> All new NAND chip defines in board configuration are needed by
> SPL NAND "simple" framework, the framework is used to reduce
> potentially duplicated code from LPC32xx SLC NAND driver.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [PATCH v2 0/4] lpc32xx: devkit3250 board update

[Vladimir Zapolskiy]

Hello Albert,

On 18.07.2015 01:46, Vladimir Zapolskiy wrote:
> This changeset improves support of Timll DevKit3250 board:
> * added LPC32xx MAC and SMSC RMII phy support, this dependends on
>   - http://patchwork.ozlabs.org/patch/489100/
>   - http://patchwork.ozlabs.org/patch/489190/
>   - http://patchwork.ozlabs.org/patch/491419/
>   - http://patchwork.ozlabs.org/patch/491420/
> * added GPIO, SPI, I2C support, works good, many thanks to Albert,
> * added LPC32xx SLC NAND driver, testing of 50 MiB data raw reading
>   shows 1 MiB/s speed, the same change has been sent to the mailing
>   list separately, here it is duplicated as a build dependency:
>   - http://patchwork.ozlabs.org/patch/495247/
>   - http://patchwork.ozlabs.org/patch/495250/
> * added an option to pass DTB to an operating system,
> * changed serial console to commonly used as default UART5,
> * boot delay is set to 1 for convenience,
> * extended predefined environment variables and reserved space on NAND,
> * added an option to build SPL image for the board, by default SPL
>   downloads U-boot image from NAND (offset 0x40000, size 0x60000).
> 
> Changes from v1 to v2:
> * addressed Albert's and Scott's comments to LPC32xx SLC NAND driver,
>   see patch v2 2/4,
> * added Tegra and TI maintainers to Cc list to review/ack a change 1/4
>   in simple NAND SPL framework, which potentially (very unlikely)
>   may cause a regression in NAND SPL on Tegra, TI OMAP or TI DaVinci
>   platforms.
> 
> Previous version of the change and discussion can be found here:
>   http://lists.denx.de/pipermail/u-boot/2015-July/219253.html
> 
> Albert, from commit logs I noticed that WORK92105 has SLC NAND chip,
> but it is managed by MLC controller, if you have any plans to test
> LPC32xx SLC NAND driver from the series, please *be aware* of
> different OOB layouts, I found it is quite easy to screw up the chip,
> if SLC and MLC are interchanged, so that only "nand scrub" helps.
> FWIW this SLC NAND driver uses a default OOB layout, the same one
> is found in Linux LPC32xx SLC NAND driver.
> 
> Vladimir Zapolskiy (4):
>   spl: nand: simple: replace readb() with chip specific read_buf()
>   nand: lpc32xx: add SLC NAND controller support
>   lpc32xx: devkit3250: update of board configuration
>   lpc32xx: devkit3250: add spl build support

do you see any left issues in this series or in MAC series mentioned on
top? If no, please could you apply these 8 patches?

Thank you in advance.

--
With best wishes,
Vladimir