From: Tero Kristo <t-kristo@ti.com>
To: Roger Quadros <rogerq@ti.com>, kishon@ti.com, tony@atomide.com
Cc: nm@ti.com, nsekhar@ti.com, balbi@ti.com,
grygorii.strashko@ti.com, linux-omap@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
Date: Mon, 20 Jul 2015 15:08:21 +0300 [thread overview]
Message-ID: <55ACE4B5.7000107@ti.com> (raw)
In-Reply-To: <1437140844-6032-3-git-send-email-rogerq@ti.com>
On 07/17/2015 04:47 PM, Roger Quadros wrote:
> This register is required to be passed to the SATA PHY driver
> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> arch/arm/boot/dts/dra7.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 8f1e25b..4a0718c 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -1140,6 +1140,7 @@
> ctrl-module = <&omap_control_sata>;
> clocks = <&sys_clkin1>, <&sata_ref_clk>;
> clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> #phy-cells = <0>;
> };
>
>
Looks fine to me.
Make sure you use this register via regmap_update_bits only, seeing
there is another potential user for the same register.
-Tero
WARNING: multiple messages have this Message-ID (diff)
From: Tero Kristo <t-kristo@ti.com>
To: Roger Quadros <rogerq@ti.com>, <kishon@ti.com>, <tony@atomide.com>
Cc: <nm@ti.com>, <nsekhar@ti.com>, <balbi@ti.com>,
<grygorii.strashko@ti.com>, <linux-omap@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY
Date: Mon, 20 Jul 2015 15:08:21 +0300 [thread overview]
Message-ID: <55ACE4B5.7000107@ti.com> (raw)
In-Reply-To: <1437140844-6032-3-git-send-email-rogerq@ti.com>
On 07/17/2015 04:47 PM, Roger Quadros wrote:
> This register is required to be passed to the SATA PHY driver
> to workaround errata i783 (SATA Lockup After SATA DPLL Unlock/Relock).
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> arch/arm/boot/dts/dra7.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 8f1e25b..4a0718c 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -1140,6 +1140,7 @@
> ctrl-module = <&omap_control_sata>;
> clocks = <&sys_clkin1>, <&sata_ref_clk>;
> clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> #phy-cells = <0>;
> };
>
>
Looks fine to me.
Make sure you use this register via regmap_update_bits only, seeing
there is another potential user for the same register.
-Tero
next prev parent reply other threads:[~2015-07-20 12:08 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-17 13:47 [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention) Roger Quadros
2015-07-17 13:47 ` Roger Quadros
2015-07-17 13:47 ` [PATCH v3 1/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock Roger Quadros
2015-07-17 13:47 ` Roger Quadros
2015-07-17 13:47 ` [PATCH v3 2/3] ARM: dts: dra7: Add syscon-pllreset syscon to SATA PHY Roger Quadros
2015-07-17 13:47 ` Roger Quadros
2015-07-20 12:08 ` Tero Kristo [this message]
2015-07-20 12:08 ` Tero Kristo
2015-07-27 9:34 ` Roger Quadros
2015-07-27 9:34 ` Roger Quadros
2015-08-04 8:19 ` Roger Quadros
2015-08-04 8:19 ` Roger Quadros
2015-08-04 8:41 ` Tony Lindgren
2015-08-04 15:43 ` Kishon Vijay Abraham I
2015-08-04 15:43 ` Kishon Vijay Abraham I
2015-07-17 13:47 ` [PATCH v3 3/3] ARM: dts: dra7: Add scm_conf1 node and remove redundant nodes Roger Quadros
2015-07-17 13:47 ` Roger Quadros
2015-07-20 12:04 ` Tero Kristo
2015-07-20 12:04 ` Tero Kristo
2015-07-21 5:11 ` Kishon Vijay Abraham I
2015-07-21 5:11 ` Kishon Vijay Abraham I
2015-07-27 9:40 ` Roger Quadros
2015-07-27 9:40 ` Roger Quadros
2015-07-27 9:40 ` Roger Quadros
2015-07-27 9:40 ` Roger Quadros
2015-07-27 10:21 ` [PATCH v3 0/3] phy: ti-pipe3: dra7: sata: allow suspend to RAM (core-retention) Roger Quadros
2015-07-27 10:21 ` Roger Quadros
2015-07-27 10:37 ` Roger Quadros
2015-07-27 10:37 ` Roger Quadros
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