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From: "Goel, Akash" <akash.goel@intel.com>
To: Michel Thierry <michel.thierry@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v6 12/19] drm/i915: Expand error state's address width to 64b
Date: Thu, 30 Jul 2015 10:39:37 +0530	[thread overview]
Message-ID: <55B9B191.3050407@intel.com> (raw)
In-Reply-To: <1438187043-34267-13-git-send-email-michel.thierry@intel.com>

Reviewed the patch & it looks fine.
Reviewed-by: "Akash Goel <akash.goel@intel.com>"

On 7/29/2015 9:53 PM, Michel Thierry wrote:
> v2: For semaphore errors, object is mapped to GGTT and offset will not
> be > 4GB, print only lower 32-bits (Akash)
> v3: Print gtt_offset in groups of 32-bit (Chris)
>
> Cc: Akash Goel <akash.goel@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h       |  4 ++--
>   drivers/gpu/drm/i915/i915_gpu_error.c | 24 ++++++++++++++----------
>   2 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0b5cbe8..33926d9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -546,7 +546,7 @@ struct drm_i915_error_state {
>
>   		struct drm_i915_error_object {
>   			int page_count;
> -			u32 gtt_offset;
> +			u64 gtt_offset;
>   			u32 *pages[0];
>   		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
>
> @@ -572,7 +572,7 @@ struct drm_i915_error_state {
>   		u32 size;
>   		u32 name;
>   		u32 rseqno[I915_NUM_RINGS], wseqno;
> -		u32 gtt_offset;
> +		u64 gtt_offset;
>   		u32 read_domains;
>   		u32 write_domain;
>   		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 6f42569..f79c952 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -197,8 +197,9 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
>   	err_printf(m, "  %s [%d]:\n", name, count);
>
>   	while (count--) {
> -		err_printf(m, "    %08x %8u %02x %02x [ ",
> -			   err->gtt_offset,
> +		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
> +			   upper_32_bits(err->gtt_offset),
> +			   lower_32_bits(err->gtt_offset),
>   			   err->size,
>   			   err->read_domains,
>   			   err->write_domain);
> @@ -426,15 +427,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>   				err_printf(m, " (submitted by %s [%d])",
>   					   error->ring[i].comm,
>   					   error->ring[i].pid);
> -			err_printf(m, " --- gtt_offset = 0x%08x\n",
> -				   obj->gtt_offset);
> +			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
> +				   upper_32_bits(obj->gtt_offset),
> +				   lower_32_bits(obj->gtt_offset));
>   			print_error_obj(m, obj);
>   		}
>
>   		obj = error->ring[i].wa_batchbuffer;
>   		if (obj) {
>   			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
> -				   dev_priv->ring[i].name, obj->gtt_offset);
> +				   dev_priv->ring[i].name,
> +				   lower_32_bits(obj->gtt_offset));
>   			print_error_obj(m, obj);
>   		}
>
> @@ -453,14 +456,14 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>   		if ((obj = error->ring[i].ringbuffer)) {
>   			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
>   				   dev_priv->ring[i].name,
> -				   obj->gtt_offset);
> +				   lower_32_bits(obj->gtt_offset));
>   			print_error_obj(m, obj);
>   		}
>
>   		if ((obj = error->ring[i].hws_page)) {
>   			err_printf(m, "%s --- HW Status = 0x%08x\n",
>   				   dev_priv->ring[i].name,
> -				   obj->gtt_offset);
> +				   lower_32_bits(obj->gtt_offset));
>   			offset = 0;
>   			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
>   				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
> @@ -476,13 +479,14 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>   		if ((obj = error->ring[i].ctx)) {
>   			err_printf(m, "%s --- HW Context = 0x%08x\n",
>   				   dev_priv->ring[i].name,
> -				   obj->gtt_offset);
> +				   lower_32_bits(obj->gtt_offset));
>   			print_error_obj(m, obj);
>   		}
>   	}
>
>   	if ((obj = error->semaphore_obj)) {
> -		err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
> +		err_printf(m, "Semaphore page = 0x%08x\n",
> +			   lower_32_bits(obj->gtt_offset));
>   		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
>   			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
>   				   elt * 4,
> @@ -590,7 +594,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
>   	int num_pages;
>   	bool use_ggtt;
>   	int i = 0;
> -	u32 reloc_offset;
> +	u64 reloc_offset;
>
>   	if (src == NULL || src->pages == NULL)
>   		return NULL;
>
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  reply	other threads:[~2015-07-30  5:09 UTC|newest]

Thread overview: 82+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-29 16:23 [PATCH v6 00/19] 48-bit PPGTT Michel Thierry
2015-07-29 16:23 ` [PATCH v6 01/19] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-30  3:06   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-30  3:18   ` Goel, Akash
2015-08-05 15:31   ` Daniel Vetter
2015-08-05 15:49     ` Michel Thierry
2015-08-05 15:51       ` Michel Thierry
2015-08-06 12:28       ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 03/19] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-30 10:02   ` [PATCH v7 " Michel Thierry
2015-07-31  4:11     ` Goel, Akash
2015-08-05 15:33       ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-30  4:46   ` Goel, Akash
2015-07-30  9:31     ` Michel Thierry
2015-07-30 10:02   ` [PATCH v7 " Michel Thierry
2015-07-31  4:00     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 05/19] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-30  3:48   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure Michel Thierry
2015-07-30  4:01   ` Goel, Akash
2015-07-30  9:31     ` Michel Thierry
2015-07-30 10:04   ` [PATCH v7 " Michel Thierry
2015-07-31  4:35     ` Goel, Akash
2015-07-31 12:12     ` [PATCH v8 " Michel Thierry
2015-07-31 17:35       ` Goel, Akash
2015-08-03  8:34         ` Michel Thierry
2015-08-03  8:52       ` [PATCH v9 " Michel Thierry
2015-08-03  9:20         ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 07/19] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-30 10:05   ` [PATCH v7 " Michel Thierry
2015-07-31  4:20     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-30  4:14   ` Goel, Akash
2015-07-30  9:36     ` Michel Thierry
2015-07-30 10:06   ` [PATCH v7 " Michel Thierry
2015-07-31  4:23     ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 09/19] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-30  4:19   ` Goel, Akash
2015-08-03  8:52   ` [PATCH v9 " Michel Thierry
2015-07-29 16:23 ` [PATCH v6 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-30  4:50   ` Goel, Akash
2015-08-03  8:53   ` [PATCH v9 " Michel Thierry
2015-08-03  9:23     ` Goel, Akash
2015-08-05 15:46     ` Daniel Vetter
2015-08-05 16:13       ` Michel Thierry
2015-07-29 16:23 ` [PATCH v6 11/19] drm/i915/gen8: Initialize PDPs and PML4 Michel Thierry
2015-07-30  4:56   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 12/19] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-30  5:09   ` Goel, Akash [this message]
2015-07-29 16:23 ` [PATCH v6 13/19] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-30  5:20   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 14/19] drm/i915: object size needs to be u64 Michel Thierry
2015-07-30  5:22   ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 15/19] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-30  5:23   ` Goel, Akash
2015-08-05 16:01   ` Daniel Vetter
2015-08-05 16:14     ` Michel Thierry
2015-08-06 12:30       ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 16/19] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-30  5:25   ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-30  5:39   ` Goel, Akash
2015-08-05 15:58   ` Daniel Vetter
2015-08-05 16:14     ` Michel Thierry
2015-08-06 12:47       ` Daniel Vetter
2015-08-06 16:27         ` Michel Thierry
2015-08-07  7:55           ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 18/19] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-30  5:49   ` Goel, Akash
2015-07-30 10:09   ` [PATCH v7 " Michel Thierry
2015-07-31 12:13     ` [PATCH v8 " Michel Thierry
2015-07-31 12:19       ` Chris Wilson
2015-07-31 12:35       ` Michel Thierry
2015-07-31 17:21         ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 19/19] drm/i915: Save some page table setup on repeated binds Michel Thierry
2015-07-30 11:26 ` [PATCH v6 00/19] 48-bit PPGTT Chris Wilson
2015-07-30 11:52   ` Michel Thierry
2015-07-30 12:13     ` Chris Wilson
2015-07-30 19:02     ` Chris Wilson
2015-08-03  9:51 ` Michel Thierry

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