From: "Goel, Akash" <akash.goel@intel.com>
To: Michel Thierry <michel.thierry@intel.com>,
intel-gfx@lists.freedesktop.org, akash.goel@intel.com
Subject: Re: [PATCH v6 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
Date: Thu, 30 Jul 2015 10:16:46 +0530 [thread overview]
Message-ID: <55B9AC36.9010904@intel.com> (raw)
In-Reply-To: <1438187043-34267-5-git-send-email-michel.thierry@intel.com>
On 7/29/2015 9:53 PM, Michel Thierry wrote:
> The insert_entries function was the function used to write PTEs. For the
> PPGTT it was "hardcoded" to only understand two level page tables, which
> was the case for GEN7. We can reuse this for 4 level page tables, and
> remove the concept of insert_entries, which was never viable past 2
> level page tables anyway, but it requires a bit of rework to make the
> function a bit more generic.
>
> This patch begins the generalization work, and it will be heavily used
> upon when the 48b code is complete. The patch series attempts to make
> each function which touches a part of code specific to the page table
> level and here is no exception.
>
> v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
> v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v2)
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 52 +++++++++++++++++++++++++++----------
> 1 file changed, 39 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index bd56979..f338a13 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -600,24 +600,21 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return 0;
> }
>
> -static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
> - uint64_t start,
> - uint64_t length,
> - bool use_scratch)
> +static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
> + struct i915_page_directory_pointer *pdp,
> + uint64_t start,
> + uint64_t length,
> + gen8_pte_t scratch_pte)
> {
> struct i915_hw_ppgtt *ppgtt =
> container_of(vm, struct i915_hw_ppgtt, base);
> - struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
> - gen8_pte_t *pt_vaddr, scratch_pte;
> + gen8_pte_t *pt_vaddr;
> unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
> unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
> unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
> unsigned num_entries = length >> PAGE_SHIFT;
> unsigned last_pte, i;
>
> - scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page),
> - I915_CACHE_LLC, use_scratch);
> -
Sorry for the late comment.
Would it be better to have a WARN_ON check here on NULL value of pdp
pointer, considering the pdp will no longer be static in case of 48 bit.
Actually there are already such checks used in this function for pd, pt
and page pointers.
Best regards
Akash
> while (num_entries) {
> struct i915_page_directory *pd;
> struct i915_page_table *pt;
> @@ -656,14 +653,30 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
> }
> }
>
> -static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
> - struct sg_table *pages,
> - uint64_t start,
> - enum i915_cache_level cache_level, u32 unused)
> +static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
> + uint64_t start,
> + uint64_t length,
> + bool use_scratch)
> {
> struct i915_hw_ppgtt *ppgtt =
> container_of(vm, struct i915_hw_ppgtt, base);
> struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
> +
> + gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
> + I915_CACHE_LLC, use_scratch);
> +
> + gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte);
> +}
> +
> +static void
> +gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
> + struct i915_page_directory_pointer *pdp,
> + struct sg_table *pages,
> + uint64_t start,
> + enum i915_cache_level cache_level)
> +{
> + struct i915_hw_ppgtt *ppgtt =
> + container_of(vm, struct i915_hw_ppgtt, base);
> gen8_pte_t *pt_vaddr;
> unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
> unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
> @@ -700,6 +713,19 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
> kunmap_px(ppgtt, pt_vaddr);
> }
>
> +static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
> + struct sg_table *pages,
> + uint64_t start,
> + enum i915_cache_level cache_level,
> + u32 unused)
> +{
> + struct i915_hw_ppgtt *ppgtt =
> + container_of(vm, struct i915_hw_ppgtt, base);
> + struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
> +
> + gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level);
> +}
> +
> static void gen8_free_page_tables(struct drm_device *dev,
> struct i915_page_directory *pd)
> {
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-07-30 4:46 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-29 16:23 [PATCH v6 00/19] 48-bit PPGTT Michel Thierry
2015-07-29 16:23 ` [PATCH v6 01/19] drm/i915: Remove unnecessary gen8_clamp_pd Michel Thierry
2015-07-30 3:06 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic Michel Thierry
2015-07-30 3:18 ` Goel, Akash
2015-08-05 15:31 ` Daniel Vetter
2015-08-05 15:49 ` Michel Thierry
2015-08-05 15:51 ` Michel Thierry
2015-08-06 12:28 ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 03/19] drm/i915/gen8: Abstract PDP usage Michel Thierry
2015-07-30 10:02 ` [PATCH v7 " Michel Thierry
2015-07-31 4:11 ` Goel, Akash
2015-08-05 15:33 ` Daniel Vetter
2015-07-29 16:23 ` [PATCH v6 04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT Michel Thierry
2015-07-30 4:46 ` Goel, Akash [this message]
2015-07-30 9:31 ` Michel Thierry
2015-07-30 10:02 ` [PATCH v7 " Michel Thierry
2015-07-31 4:00 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 05/19] drm/i915/gen8: Add dynamic page trace events Michel Thierry
2015-07-30 3:48 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure Michel Thierry
2015-07-30 4:01 ` Goel, Akash
2015-07-30 9:31 ` Michel Thierry
2015-07-30 10:04 ` [PATCH v7 " Michel Thierry
2015-07-31 4:35 ` Goel, Akash
2015-07-31 12:12 ` [PATCH v8 " Michel Thierry
2015-07-31 17:35 ` Goel, Akash
2015-08-03 8:34 ` Michel Thierry
2015-08-03 8:52 ` [PATCH v9 " Michel Thierry
2015-08-03 9:20 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 07/19] drm/i915/gen8: implement alloc/free for 4lvl Michel Thierry
2015-07-30 10:05 ` [PATCH v7 " Michel Thierry
2015-07-31 4:20 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc support Michel Thierry
2015-07-30 4:14 ` Goel, Akash
2015-07-30 9:36 ` Michel Thierry
2015-07-30 10:06 ` [PATCH v7 " Michel Thierry
2015-07-31 4:23 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 09/19] drm/i915/gen8: Pass sg_iter through pte inserts Michel Thierry
2015-07-30 4:19 ` Goel, Akash
2015-08-03 8:52 ` [PATCH v9 " Michel Thierry
2015-07-29 16:23 ` [PATCH v6 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range Michel Thierry
2015-07-30 4:50 ` Goel, Akash
2015-08-03 8:53 ` [PATCH v9 " Michel Thierry
2015-08-03 9:23 ` Goel, Akash
2015-08-05 15:46 ` Daniel Vetter
2015-08-05 16:13 ` Michel Thierry
2015-07-29 16:23 ` [PATCH v6 11/19] drm/i915/gen8: Initialize PDPs and PML4 Michel Thierry
2015-07-30 4:56 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 12/19] drm/i915: Expand error state's address width to 64b Michel Thierry
2015-07-30 5:09 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 13/19] drm/i915/gen8: Add ppgtt info and debug_dump Michel Thierry
2015-07-30 5:20 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 14/19] drm/i915: object size needs to be u64 Michel Thierry
2015-07-30 5:22 ` Goel, Akash
2015-07-29 16:23 ` [PATCH v6 15/19] drm/i915: batch_obj vm offset must " Michel Thierry
2015-07-30 5:23 ` Goel, Akash
2015-08-05 16:01 ` Daniel Vetter
2015-08-05 16:14 ` Michel Thierry
2015-08-06 12:30 ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 16/19] drm/i915/userptr: Kill user_size limit check Michel Thierry
2015-07-30 5:25 ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 17/19] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset Michel Thierry
2015-07-30 5:39 ` Goel, Akash
2015-08-05 15:58 ` Daniel Vetter
2015-08-05 16:14 ` Michel Thierry
2015-08-06 12:47 ` Daniel Vetter
2015-08-06 16:27 ` Michel Thierry
2015-08-07 7:55 ` Daniel Vetter
2015-07-29 16:24 ` [PATCH v6 18/19] drm/i915/gen8: Flip the 48b switch Michel Thierry
2015-07-30 5:49 ` Goel, Akash
2015-07-30 10:09 ` [PATCH v7 " Michel Thierry
2015-07-31 12:13 ` [PATCH v8 " Michel Thierry
2015-07-31 12:19 ` Chris Wilson
2015-07-31 12:35 ` Michel Thierry
2015-07-31 17:21 ` Goel, Akash
2015-07-29 16:24 ` [PATCH v6 19/19] drm/i915: Save some page table setup on repeated binds Michel Thierry
2015-07-30 11:26 ` [PATCH v6 00/19] 48-bit PPGTT Chris Wilson
2015-07-30 11:52 ` Michel Thierry
2015-07-30 12:13 ` Chris Wilson
2015-07-30 19:02 ` Chris Wilson
2015-08-03 9:51 ` Michel Thierry
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=55B9AC36.9010904@intel.com \
--to=akash.goel@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=michel.thierry@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.