Re: [PATCH v6 00/19] 48-bit PPGTT

[Michel Thierry <michel.thierry@intel.com>]

On 7/29/2015 5:23 PM, Michel Thierry wrote:
> Michel Thierry (19):
>    drm/i915: Remove unnecessary gen8_clamp_pd
>    drm/i915/gen8: Make pdp allocation more dynamic
>    drm/i915/gen8: Abstract PDP usage
>    drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
>    drm/i915/gen8: Add dynamic page trace events
>    drm/i915/gen8: Add PML4 structure
>    drm/i915/gen8: implement alloc/free for 4lvl
>    drm/i915/gen8: Add 4 level switching infrastructure and lrc support
>    drm/i915/gen8: Pass sg_iter through pte inserts
>    drm/i915/gen8: Add 4 level support in insert_entries and clear_range
>    drm/i915/gen8: Initialize PDPs and PML4
>    drm/i915: Expand error state's address width to 64b
>    drm/i915/gen8: Add ppgtt info and debug_dump
>    drm/i915: object size needs to be u64
>    drm/i915: batch_obj vm offset must be u64
>    drm/i915/userptr: Kill user_size limit check
>    drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
>    drm/i915/gen8: Flip the 48b switch
>    drm/i915: Save some page table setup on repeated binds
>
>   drivers/gpu/drm/i915/i915_debugfs.c        |  18 +-
>   drivers/gpu/drm/i915/i915_drv.h            |  11 +-
>   drivers/gpu/drm/i915/i915_gem.c            |  30 +-
>   drivers/gpu/drm/i915/i915_gem_execbuffer.c |  13 +
>   drivers/gpu/drm/i915/i915_gem_gtt.c        | 665 ++++++++++++++++++++++++-----
>   drivers/gpu/drm/i915/i915_gem_gtt.h        |  64 ++-
>   drivers/gpu/drm/i915/i915_gem_userptr.c    |   4 -
>   drivers/gpu/drm/i915/i915_gpu_error.c      |  24 +-
>   drivers/gpu/drm/i915/i915_params.c         |   2 +-
>   drivers/gpu/drm/i915/i915_reg.h            |   1 +
>   drivers/gpu/drm/i915/i915_trace.h          |  32 +-
>   drivers/gpu/drm/i915/intel_lrc.c           |  60 ++-
>   include/uapi/drm/i915_drm.h                |   3 +-
>   13 files changed, 747 insertions(+), 180 deletions(-)
>
> --
> 2.4.5
>

Hi Daniel,

Finally all the patches have Akash's r-b.
Since there were still some small changes by him and Chris, I addressed 
them individually (instead of resending the whole series one more time).

Below are the msg-id of the last versions of each of them, in case there 
are some doubts about which patches to merge.

Note, the last patch (drm/i915: Save some page table setup on repeated 
binds) is an optimization Akash recommended. That's why he didn't review 
it. Do you have someone in mind to check it? Or should I ask around for 
volunteers?

Thanks,

-Michel

[01/19] drm/i915: Remove unnecessary gen8_clamp_pd
1438187043-34267-2-git-send-email-michel.thierry@intel.com

[02/19] drm/i915/gen8: Make pdp allocation more dynamic
1438187043-34267-3-git-send-email-michel.thierry@intel.com

[03/19] drm/i915/gen8: Abstract PDP usage
1438250523-22533-1-git-send-email-michel.thierry@intel.com

[04/19] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
1438250569-22618-1-git-send-email-michel.thierry@intel.com

[05/19] drm/i915/gen8: Add dynamic page trace events
1438187043-34267-6-git-send-email-michel.thierry@intel.com

[06/19] drm/i915/gen8: Add PML4 structure
1438591921-3087-1-git-send-email-michel.thierry@intel.com

[07/19] drm/i915/gen8: implement alloc/free for 4lvl
1438250729-22955-1-git-send-email-michel.thierry@intel.com

[08/19] drm/i915/gen8: Add 4 level switching infrastructure and lrc
support
1438250783-23118-1-git-send-email-michel.thierry@intel.com

[09/19] drm/i915/gen8: Pass sg_iter through pte inserts
1438591967-3249-1-git-send-email-michel.thierry@intel.com

[10/19] drm/i915/gen8: Add 4 level support in insert_entries and
clear_range
1438592007-3354-1-git-send-email-michel.thierry@intel.com

[11/19] drm/i915/gen8: Initialize PDPs and PML4
1438187043-34267-12-git-send-email-michel.thierry@intel.com

[12/19] drm/i915: Expand error state's address width to 64b
1438187043-34267-13-git-send-email-michel.thierry@intel.com

[13/19] drm/i915/gen8: Add ppgtt info and debug_dump
1438187043-34267-14-git-send-email-michel.thierry@intel.com

[14/19] drm/i915: object size needs to be u64
1438187043-34267-15-git-send-email-michel.thierry@intel.com

[15/19] drm/i915: batch_obj vm offset must be u64
1438187043-34267-16-git-send-email-michel.thierry@intel.com

[16/19] drm/i915/userptr: Kill user_size limit check
1438187043-34267-17-git-send-email-michel.thierry@intel.com

[17/19] drm/i915: Wa32bitGeneralStateOffset &
Wa32bitInstructionBaseOffset
1438187043-34267-18-git-send-email-michel.thierry@intel.com

[18/19] drm/i915/gen8: Flip the 48b switch
1438346110-18985-1-git-send-email-michel.thierry@intel.com

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