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From: ddaney@caviumnetworks.com (David Daney)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154
Date: Mon, 17 Aug 2015 10:00:53 -0700	[thread overview]
Message-ID: <55D21345.3040903@caviumnetworks.com> (raw)
In-Reply-To: <1439576885-15621-3-git-send-email-rric@kernel.org>

On 08/14/2015 11:28 AM, Robert Richter wrote:
> From: Robert Richter <rrichter@cavium.com>
>
> This patch implements Cavium ThunderX erratum 23154.
>
> The gicv3 of ThunderX requires a modified version for reading the IAR
> status to ensure data synchronization. Since this is in the fast-path
> and called with each interrupt, runtime patching is used using jump
> label patching for smallest overhead (no-op). This is the same
> technique as used for tracepoints.
>
> v4:
>   * simplify code to only use cpus_have_cap() in gicv3_enable_quirks()
>
> v3:
>   * fix erratum to be dependend from midr
>   * use arm64 errata framework
>
> v2:
>   * implement code in a single asm() to keep instruction sequence
>   * added comment to the code that explains the erratum
>   * apply workaround also if running as guest, thus check MIDR
>
> Signed-off-by: Robert Richter <rrichter@cavium.com>
> ---
>   arch/arm64/Kconfig                  | 11 ++++++++++
>   arch/arm64/include/asm/cpufeature.h |  3 ++-
>   arch/arm64/include/asm/cputype.h    | 18 +++++++++-------
>   arch/arm64/kernel/cpu_errata.c      |  9 ++++++++
>   drivers/irqchip/irq-gic-v3.c        | 42 ++++++++++++++++++++++++++++++++++++-
>   5 files changed, 74 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 0f6edb14b7e4..4f866a4c6536 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -417,6 +417,17 @@ config ARM64_ERRATUM_845719
>
>   	  If unsure, say Y.
>
> +config CAVIUM_ERRATUM_23154
> +	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
> +	depends on ARCH_THUNDER

None of the other errata depend on a specific ARCH_*.  I think we should 
remove this 'depends on', so that a generic kernel can be configured to 
work on Thunder without having to first select ARCH_THUNDER.

David Daney


> +	default y
> +	help
> +	  The gicv3 of ThunderX requires a modified version for
> +	  reading the IAR status to ensure data synchronization
> +	  (access to icc_iar1_el1 is not sync'ed before and after).
> +
> +	  If unsure, say Y.
> +
>   endmenu
>
>
>

WARNING: multiple messages have this Message-ID (diff)
From: David Daney <ddaney@caviumnetworks.com>
To: Robert Richter <rric@kernel.org>
Cc: Marc Zygnier <marc.zyngier@arm.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	Robert Richter <rrichter@cavium.com>,
	Tirumalesh Chalamarla <tchalamarla@cavium.com>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154
Date: Mon, 17 Aug 2015 10:00:53 -0700	[thread overview]
Message-ID: <55D21345.3040903@caviumnetworks.com> (raw)
In-Reply-To: <1439576885-15621-3-git-send-email-rric@kernel.org>

On 08/14/2015 11:28 AM, Robert Richter wrote:
> From: Robert Richter <rrichter@cavium.com>
>
> This patch implements Cavium ThunderX erratum 23154.
>
> The gicv3 of ThunderX requires a modified version for reading the IAR
> status to ensure data synchronization. Since this is in the fast-path
> and called with each interrupt, runtime patching is used using jump
> label patching for smallest overhead (no-op). This is the same
> technique as used for tracepoints.
>
> v4:
>   * simplify code to only use cpus_have_cap() in gicv3_enable_quirks()
>
> v3:
>   * fix erratum to be dependend from midr
>   * use arm64 errata framework
>
> v2:
>   * implement code in a single asm() to keep instruction sequence
>   * added comment to the code that explains the erratum
>   * apply workaround also if running as guest, thus check MIDR
>
> Signed-off-by: Robert Richter <rrichter@cavium.com>
> ---
>   arch/arm64/Kconfig                  | 11 ++++++++++
>   arch/arm64/include/asm/cpufeature.h |  3 ++-
>   arch/arm64/include/asm/cputype.h    | 18 +++++++++-------
>   arch/arm64/kernel/cpu_errata.c      |  9 ++++++++
>   drivers/irqchip/irq-gic-v3.c        | 42 ++++++++++++++++++++++++++++++++++++-
>   5 files changed, 74 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 0f6edb14b7e4..4f866a4c6536 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -417,6 +417,17 @@ config ARM64_ERRATUM_845719
>
>   	  If unsure, say Y.
>
> +config CAVIUM_ERRATUM_23154
> +	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
> +	depends on ARCH_THUNDER

None of the other errata depend on a specific ARCH_*.  I think we should 
remove this 'depends on', so that a generic kernel can be configured to 
work on Thunder without having to first select ARCH_THUNDER.

David Daney


> +	default y
> +	help
> +	  The gicv3 of ThunderX requires a modified version for
> +	  reading the IAR status to ensure data synchronization
> +	  (access to icc_iar1_el1 is not sync'ed before and after).
> +
> +	  If unsure, say Y.
> +
>   endmenu
>
>
>

  parent reply	other threads:[~2015-08-17 17:00 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-08-14 18:28 [PATCH v4 0/5] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Robert Richter
2015-08-14 18:28 ` Robert Richter
2015-08-14 18:28 ` [PATCH v4 1/5] irqchip, gicv3-its: Add range check for number of allocated pages Robert Richter
2015-08-14 18:28   ` Robert Richter
2015-08-14 18:28 ` [PATCH v4 2/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 Robert Richter
2015-08-14 18:28   ` Robert Richter
2015-08-17 16:40   ` Catalin Marinas
2015-08-17 16:40     ` Catalin Marinas
2015-08-19 15:43     ` Robert Richter
2015-08-19 15:43       ` Robert Richter
2015-08-17 17:00   ` David Daney [this message]
2015-08-17 17:00     ` David Daney
2015-08-19 16:05     ` Robert Richter
2015-08-19 16:05       ` Robert Richter
2015-09-07 16:54   ` Suzuki K. Poulose
2015-09-07 16:54     ` Suzuki K. Poulose
2015-09-07 17:09     ` Marc Zyngier
2015-09-07 17:09       ` Marc Zyngier
2015-09-07 17:32       ` Robert Richter
2015-09-07 17:32         ` Robert Richter
2015-09-07 17:15     ` Catalin Marinas
2015-09-07 17:15       ` Catalin Marinas
2015-09-07 17:41       ` Suzuki K. Poulose
2015-09-07 17:41         ` Suzuki K. Poulose
2015-09-08  9:00         ` Catalin Marinas
2015-09-08  9:00           ` Catalin Marinas
2015-09-08  9:09           ` Suzuki K. Poulose
2015-09-08  9:09             ` Suzuki K. Poulose
2015-09-08  9:37             ` Catalin Marinas
2015-09-08  9:37               ` Catalin Marinas
2015-09-08 10:30               ` Suzuki K. Poulose
2015-09-08 10:30                 ` Suzuki K. Poulose
2015-08-14 18:28 ` [PATCH v4 3/5] irqchip, gicv3-its: Read typer register outside the loop Robert Richter
2015-08-14 18:28   ` Robert Richter
2015-08-14 18:28 ` [PATCH v4 4/5] irqchip, gicv3-its: Add HW revision detection and configuration Robert Richter
2015-08-14 18:28   ` Robert Richter
2015-09-07 16:26   ` Marc Zyngier
2015-09-07 16:26     ` Marc Zyngier
2015-08-14 18:28 ` [PATCH v4 5/5] irqchip, gicv3-its: Workaround for Cavium ThunderX errata 22375, 24313 Robert Richter
2015-08-14 18:28   ` Robert Richter
2015-09-07 16:32   ` Marc Zyngier
2015-09-07 16:32     ` Marc Zyngier
2015-09-18  8:33     ` Robert Richter
2015-09-18  8:33       ` Robert Richter
2015-09-07 16:35 ` [PATCH v4 0/5] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Marc Zyngier
2015-09-07 16:35   ` Marc Zyngier

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