[PATCH v4 0/6] drm/rockchip: fixes and new features

[PATCH v4 0/6] drm/rockchip: fixes and new features

[Mark Yao]

This series patches are used for yuv image overlay display.

Rockchip vop support NV11, NV16, NV24 yuv format,
and can scale the image scale 1/8 to 8.

Changes in v4:
- rebase to top of drm-next, fix conflict
- tiny fix on plane scale.

Changes in v3:
- make code more readable
- fix some bugs

Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image. 
- Fix scale dest info. 
Mark Yao (6):
  drm/rockchip: vop: Fix virtual stride calculation
  drm/rockchip: vop: Fix window dest start point
  drm/rockchip: vop: Add yuv plane support
  drm/rockchip: vop: Default enable win2/3 area0 bit
  drm/rockchip: vop: restore vop registers when resume
  drm/rockchip: vop: support plane scale

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  269 ++++++++++++++++++++++++++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 +++++++++
 2 files changed, 348 insertions(+), 9 deletions(-)

-- 
1.7.9.5


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[PATCH v4 0/6] drm/rockchip: fixes and new features

[Mark Yao]

This series patches are used for yuv image overlay display.

Rockchip vop support NV11, NV16, NV24 yuv format,
and can scale the image scale 1/8 to 8.

Changes in v4:
- rebase to top of drm-next, fix conflict
- tiny fix on plane scale.

Changes in v3:
- make code more readable
- fix some bugs

Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image. 
- Fix scale dest info. 
Mark Yao (6):
  drm/rockchip: vop: Fix virtual stride calculation
  drm/rockchip: vop: Fix window dest start point
  drm/rockchip: vop: Add yuv plane support
  drm/rockchip: vop: Default enable win2/3 area0 bit
  drm/rockchip: vop: restore vop registers when resume
  drm/rockchip: vop: support plane scale

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  269 ++++++++++++++++++++++++++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 +++++++++
 2 files changed, 348 insertions(+), 9 deletions(-)

-- 
1.7.9.5

[PATCH v4 1/6] drm/rockchip: vop: Fix virtual stride calculation

[Mark Yao]

vir_stride need number words of the virtual width, and fb->pitches
save bytes_per_pixel, so just div 4 switch to stride.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

Changes in v3:
Adviced by Tomasz Figa
- use more suitable tile for this patch. 

Changes in v2: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..6b44731 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -667,7 +667,7 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	offset += (src.y1 >> 16) * fb->pitches[0];
 	yrgb_mst = rk_obj->dma_addr + offset;
 
-	y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
+	y_vir_stride = fb->pitches[0] >> 2;
 
 	/*
 	 * If this plane update changes the plane's framebuffer, (or more
-- 
1.7.9.5


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[PATCH v4 1/6] drm/rockchip: vop: Fix virtual stride calculation

[Mark Yao]

vir_stride need number words of the virtual width, and fb->pitches
save bytes_per_pixel, so just div 4 switch to stride.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

Changes in v3:
Adviced by Tomasz Figa
- use more suitable tile for this patch. 

Changes in v2: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 34b78e7..6b44731 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -667,7 +667,7 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	offset += (src.y1 >> 16) * fb->pitches[0];
 	yrgb_mst = rk_obj->dma_addr + offset;
 
-	y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
+	y_vir_stride = fb->pitches[0] >> 2;
 
 	/*
 	 * If this plane update changes the plane's framebuffer, (or more
-- 
1.7.9.5

[PATCH v4 2/6] drm/rockchip: vop: Fix window dest start point

[Mark Yao]

Dest start point use crtc_x/y is wrong, crtc_x/y is not equal
to dest.x1/y1 at plane scale.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 6b44731..da72de9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -657,11 +657,9 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	actual_w = (src.x2 - src.x1) >> 16;
 	actual_h = (src.y2 - src.y1) >> 16;
-	crtc_x = max(0, crtc_x);
-	crtc_y = max(0, crtc_y);
 
-	dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
-	dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
+	dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+	dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 
 	offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 	offset += (src.y1 >> 16) * fb->pitches[0];
-- 
1.7.9.5


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[PATCH v4 2/6] drm/rockchip: vop: Fix window dest start point

[Mark Yao]

Dest start point use crtc_x/y is wrong, crtc_x/y is not equal
to dest.x1/y1 at plane scale.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 6b44731..da72de9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -657,11 +657,9 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	actual_w = (src.x2 - src.x1) >> 16;
 	actual_h = (src.y2 - src.y1) >> 16;
-	crtc_x = max(0, crtc_x);
-	crtc_y = max(0, crtc_y);
 
-	dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
-	dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
+	dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+	dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 
 	offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 	offset += (src.y1 >> 16) * fb->pitches[0];
-- 
1.7.9.5

[PATCH v4 3/6] drm/rockchip: vop: Add yuv plane support

[Mark Yao]

vop support yuv with NV12, NV16 and NV24, only 2 plane yuv.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: rebase to drm-next, fix conflict

Changes in v3:
Adviced by Tomasz Figa
- separate dest calculate to another patch
- fix src x1,x2 when do align, and remove unnecessary src.y1 align.

Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image.  

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   56 ++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index da72de9..c1264d5 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -393,6 +393,18 @@ static enum vop_data_format vop_convert_format(uint32_t format)
 	}
 }
 
+static bool is_yuv_support(uint32_t format)
+{
+	switch (format) {
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV16:
+	case DRM_FORMAT_NV24:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool is_alpha_support(uint32_t format)
 {
 	switch (format) {
@@ -598,17 +610,22 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	struct vop *vop = to_vop(crtc);
 	struct drm_gem_object *obj;
 	struct rockchip_gem_object *rk_obj;
+	struct drm_gem_object *uv_obj;
+	struct rockchip_gem_object *rk_uv_obj;
 	unsigned long offset;
 	unsigned int actual_w;
 	unsigned int actual_h;
 	unsigned int dsp_stx;
 	unsigned int dsp_sty;
 	unsigned int y_vir_stride;
+	unsigned int uv_vir_stride = 0;
 	dma_addr_t yrgb_mst;
+	dma_addr_t uv_mst = 0;
 	enum vop_data_format format;
 	uint32_t val;
 	bool is_alpha;
 	bool rb_swap;
+	bool is_yuv;
 	bool visible;
 	int ret;
 	struct drm_rect dest = {
@@ -643,6 +660,8 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	is_alpha = is_alpha_support(fb->pixel_format);
 	rb_swap = has_rb_swapped(fb->pixel_format);
+	is_yuv = is_yuv_support(fb->pixel_format);
+
 	format = vop_convert_format(fb->pixel_format);
 	if (format < 0)
 		return format;
@@ -655,18 +674,47 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	rk_obj = to_rockchip_obj(obj);
 
+	if (is_yuv) {
+		/*
+		 * Src.x1 can be odd when do clip, but yuv plane start point
+		 * need align with 2 pixel.
+		 */
+		val = (src.x1 >> 16) % 2;
+		src.x1 += val << 16;
+		src.x2 += val << 16;
+	}
+
 	actual_w = (src.x2 - src.x1) >> 16;
 	actual_h = (src.y2 - src.y1) >> 16;
 
 	dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 	dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 
-	offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
+	offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 	offset += (src.y1 >> 16) * fb->pitches[0];
-	yrgb_mst = rk_obj->dma_addr + offset;
 
+	yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 	y_vir_stride = fb->pitches[0] >> 2;
 
+	if (is_yuv) {
+		int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+		int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
+		int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+
+		uv_obj = rockchip_fb_get_gem_obj(fb, 1);
+		if (!uv_obj) {
+			DRM_ERROR("fail to get uv object from framebuffer\n");
+			return -EINVAL;
+		}
+		rk_uv_obj = to_rockchip_obj(uv_obj);
+		uv_vir_stride = fb->pitches[1] >> 2;
+
+		offset = (src.x1 >> 16) * bpp / hsub;
+		offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
+
+		uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
+	}
+
 	/*
 	 * If this plane update changes the plane's framebuffer, (or more
 	 * precisely, if this update has a different framebuffer than the last
@@ -702,6 +750,10 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	VOP_WIN_SET(vop, win, format, format);
 	VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 	VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
+	if (is_yuv) {
+		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
+		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
+	}
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
-- 
1.7.9.5


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[PATCH v4 3/6] drm/rockchip: vop: Add yuv plane support

[Mark Yao]

vop support yuv with NV12, NV16 and NV24, only 2 plane yuv.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: rebase to drm-next, fix conflict

Changes in v3:
Adviced by Tomasz Figa
- separate dest calculate to another patch
- fix src x1,x2 when do align, and remove unnecessary src.y1 align.

Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image.  

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   56 ++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index da72de9..c1264d5 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -393,6 +393,18 @@ static enum vop_data_format vop_convert_format(uint32_t format)
 	}
 }
 
+static bool is_yuv_support(uint32_t format)
+{
+	switch (format) {
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV16:
+	case DRM_FORMAT_NV24:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool is_alpha_support(uint32_t format)
 {
 	switch (format) {
@@ -598,17 +610,22 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	struct vop *vop = to_vop(crtc);
 	struct drm_gem_object *obj;
 	struct rockchip_gem_object *rk_obj;
+	struct drm_gem_object *uv_obj;
+	struct rockchip_gem_object *rk_uv_obj;
 	unsigned long offset;
 	unsigned int actual_w;
 	unsigned int actual_h;
 	unsigned int dsp_stx;
 	unsigned int dsp_sty;
 	unsigned int y_vir_stride;
+	unsigned int uv_vir_stride = 0;
 	dma_addr_t yrgb_mst;
+	dma_addr_t uv_mst = 0;
 	enum vop_data_format format;
 	uint32_t val;
 	bool is_alpha;
 	bool rb_swap;
+	bool is_yuv;
 	bool visible;
 	int ret;
 	struct drm_rect dest = {
@@ -643,6 +660,8 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	is_alpha = is_alpha_support(fb->pixel_format);
 	rb_swap = has_rb_swapped(fb->pixel_format);
+	is_yuv = is_yuv_support(fb->pixel_format);
+
 	format = vop_convert_format(fb->pixel_format);
 	if (format < 0)
 		return format;
@@ -655,18 +674,47 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	rk_obj = to_rockchip_obj(obj);
 
+	if (is_yuv) {
+		/*
+		 * Src.x1 can be odd when do clip, but yuv plane start point
+		 * need align with 2 pixel.
+		 */
+		val = (src.x1 >> 16) % 2;
+		src.x1 += val << 16;
+		src.x2 += val << 16;
+	}
+
 	actual_w = (src.x2 - src.x1) >> 16;
 	actual_h = (src.y2 - src.y1) >> 16;
 
 	dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 	dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 
-	offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
+	offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 	offset += (src.y1 >> 16) * fb->pitches[0];
-	yrgb_mst = rk_obj->dma_addr + offset;
 
+	yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 	y_vir_stride = fb->pitches[0] >> 2;
 
+	if (is_yuv) {
+		int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+		int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
+		int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+
+		uv_obj = rockchip_fb_get_gem_obj(fb, 1);
+		if (!uv_obj) {
+			DRM_ERROR("fail to get uv object from framebuffer\n");
+			return -EINVAL;
+		}
+		rk_uv_obj = to_rockchip_obj(uv_obj);
+		uv_vir_stride = fb->pitches[1] >> 2;
+
+		offset = (src.x1 >> 16) * bpp / hsub;
+		offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
+
+		uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
+	}
+
 	/*
 	 * If this plane update changes the plane's framebuffer, (or more
 	 * precisely, if this update has a different framebuffer than the last
@@ -702,6 +750,10 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	VOP_WIN_SET(vop, win, format, format);
 	VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 	VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
+	if (is_yuv) {
+		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
+		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
+	}
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
-- 
1.7.9.5

[PATCH v4 3/6] drm/rockchip: vop: Add yuv plane support

[Mark Yao]

vop support yuv with NV12, NV16 and NV24, only 2 plane yuv.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: rebase to drm-next, fix conflict

Changes in v3:
Adviced by Tomasz Figa
- separate dest calculate to another patch
- fix src x1,x2 when do align, and remove unnecessary src.y1 align.

Changes in v2:
- Uv buffer not support odd offset, align it.
- Fix error display when move yuv image.  

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   56 ++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index da72de9..c1264d5 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -393,6 +393,18 @@ static enum vop_data_format vop_convert_format(uint32_t format)
 	}
 }
 
+static bool is_yuv_support(uint32_t format)
+{
+	switch (format) {
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_NV16:
+	case DRM_FORMAT_NV24:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool is_alpha_support(uint32_t format)
 {
 	switch (format) {
@@ -598,17 +610,22 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	struct vop *vop = to_vop(crtc);
 	struct drm_gem_object *obj;
 	struct rockchip_gem_object *rk_obj;
+	struct drm_gem_object *uv_obj;
+	struct rockchip_gem_object *rk_uv_obj;
 	unsigned long offset;
 	unsigned int actual_w;
 	unsigned int actual_h;
 	unsigned int dsp_stx;
 	unsigned int dsp_sty;
 	unsigned int y_vir_stride;
+	unsigned int uv_vir_stride = 0;
 	dma_addr_t yrgb_mst;
+	dma_addr_t uv_mst = 0;
 	enum vop_data_format format;
 	uint32_t val;
 	bool is_alpha;
 	bool rb_swap;
+	bool is_yuv;
 	bool visible;
 	int ret;
 	struct drm_rect dest = {
@@ -643,6 +660,8 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	is_alpha = is_alpha_support(fb->pixel_format);
 	rb_swap = has_rb_swapped(fb->pixel_format);
+	is_yuv = is_yuv_support(fb->pixel_format);
+
 	format = vop_convert_format(fb->pixel_format);
 	if (format < 0)
 		return format;
@@ -655,18 +674,47 @@ static int vop_update_plane_event(struct drm_plane *plane,
 
 	rk_obj = to_rockchip_obj(obj);
 
+	if (is_yuv) {
+		/*
+		 * Src.x1 can be odd when do clip, but yuv plane start point
+		 * need align with 2 pixel.
+		 */
+		val = (src.x1 >> 16) % 2;
+		src.x1 += val << 16;
+		src.x2 += val << 16;
+	}
+
 	actual_w = (src.x2 - src.x1) >> 16;
 	actual_h = (src.y2 - src.y1) >> 16;
 
 	dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 	dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 
-	offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
+	offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 	offset += (src.y1 >> 16) * fb->pitches[0];
-	yrgb_mst = rk_obj->dma_addr + offset;
 
+	yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 	y_vir_stride = fb->pitches[0] >> 2;
 
+	if (is_yuv) {
+		int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+		int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
+		int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+
+		uv_obj = rockchip_fb_get_gem_obj(fb, 1);
+		if (!uv_obj) {
+			DRM_ERROR("fail to get uv object from framebuffer\n");
+			return -EINVAL;
+		}
+		rk_uv_obj = to_rockchip_obj(uv_obj);
+		uv_vir_stride = fb->pitches[1] >> 2;
+
+		offset = (src.x1 >> 16) * bpp / hsub;
+		offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
+
+		uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
+	}
+
 	/*
 	 * If this plane update changes the plane's framebuffer, (or more
 	 * precisely, if this update has a different framebuffer than the last
@@ -702,6 +750,10 @@ static int vop_update_plane_event(struct drm_plane *plane,
 	VOP_WIN_SET(vop, win, format, format);
 	VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 	VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
+	if (is_yuv) {
+		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
+		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
+	}
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
-- 
1.7.9.5

[PATCH v4 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit

[Mark Yao]

Win2/3 support multiple area function, but we haven't found
a suitable way to use it yet, so let's just use them as other windows
with only area 0 enabled.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

Changes in v3:
Adviced by Tomasz Figa
- fix patch comments.
Changes in v2: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c1264d5..4a2923b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -279,6 +279,12 @@ static const struct vop_reg_data vop_init_reg_table[] = {
 	{DSP_CTRL0, 0x00000000},
 	{WIN0_CTRL0, 0x00000080},
 	{WIN1_CTRL0, 0x00000080},
+	/* TODO: Win2/3 support multiple area function, but we haven't found
+	 * a suitable way to use it yet, so let's just use them as other windows
+	 * with only area 0 enabled.
+	 */
+	{WIN2_CTRL0, 0x00000010},
+	{WIN3_CTRL0, 0x00000010},
 };
 
 /*
-- 
1.7.9.5


_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v4 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit

[Mark Yao]

Win2/3 support multiple area function, but we haven't found
a suitable way to use it yet, so let's just use them as other windows
with only area 0 enabled.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

Changes in v3:
Adviced by Tomasz Figa
- fix patch comments.
Changes in v2: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c1264d5..4a2923b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -279,6 +279,12 @@ static const struct vop_reg_data vop_init_reg_table[] = {
 	{DSP_CTRL0, 0x00000000},
 	{WIN0_CTRL0, 0x00000080},
 	{WIN1_CTRL0, 0x00000080},
+	/* TODO: Win2/3 support multiple area function, but we haven't found
+	 * a suitable way to use it yet, so let's just use them as other windows
+	 * with only area 0 enabled.
+	 */
+	{WIN2_CTRL0, 0x00000010},
+	{WIN3_CTRL0, 0x00000010},
 };
 
 /*
-- 
1.7.9.5

[PATCH v4 4/6] drm/rockchip: vop: Default enable win2/3 area0 bit

[Mark Yao]

Win2/3 support multiple area function, but we haven't found
a suitable way to use it yet, so let's just use them as other windows
with only area 0 enabled.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

Changes in v3:
Adviced by Tomasz Figa
- fix patch comments.
Changes in v2: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c1264d5..4a2923b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -279,6 +279,12 @@ static const struct vop_reg_data vop_init_reg_table[] = {
 	{DSP_CTRL0, 0x00000000},
 	{WIN0_CTRL0, 0x00000080},
 	{WIN1_CTRL0, 0x00000080},
+	/* TODO: Win2/3 support multiple area function, but we haven't found
+	 * a suitable way to use it yet, so let's just use them as other windows
+	 * with only area 0 enabled.
+	 */
+	{WIN2_CTRL0, 0x00000010},
+	{WIN3_CTRL0, 0x00000010},
 };
 
 /*
-- 
1.7.9.5

[PATCH v4 5/6] drm/rockchip: vop: restore vop registers when resume

[Mark Yao]

The registers will be reset to default values when whole
power domain off, so restore registers from regsbak.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4a2923b..16b7d98 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -496,6 +496,7 @@ static void vop_enable(struct drm_crtc *crtc)
 		goto err_disable_aclk;
 	}
 
+	memcpy(vop->regs, vop->regsbak, vop->len);
 	/*
 	 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 	 */
-- 
1.7.9.5


_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v4 5/6] drm/rockchip: vop: restore vop registers when resume

[Mark Yao]

The registers will be reset to default values when whole
power domain off, so restore registers from regsbak.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4a2923b..16b7d98 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -496,6 +496,7 @@ static void vop_enable(struct drm_crtc *crtc)
 		goto err_disable_aclk;
 	}
 
+	memcpy(vop->regs, vop->regsbak, vop->len);
 	/*
 	 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 	 */
-- 
1.7.9.5

[PATCH v4 5/6] drm/rockchip: vop: restore vop registers when resume

[Mark Yao]

The registers will be reset to default values when whole
power domain off, so restore registers from regsbak.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: None

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 4a2923b..16b7d98 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -496,6 +496,7 @@ static void vop_enable(struct drm_crtc *crtc)
 		goto err_disable_aclk;
 	}
 
+	memcpy(vop->regs, vop->regsbak, vop->len);
 	/*
 	 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 	 */
-- 
1.7.9.5

[PATCH v4 6/6] drm/rockchip: vop: support plane scale

[Mark Yao]

Win_full support 1/8 to 8 scale down/up engine, support
all format scale.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: 
Adviced by Tomasz Figa
- calcaute min/max scale with readable macro.

Changes in v3:
Adviced by Tomasz Figa
- remove unused code and unnecessary scale path.
- use static inline funcion instead "#define", let gcc check the cast
- move same call into helper, make code clean.

Changes in v2:
- Fix scale dest info. 
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  198 ++++++++++++++++++++++++++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 ++++++++++++
 2 files changed, 284 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 16b7d98..5d8ae5e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -50,6 +50,8 @@
 
 #define VOP_WIN_SET(x, win, name, v) \
 		REG_SET(x, win->base, win->phy->name, v, RELAXED)
+#define VOP_SCL_SET(x, win, name, v) \
+		REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
 #define VOP_CTRL_SET(x, name, v) \
 		REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
 
@@ -164,7 +166,37 @@ struct vop_ctrl {
 	struct vop_reg vpost_st_end;
 };
 
+struct vop_scl_regs {
+	struct vop_reg cbcr_vsd_mode;
+	struct vop_reg cbcr_vsu_mode;
+	struct vop_reg cbcr_hsd_mode;
+	struct vop_reg cbcr_ver_scl_mode;
+	struct vop_reg cbcr_hor_scl_mode;
+	struct vop_reg yrgb_vsd_mode;
+	struct vop_reg yrgb_vsu_mode;
+	struct vop_reg yrgb_hsd_mode;
+	struct vop_reg yrgb_ver_scl_mode;
+	struct vop_reg yrgb_hor_scl_mode;
+	struct vop_reg line_load_mode;
+	struct vop_reg cbcr_axi_gather_num;
+	struct vop_reg yrgb_axi_gather_num;
+	struct vop_reg vsd_cbcr_gt2;
+	struct vop_reg vsd_cbcr_gt4;
+	struct vop_reg vsd_yrgb_gt2;
+	struct vop_reg vsd_yrgb_gt4;
+	struct vop_reg bic_coe_sel;
+	struct vop_reg cbcr_axi_gather_en;
+	struct vop_reg yrgb_axi_gather_en;
+
+	struct vop_reg lb_mode;
+	struct vop_reg scale_yrgb_x;
+	struct vop_reg scale_yrgb_y;
+	struct vop_reg scale_cbcr_x;
+	struct vop_reg scale_cbcr_y;
+};
+
 struct vop_win_phy {
+	const struct vop_scl_regs *scl;
 	const uint32_t *data_formats;
 	uint32_t nformats;
 
@@ -222,7 +254,36 @@ static const uint32_t formats_234[] = {
 	DRM_FORMAT_BGR565,
 };
 
+static const struct vop_scl_regs win_full_scl = {
+	.cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
+	.cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
+	.cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
+	.cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
+	.cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
+	.yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
+	.yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
+	.yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
+	.yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
+	.yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
+	.line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
+	.cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
+	.yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
+	.vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
+	.vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
+	.vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
+	.vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
+	.bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
+	.cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
+	.yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
+	.lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
+	.scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+	.scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+	.scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+	.scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
 static const struct vop_win_phy win01_data = {
+	.scl = &win_full_scl,
 	.data_formats = formats_01,
 	.nformats = ARRAY_SIZE(formats_01),
 	.enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
@@ -422,6 +483,126 @@ static bool is_alpha_support(uint32_t format)
 	}
 }
 
+static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
+				  uint32_t dst, bool is_horizontal,
+				  int vsu_mode, int *vskiplines)
+{
+	uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
+
+	if (is_horizontal) {
+		if (mode == SCALE_UP)
+			val = GET_SCL_FT_BIC(src, dst);
+		else if (mode == SCALE_DOWN)
+			val = GET_SCL_FT_BILI_DN(src, dst);
+	} else {
+		if (mode == SCALE_UP) {
+			if (vsu_mode == SCALE_UP_BIL)
+				val = GET_SCL_FT_BILI_UP(src, dst);
+			else
+				val = GET_SCL_FT_BIC(src, dst);
+		} else if (mode == SCALE_DOWN) {
+			if (vskiplines) {
+				*vskiplines = scl_get_vskiplines(src, dst);
+				val = scl_get_bili_dn_vskip(src, dst,
+							    *vskiplines);
+			} else {
+				val = GET_SCL_FT_BILI_DN(src, dst);
+			}
+		}
+	}
+
+	return val;
+}
+
+static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
+			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
+			     uint32_t dst_h, uint32_t pixel_format)
+{
+	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
+	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
+	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
+	int hsub = drm_format_horz_chroma_subsampling(pixel_format);
+	int vsub = drm_format_vert_chroma_subsampling(pixel_format);
+	bool is_yuv = is_yuv_support(pixel_format);
+	uint16_t cbcr_src_w = src_w / hsub;
+	uint16_t cbcr_src_h = src_h / vsub;
+	uint16_t vsu_mode;
+	uint16_t lb_mode;
+	uint32_t val;
+	int vskiplines;
+
+	if (dst_w > 3840) {
+		DRM_ERROR("Maximum destination width (3840) exceeded\n");
+		return;
+	}
+
+	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
+	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
+
+	if (is_yuv) {
+		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
+		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
+		if (cbcr_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, true);
+		else
+			lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
+	} else {
+		if (yrgb_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, false);
+		else
+			lb_mode = scl_vop_cal_lb_mode(src_w, false);
+	}
+
+	VOP_SCL_SET(vop, win, lb_mode, lb_mode);
+	if (lb_mode == LB_RGB_3840X2) {
+		if (yrgb_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow yrgb ver scale\n");
+			return;
+		}
+		if (cbcr_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow cbcr ver scale\n");
+			return;
+		}
+		vsu_mode = SCALE_UP_BIL;
+	} else if (lb_mode == LB_RGB_2560X4) {
+		vsu_mode = SCALE_UP_BIL;
+	} else {
+		vsu_mode = SCALE_UP_BIC;
+	}
+
+	val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
+				true, 0, NULL);
+	VOP_SCL_SET(vop, win, scale_yrgb_x, val);
+	val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
+				false, vsu_mode, &vskiplines);
+	VOP_SCL_SET(vop, win, scale_yrgb_y, val);
+
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
+
+	VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
+	if (is_yuv) {
+		val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
+					dst_w, true, 0, NULL);
+		VOP_SCL_SET(vop, win, scale_cbcr_x, val);
+		val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
+					dst_h, false, vsu_mode, &vskiplines);
+		VOP_SCL_SET(vop, win, scale_cbcr_y, val);
+
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
+		VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
+	}
+}
+
 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 {
 	unsigned long flags;
@@ -653,11 +834,15 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		.y2 = crtc->mode.vdisplay,
 	};
 	bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
+	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
+					DRM_PLANE_HELPER_NO_SCALING;
+	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
+					DRM_PLANE_HELPER_NO_SCALING;
 
 	ret = drm_plane_helper_check_update(plane, crtc, fb,
 					    &src, &dest, &clip,
-					    DRM_PLANE_HELPER_NO_SCALING,
-					    DRM_PLANE_HELPER_NO_SCALING,
+					    min_scale,
+					    max_scale,
 					    can_position, false, &visible);
 	if (ret)
 		return ret;
@@ -761,9 +946,18 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
 		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
 	}
+
+	if (win->phy->scl)
+		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+				    dest.x2 - dest.x1, dest.y2 - dest.y1,
+				    fb->pixel_format);
+
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
+
+	val = (dest.y2 - dest.y1 - 1) << 16;
+	val |= (dest.x2 - dest.x1 - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, dsp_info, val);
 	val = (dsp_sty - 1) << 16;
 	val |= (dsp_stx - 1) & 0xffff;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 63e9b3a..a2d4ddb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -198,4 +198,92 @@ enum factor_mode {
 	ALPHA_SRC_GLOBAL,
 };
 
+enum scale_mode {
+	SCALE_NONE = 0x0,
+	SCALE_UP   = 0x1,
+	SCALE_DOWN = 0x2
+};
+
+enum lb_mode {
+	LB_YUV_3840X5 = 0x0,
+	LB_YUV_2560X8 = 0x1,
+	LB_RGB_3840X2 = 0x2,
+	LB_RGB_2560X4 = 0x3,
+	LB_RGB_1920X5 = 0x4,
+	LB_RGB_1280X8 = 0x5
+};
+
+enum sacle_up_mode {
+	SCALE_UP_BIL = 0x0,
+	SCALE_UP_BIC = 0x1
+};
+
+enum scale_down_mode {
+	SCALE_DOWN_BIL = 0x0,
+	SCALE_DOWN_AVG = 0x1
+};
+
+#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
+#define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
+#define SCL_MAX_VSKIPLINES		4
+#define MIN_SCL_FT_AFTER_VSKIP		1
+
+static inline uint16_t scl_cal_scale(int src, int dst, int shift)
+{
+	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
+}
+
+#define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
+#define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
+#define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
+
+static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
+					     int vskiplines)
+{
+	int act_height;
+
+	act_height = (src_h + vskiplines - 1) / vskiplines;
+
+	return GET_SCL_FT_BILI_DN(act_height, dst_h);
+}
+
+static inline enum scale_mode scl_get_scl_mode(int src, int dst)
+{
+	if (src < dst)
+		return SCALE_UP;
+	else if (src > dst)
+		return SCALE_DOWN;
+
+	return SCALE_NONE;
+}
+
+static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
+{
+	uint32_t vskiplines;
+
+	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
+		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
+			break;
+
+	return vskiplines;
+}
+
+static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
+{
+	int lb_mode;
+
+	if (width > 2560)
+		lb_mode = LB_RGB_3840X2;
+	else if (width > 1920)
+		lb_mode = LB_RGB_2560X4;
+	else if (!is_yuv)
+		lb_mode = LB_RGB_1920X5;
+	else if (width > 1280)
+		lb_mode = LB_YUV_3840X5;
+	else
+		lb_mode = LB_YUV_2560X8;
+
+	return lb_mode;
+}
+
 #endif /* _ROCKCHIP_DRM_VOP_H */
-- 
1.7.9.5


_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v4 6/6] drm/rockchip: vop: support plane scale

[Mark Yao]

Win_full support 1/8 to 8 scale down/up engine, support
all format scale.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: 
Adviced by Tomasz Figa
- calcaute min/max scale with readable macro.

Changes in v3:
Adviced by Tomasz Figa
- remove unused code and unnecessary scale path.
- use static inline funcion instead "#define", let gcc check the cast
- move same call into helper, make code clean.

Changes in v2:
- Fix scale dest info. 
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  198 ++++++++++++++++++++++++++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 ++++++++++++
 2 files changed, 284 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 16b7d98..5d8ae5e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -50,6 +50,8 @@
 
 #define VOP_WIN_SET(x, win, name, v) \
 		REG_SET(x, win->base, win->phy->name, v, RELAXED)
+#define VOP_SCL_SET(x, win, name, v) \
+		REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
 #define VOP_CTRL_SET(x, name, v) \
 		REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
 
@@ -164,7 +166,37 @@ struct vop_ctrl {
 	struct vop_reg vpost_st_end;
 };
 
+struct vop_scl_regs {
+	struct vop_reg cbcr_vsd_mode;
+	struct vop_reg cbcr_vsu_mode;
+	struct vop_reg cbcr_hsd_mode;
+	struct vop_reg cbcr_ver_scl_mode;
+	struct vop_reg cbcr_hor_scl_mode;
+	struct vop_reg yrgb_vsd_mode;
+	struct vop_reg yrgb_vsu_mode;
+	struct vop_reg yrgb_hsd_mode;
+	struct vop_reg yrgb_ver_scl_mode;
+	struct vop_reg yrgb_hor_scl_mode;
+	struct vop_reg line_load_mode;
+	struct vop_reg cbcr_axi_gather_num;
+	struct vop_reg yrgb_axi_gather_num;
+	struct vop_reg vsd_cbcr_gt2;
+	struct vop_reg vsd_cbcr_gt4;
+	struct vop_reg vsd_yrgb_gt2;
+	struct vop_reg vsd_yrgb_gt4;
+	struct vop_reg bic_coe_sel;
+	struct vop_reg cbcr_axi_gather_en;
+	struct vop_reg yrgb_axi_gather_en;
+
+	struct vop_reg lb_mode;
+	struct vop_reg scale_yrgb_x;
+	struct vop_reg scale_yrgb_y;
+	struct vop_reg scale_cbcr_x;
+	struct vop_reg scale_cbcr_y;
+};
+
 struct vop_win_phy {
+	const struct vop_scl_regs *scl;
 	const uint32_t *data_formats;
 	uint32_t nformats;
 
@@ -222,7 +254,36 @@ static const uint32_t formats_234[] = {
 	DRM_FORMAT_BGR565,
 };
 
+static const struct vop_scl_regs win_full_scl = {
+	.cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
+	.cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
+	.cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
+	.cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
+	.cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
+	.yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
+	.yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
+	.yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
+	.yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
+	.yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
+	.line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
+	.cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
+	.yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
+	.vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
+	.vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
+	.vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
+	.vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
+	.bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
+	.cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
+	.yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
+	.lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
+	.scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+	.scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+	.scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+	.scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
 static const struct vop_win_phy win01_data = {
+	.scl = &win_full_scl,
 	.data_formats = formats_01,
 	.nformats = ARRAY_SIZE(formats_01),
 	.enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
@@ -422,6 +483,126 @@ static bool is_alpha_support(uint32_t format)
 	}
 }
 
+static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
+				  uint32_t dst, bool is_horizontal,
+				  int vsu_mode, int *vskiplines)
+{
+	uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
+
+	if (is_horizontal) {
+		if (mode == SCALE_UP)
+			val = GET_SCL_FT_BIC(src, dst);
+		else if (mode == SCALE_DOWN)
+			val = GET_SCL_FT_BILI_DN(src, dst);
+	} else {
+		if (mode == SCALE_UP) {
+			if (vsu_mode == SCALE_UP_BIL)
+				val = GET_SCL_FT_BILI_UP(src, dst);
+			else
+				val = GET_SCL_FT_BIC(src, dst);
+		} else if (mode == SCALE_DOWN) {
+			if (vskiplines) {
+				*vskiplines = scl_get_vskiplines(src, dst);
+				val = scl_get_bili_dn_vskip(src, dst,
+							    *vskiplines);
+			} else {
+				val = GET_SCL_FT_BILI_DN(src, dst);
+			}
+		}
+	}
+
+	return val;
+}
+
+static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
+			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
+			     uint32_t dst_h, uint32_t pixel_format)
+{
+	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
+	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
+	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
+	int hsub = drm_format_horz_chroma_subsampling(pixel_format);
+	int vsub = drm_format_vert_chroma_subsampling(pixel_format);
+	bool is_yuv = is_yuv_support(pixel_format);
+	uint16_t cbcr_src_w = src_w / hsub;
+	uint16_t cbcr_src_h = src_h / vsub;
+	uint16_t vsu_mode;
+	uint16_t lb_mode;
+	uint32_t val;
+	int vskiplines;
+
+	if (dst_w > 3840) {
+		DRM_ERROR("Maximum destination width (3840) exceeded\n");
+		return;
+	}
+
+	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
+	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
+
+	if (is_yuv) {
+		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
+		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
+		if (cbcr_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, true);
+		else
+			lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
+	} else {
+		if (yrgb_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, false);
+		else
+			lb_mode = scl_vop_cal_lb_mode(src_w, false);
+	}
+
+	VOP_SCL_SET(vop, win, lb_mode, lb_mode);
+	if (lb_mode == LB_RGB_3840X2) {
+		if (yrgb_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow yrgb ver scale\n");
+			return;
+		}
+		if (cbcr_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow cbcr ver scale\n");
+			return;
+		}
+		vsu_mode = SCALE_UP_BIL;
+	} else if (lb_mode == LB_RGB_2560X4) {
+		vsu_mode = SCALE_UP_BIL;
+	} else {
+		vsu_mode = SCALE_UP_BIC;
+	}
+
+	val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
+				true, 0, NULL);
+	VOP_SCL_SET(vop, win, scale_yrgb_x, val);
+	val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
+				false, vsu_mode, &vskiplines);
+	VOP_SCL_SET(vop, win, scale_yrgb_y, val);
+
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
+
+	VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
+	if (is_yuv) {
+		val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
+					dst_w, true, 0, NULL);
+		VOP_SCL_SET(vop, win, scale_cbcr_x, val);
+		val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
+					dst_h, false, vsu_mode, &vskiplines);
+		VOP_SCL_SET(vop, win, scale_cbcr_y, val);
+
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
+		VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
+	}
+}
+
 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 {
 	unsigned long flags;
@@ -653,11 +834,15 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		.y2 = crtc->mode.vdisplay,
 	};
 	bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
+	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
+					DRM_PLANE_HELPER_NO_SCALING;
+	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
+					DRM_PLANE_HELPER_NO_SCALING;
 
 	ret = drm_plane_helper_check_update(plane, crtc, fb,
 					    &src, &dest, &clip,
-					    DRM_PLANE_HELPER_NO_SCALING,
-					    DRM_PLANE_HELPER_NO_SCALING,
+					    min_scale,
+					    max_scale,
 					    can_position, false, &visible);
 	if (ret)
 		return ret;
@@ -761,9 +946,18 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
 		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
 	}
+
+	if (win->phy->scl)
+		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+				    dest.x2 - dest.x1, dest.y2 - dest.y1,
+				    fb->pixel_format);
+
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
+
+	val = (dest.y2 - dest.y1 - 1) << 16;
+	val |= (dest.x2 - dest.x1 - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, dsp_info, val);
 	val = (dsp_sty - 1) << 16;
 	val |= (dsp_stx - 1) & 0xffff;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 63e9b3a..a2d4ddb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -198,4 +198,92 @@ enum factor_mode {
 	ALPHA_SRC_GLOBAL,
 };
 
+enum scale_mode {
+	SCALE_NONE = 0x0,
+	SCALE_UP   = 0x1,
+	SCALE_DOWN = 0x2
+};
+
+enum lb_mode {
+	LB_YUV_3840X5 = 0x0,
+	LB_YUV_2560X8 = 0x1,
+	LB_RGB_3840X2 = 0x2,
+	LB_RGB_2560X4 = 0x3,
+	LB_RGB_1920X5 = 0x4,
+	LB_RGB_1280X8 = 0x5
+};
+
+enum sacle_up_mode {
+	SCALE_UP_BIL = 0x0,
+	SCALE_UP_BIC = 0x1
+};
+
+enum scale_down_mode {
+	SCALE_DOWN_BIL = 0x0,
+	SCALE_DOWN_AVG = 0x1
+};
+
+#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
+#define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
+#define SCL_MAX_VSKIPLINES		4
+#define MIN_SCL_FT_AFTER_VSKIP		1
+
+static inline uint16_t scl_cal_scale(int src, int dst, int shift)
+{
+	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
+}
+
+#define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
+#define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
+#define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
+
+static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
+					     int vskiplines)
+{
+	int act_height;
+
+	act_height = (src_h + vskiplines - 1) / vskiplines;
+
+	return GET_SCL_FT_BILI_DN(act_height, dst_h);
+}
+
+static inline enum scale_mode scl_get_scl_mode(int src, int dst)
+{
+	if (src < dst)
+		return SCALE_UP;
+	else if (src > dst)
+		return SCALE_DOWN;
+
+	return SCALE_NONE;
+}
+
+static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
+{
+	uint32_t vskiplines;
+
+	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
+		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
+			break;
+
+	return vskiplines;
+}
+
+static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
+{
+	int lb_mode;
+
+	if (width > 2560)
+		lb_mode = LB_RGB_3840X2;
+	else if (width > 1920)
+		lb_mode = LB_RGB_2560X4;
+	else if (!is_yuv)
+		lb_mode = LB_RGB_1920X5;
+	else if (width > 1280)
+		lb_mode = LB_YUV_3840X5;
+	else
+		lb_mode = LB_YUV_2560X8;
+
+	return lb_mode;
+}
+
 #endif /* _ROCKCHIP_DRM_VOP_H */
-- 
1.7.9.5

[PATCH v4 6/6] drm/rockchip: vop: support plane scale

[Mark Yao]

Win_full support 1/8 to 8 scale down/up engine, support
all format scale.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
Changes in v4: 
Adviced by Tomasz Figa
- calcaute min/max scale with readable macro.

Changes in v3:
Adviced by Tomasz Figa
- remove unused code and unnecessary scale path.
- use static inline funcion instead "#define", let gcc check the cast
- move same call into helper, make code clean.

Changes in v2:
- Fix scale dest info. 
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  198 ++++++++++++++++++++++++++-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 ++++++++++++
 2 files changed, 284 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 16b7d98..5d8ae5e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -50,6 +50,8 @@
 
 #define VOP_WIN_SET(x, win, name, v) \
 		REG_SET(x, win->base, win->phy->name, v, RELAXED)
+#define VOP_SCL_SET(x, win, name, v) \
+		REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
 #define VOP_CTRL_SET(x, name, v) \
 		REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
 
@@ -164,7 +166,37 @@ struct vop_ctrl {
 	struct vop_reg vpost_st_end;
 };
 
+struct vop_scl_regs {
+	struct vop_reg cbcr_vsd_mode;
+	struct vop_reg cbcr_vsu_mode;
+	struct vop_reg cbcr_hsd_mode;
+	struct vop_reg cbcr_ver_scl_mode;
+	struct vop_reg cbcr_hor_scl_mode;
+	struct vop_reg yrgb_vsd_mode;
+	struct vop_reg yrgb_vsu_mode;
+	struct vop_reg yrgb_hsd_mode;
+	struct vop_reg yrgb_ver_scl_mode;
+	struct vop_reg yrgb_hor_scl_mode;
+	struct vop_reg line_load_mode;
+	struct vop_reg cbcr_axi_gather_num;
+	struct vop_reg yrgb_axi_gather_num;
+	struct vop_reg vsd_cbcr_gt2;
+	struct vop_reg vsd_cbcr_gt4;
+	struct vop_reg vsd_yrgb_gt2;
+	struct vop_reg vsd_yrgb_gt4;
+	struct vop_reg bic_coe_sel;
+	struct vop_reg cbcr_axi_gather_en;
+	struct vop_reg yrgb_axi_gather_en;
+
+	struct vop_reg lb_mode;
+	struct vop_reg scale_yrgb_x;
+	struct vop_reg scale_yrgb_y;
+	struct vop_reg scale_cbcr_x;
+	struct vop_reg scale_cbcr_y;
+};
+
 struct vop_win_phy {
+	const struct vop_scl_regs *scl;
 	const uint32_t *data_formats;
 	uint32_t nformats;
 
@@ -222,7 +254,36 @@ static const uint32_t formats_234[] = {
 	DRM_FORMAT_BGR565,
 };
 
+static const struct vop_scl_regs win_full_scl = {
+	.cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
+	.cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
+	.cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
+	.cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
+	.cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
+	.yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
+	.yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
+	.yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
+	.yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
+	.yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
+	.line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
+	.cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
+	.yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
+	.vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
+	.vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
+	.vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
+	.vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
+	.bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
+	.cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
+	.yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
+	.lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
+	.scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+	.scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+	.scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+	.scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
 static const struct vop_win_phy win01_data = {
+	.scl = &win_full_scl,
 	.data_formats = formats_01,
 	.nformats = ARRAY_SIZE(formats_01),
 	.enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
@@ -422,6 +483,126 @@ static bool is_alpha_support(uint32_t format)
 	}
 }
 
+static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
+				  uint32_t dst, bool is_horizontal,
+				  int vsu_mode, int *vskiplines)
+{
+	uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
+
+	if (is_horizontal) {
+		if (mode == SCALE_UP)
+			val = GET_SCL_FT_BIC(src, dst);
+		else if (mode == SCALE_DOWN)
+			val = GET_SCL_FT_BILI_DN(src, dst);
+	} else {
+		if (mode == SCALE_UP) {
+			if (vsu_mode == SCALE_UP_BIL)
+				val = GET_SCL_FT_BILI_UP(src, dst);
+			else
+				val = GET_SCL_FT_BIC(src, dst);
+		} else if (mode == SCALE_DOWN) {
+			if (vskiplines) {
+				*vskiplines = scl_get_vskiplines(src, dst);
+				val = scl_get_bili_dn_vskip(src, dst,
+							    *vskiplines);
+			} else {
+				val = GET_SCL_FT_BILI_DN(src, dst);
+			}
+		}
+	}
+
+	return val;
+}
+
+static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
+			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
+			     uint32_t dst_h, uint32_t pixel_format)
+{
+	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
+	uint16_t cbcr_hor_scl_mode = SCALE_NONE;
+	uint16_t cbcr_ver_scl_mode = SCALE_NONE;
+	int hsub = drm_format_horz_chroma_subsampling(pixel_format);
+	int vsub = drm_format_vert_chroma_subsampling(pixel_format);
+	bool is_yuv = is_yuv_support(pixel_format);
+	uint16_t cbcr_src_w = src_w / hsub;
+	uint16_t cbcr_src_h = src_h / vsub;
+	uint16_t vsu_mode;
+	uint16_t lb_mode;
+	uint32_t val;
+	int vskiplines;
+
+	if (dst_w > 3840) {
+		DRM_ERROR("Maximum destination width (3840) exceeded\n");
+		return;
+	}
+
+	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
+	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
+
+	if (is_yuv) {
+		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
+		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
+		if (cbcr_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, true);
+		else
+			lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
+	} else {
+		if (yrgb_hor_scl_mode == SCALE_DOWN)
+			lb_mode = scl_vop_cal_lb_mode(dst_w, false);
+		else
+			lb_mode = scl_vop_cal_lb_mode(src_w, false);
+	}
+
+	VOP_SCL_SET(vop, win, lb_mode, lb_mode);
+	if (lb_mode == LB_RGB_3840X2) {
+		if (yrgb_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow yrgb ver scale\n");
+			return;
+		}
+		if (cbcr_ver_scl_mode != SCALE_NONE) {
+			DRM_ERROR("ERROR : not allow cbcr ver scale\n");
+			return;
+		}
+		vsu_mode = SCALE_UP_BIL;
+	} else if (lb_mode == LB_RGB_2560X4) {
+		vsu_mode = SCALE_UP_BIL;
+	} else {
+		vsu_mode = SCALE_UP_BIC;
+	}
+
+	val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
+				true, 0, NULL);
+	VOP_SCL_SET(vop, win, scale_yrgb_x, val);
+	val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
+				false, vsu_mode, &vskiplines);
+	VOP_SCL_SET(vop, win, scale_yrgb_y, val);
+
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
+	VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
+
+	VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
+	VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
+	VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
+	if (is_yuv) {
+		val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
+					dst_w, true, 0, NULL);
+		VOP_SCL_SET(vop, win, scale_cbcr_x, val);
+		val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
+					dst_h, false, vsu_mode, &vskiplines);
+		VOP_SCL_SET(vop, win, scale_cbcr_y, val);
+
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
+		VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
+		VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
+		VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
+		VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
+	}
+}
+
 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 {
 	unsigned long flags;
@@ -653,11 +834,15 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		.y2 = crtc->mode.vdisplay,
 	};
 	bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
+	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
+					DRM_PLANE_HELPER_NO_SCALING;
+	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
+					DRM_PLANE_HELPER_NO_SCALING;
 
 	ret = drm_plane_helper_check_update(plane, crtc, fb,
 					    &src, &dest, &clip,
-					    DRM_PLANE_HELPER_NO_SCALING,
-					    DRM_PLANE_HELPER_NO_SCALING,
+					    min_scale,
+					    max_scale,
 					    can_position, false, &visible);
 	if (ret)
 		return ret;
@@ -761,9 +946,18 @@ static int vop_update_plane_event(struct drm_plane *plane,
 		VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
 		VOP_WIN_SET(vop, win, uv_mst, uv_mst);
 	}
+
+	if (win->phy->scl)
+		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+				    dest.x2 - dest.x1, dest.y2 - dest.y1,
+				    fb->pixel_format);
+
 	val = (actual_h - 1) << 16;
 	val |= (actual_w - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, act_info, val);
+
+	val = (dest.y2 - dest.y1 - 1) << 16;
+	val |= (dest.x2 - dest.x1 - 1) & 0xffff;
 	VOP_WIN_SET(vop, win, dsp_info, val);
 	val = (dsp_sty - 1) << 16;
 	val |= (dsp_stx - 1) & 0xffff;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 63e9b3a..a2d4ddb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -198,4 +198,92 @@ enum factor_mode {
 	ALPHA_SRC_GLOBAL,
 };
 
+enum scale_mode {
+	SCALE_NONE = 0x0,
+	SCALE_UP   = 0x1,
+	SCALE_DOWN = 0x2
+};
+
+enum lb_mode {
+	LB_YUV_3840X5 = 0x0,
+	LB_YUV_2560X8 = 0x1,
+	LB_RGB_3840X2 = 0x2,
+	LB_RGB_2560X4 = 0x3,
+	LB_RGB_1920X5 = 0x4,
+	LB_RGB_1280X8 = 0x5
+};
+
+enum sacle_up_mode {
+	SCALE_UP_BIL = 0x0,
+	SCALE_UP_BIC = 0x1
+};
+
+enum scale_down_mode {
+	SCALE_DOWN_BIL = 0x0,
+	SCALE_DOWN_AVG = 0x1
+};
+
+#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
+#define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
+#define SCL_MAX_VSKIPLINES		4
+#define MIN_SCL_FT_AFTER_VSKIP		1
+
+static inline uint16_t scl_cal_scale(int src, int dst, int shift)
+{
+	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
+}
+
+#define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
+#define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
+#define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)
+
+static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
+					     int vskiplines)
+{
+	int act_height;
+
+	act_height = (src_h + vskiplines - 1) / vskiplines;
+
+	return GET_SCL_FT_BILI_DN(act_height, dst_h);
+}
+
+static inline enum scale_mode scl_get_scl_mode(int src, int dst)
+{
+	if (src < dst)
+		return SCALE_UP;
+	else if (src > dst)
+		return SCALE_DOWN;
+
+	return SCALE_NONE;
+}
+
+static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
+{
+	uint32_t vskiplines;
+
+	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
+		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
+			break;
+
+	return vskiplines;
+}
+
+static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
+{
+	int lb_mode;
+
+	if (width > 2560)
+		lb_mode = LB_RGB_3840X2;
+	else if (width > 1920)
+		lb_mode = LB_RGB_2560X4;
+	else if (!is_yuv)
+		lb_mode = LB_RGB_1920X5;
+	else if (width > 1280)
+		lb_mode = LB_YUV_3840X5;
+	else
+		lb_mode = LB_YUV_2560X8;
+
+	return lb_mode;
+}
+
 #endif /* _ROCKCHIP_DRM_VOP_H */
-- 
1.7.9.5

[GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

Hi Dave
     Here are some fixes and some new features for rockchip drm,
     tested on popmetal rk3288 board, can you land them?

The following changes since commit db56176025cee5e242dfeed5f4e304d095d29fa3:

   Revert "drm/atomic: Call ww_acquire_done after check phase is 
complete" (2015-08-25 17:23:36 +1000)

are available in the git repository at:

   https://github.com/markyzq/kernel-drm-rockchip.git 
drm-rockchip-2015-08-26

for you to fetch changes up to 4c156c21c7948a0be854cbe5914af3181303e529:

   drm/rockchip: vop: support plane scale (2015-08-26 14:16:26 +0800)

----------------------------------------------------------------
Mark Yao (6):
       drm/rockchip: vop: Fix virtual stride calculation
       drm/rockchip: vop: Fix window dest start point
       drm/rockchip: vop: Add yuv plane support
       drm/rockchip: vop: Default enable win2/3 area0 bit
       drm/rockchip: vop: restore vop registers when resume
       drm/rockchip: vop: support plane scale

  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  269 
++++++++++++++++++++++++++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 +++++++++
  2 files changed, 348 insertions(+), 9 deletions(-)

-Mark

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dri-devel@lists.freedesktop.org
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[GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

Hi Dave
     Here are some fixes and some new features for rockchip drm,
     tested on popmetal rk3288 board, can you land them?

The following changes since commit db56176025cee5e242dfeed5f4e304d095d29fa3:

   Revert "drm/atomic: Call ww_acquire_done after check phase is 
complete" (2015-08-25 17:23:36 +1000)

are available in the git repository at:

   https://github.com/markyzq/kernel-drm-rockchip.git 
drm-rockchip-2015-08-26

for you to fetch changes up to 4c156c21c7948a0be854cbe5914af3181303e529:

   drm/rockchip: vop: support plane scale (2015-08-26 14:16:26 +0800)

----------------------------------------------------------------
Mark Yao (6):
       drm/rockchip: vop: Fix virtual stride calculation
       drm/rockchip: vop: Fix window dest start point
       drm/rockchip: vop: Add yuv plane support
       drm/rockchip: vop: Default enable win2/3 area0 bit
       drm/rockchip: vop: restore vop registers when resume
       drm/rockchip: vop: support plane scale

  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  269 
++++++++++++++++++++++++++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 +++++++++
  2 files changed, 348 insertions(+), 9 deletions(-)

-Mark

[GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

Hi Dave
     Here are some fixes and some new features for rockchip drm,
     tested on popmetal rk3288 board, can you land them?

The following changes since commit db56176025cee5e242dfeed5f4e304d095d29fa3:

   Revert "drm/atomic: Call ww_acquire_done after check phase is 
complete" (2015-08-25 17:23:36 +1000)

are available in the git repository at:

   https://github.com/markyzq/kernel-drm-rockchip.git 
drm-rockchip-2015-08-26

for you to fetch changes up to 4c156c21c7948a0be854cbe5914af3181303e529:

   drm/rockchip: vop: support plane scale (2015-08-26 14:16:26 +0800)

----------------------------------------------------------------
Mark Yao (6):
       drm/rockchip: vop: Fix virtual stride calculation
       drm/rockchip: vop: Fix window dest start point
       drm/rockchip: vop: Add yuv plane support
       drm/rockchip: vop: Default enable win2/3 area0 bit
       drm/rockchip: vop: restore vop registers when resume
       drm/rockchip: vop: support plane scale

  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  269 
++++++++++++++++++++++++++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   88 +++++++++
  2 files changed, 348 insertions(+), 9 deletions(-)

-Mark

[GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

Hi Dave.

     Some fixes and some new features. I'd like you can pull them.

The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:

   drm/nouveau: Pause between setting gpu to D3hot and cutting the power 
(2015-06-26 10:26:37 +1000)

are available in the git repository at:

   https://github.com/markyzq/kernel-drm-rockchip.git 
drm-rockchip-2015-06-30

for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:

   drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)

----------------------------------------------------------------
Heiko Stübner (1):
       drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper 
present

Mark Yao (6):
       drm/rockchip: import dma_buf to gem
       drm/rockchip: vop: optimize virtual stride calculate
       drm/rockchip: vop: fix yuv plane support
       drm/rockchip: vop: support plane scale
       drm/rockchip: vop: switch cursor plane to window 3
       drm/rockchip: default enable win2/3 area0 bit

Tomasz Figa (1):
       drm/rockchip: Add BGR formats to VOP

  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |    1 +
  drivers/gpu/drm/rockchip/rockchip_drm_fb.c  |    3 +-
  drivers/gpu/drm/rockchip/rockchip_drm_gem.c |   40 ++-
  drivers/gpu/drm/rockchip/rockchip_drm_gem.h |    5 +-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  500 
++++++++++++++++++++++++++-
  drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   96 +++++
  6 files changed, 628 insertions(+), 17 deletions(-)

-- 
Ｍark


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Re: [GIT PULL] drm/rockchip: fixes and new features

[Tomasz Figa]

Hi Mark,

On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>
> Hi Dave.
>
>     Some fixes and some new features. I'd like you can pull them.
>
> The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:
>
>   drm/nouveau: Pause between setting gpu to D3hot and cutting the power (2015-06-26 10:26:37 +1000)
>
> are available in the git repository at:
>
>   https://github.com/markyzq/kernel-drm-rockchip.git drm-rockchip-2015-06-30
>
> for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>
>   drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)
>
> ----------------------------------------------------------------
> Heiko Stübner (1):
>       drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper present
>
> Mark Yao (6):
>       drm/rockchip: import dma_buf to gem
>       drm/rockchip: vop: optimize virtual stride calculate
>       drm/rockchip: vop: fix yuv plane support
>       drm/rockchip: vop: support plane scale
>       drm/rockchip: vop: switch cursor plane to window 3
>       drm/rockchip: default enable win2/3 area0 bit

Has this series been reviewed properly? I can see that at least
"drm/rockchip: vop: support plane scale" is kind of "controversial".

By the way, if we're using window 3 for cursor plane, because the
cursor window needs special handling, is it okay to expose the cusor
window as an overlay plane to userspace, as we do currently?

Best regards,
Tomasz
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Daniel Vetter]

On Wed, Jul 01, 2015 at 05:03:39PM +0900, Tomasz Figa wrote:
> Hi Mark,
> 
> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
> >
> > Hi Dave.
> >
> >     Some fixes and some new features. I'd like you can pull them.
> >
> > The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:
> >
> >   drm/nouveau: Pause between setting gpu to D3hot and cutting the power (2015-06-26 10:26:37 +1000)
> >
> > are available in the git repository at:
> >
> >   https://github.com/markyzq/kernel-drm-rockchip.git drm-rockchip-2015-06-30
> >
> > for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
> >
> >   drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)
> >
> > ----------------------------------------------------------------
> > Heiko Stübner (1):
> >       drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper present
> >
> > Mark Yao (6):
> >       drm/rockchip: import dma_buf to gem
> >       drm/rockchip: vop: optimize virtual stride calculate
> >       drm/rockchip: vop: fix yuv plane support
> >       drm/rockchip: vop: support plane scale
> >       drm/rockchip: vop: switch cursor plane to window 3
> >       drm/rockchip: default enable win2/3 area0 bit
> 
> Has this series been reviewed properly? I can see that at least
> "drm/rockchip: vop: support plane scale" is kind of "controversial".

I don't see any discussion of this patch at all on dri-devel, where's this
controversy?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Tomasz Figa]

On Wed, Jul 1, 2015 at 5:20 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Jul 01, 2015 at 05:03:39PM +0900, Tomasz Figa wrote:
>> Hi Mark,
>>
>> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>> >
>> > Hi Dave.
>> >
>> >     Some fixes and some new features. I'd like you can pull them.
>> >
>> > The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:
>> >
>> >   drm/nouveau: Pause between setting gpu to D3hot and cutting the power (2015-06-26 10:26:37 +1000)
>> >
>> > are available in the git repository at:
>> >
>> >   https://github.com/markyzq/kernel-drm-rockchip.git drm-rockchip-2015-06-30
>> >
>> > for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>> >
>> >   drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)
>> >
>> > ----------------------------------------------------------------
>> > Heiko Stübner (1):
>> >       drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper present
>> >
>> > Mark Yao (6):
>> >       drm/rockchip: import dma_buf to gem
>> >       drm/rockchip: vop: optimize virtual stride calculate
>> >       drm/rockchip: vop: fix yuv plane support
>> >       drm/rockchip: vop: support plane scale
>> >       drm/rockchip: vop: switch cursor plane to window 3
>> >       drm/rockchip: default enable win2/3 area0 bit
>>
>> Has this series been reviewed properly? I can see that at least
>> "drm/rockchip: vop: support plane scale" is kind of "controversial".
>
> I don't see any discussion of this patch at all on dri-devel, where's this
> controversy?

Well, it adds a lot of seemingly complex, hard to read code with
obvious style issues. I'll review the series later this week.

Best regards,
Tomasz
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

On 2015年07月01日 16:32, Tomasz Figa wrote:
> On Wed, Jul 1, 2015 at 5:20 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Wed, Jul 01, 2015 at 05:03:39PM +0900, Tomasz Figa wrote:
>>> Hi Mark,
>>>
>>> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>>>> Hi Dave.
>>>>
>>>>      Some fixes and some new features. I'd like you can pull them.
>>>>
>>>> The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:
>>>>
>>>>    drm/nouveau: Pause between setting gpu to D3hot and cutting the power (2015-06-26 10:26:37 +1000)
>>>>
>>>> are available in the git repository at:
>>>>
>>>>    https://github.com/markyzq/kernel-drm-rockchip.git drm-rockchip-2015-06-30
>>>>
>>>> for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>>>>
>>>>    drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)
>>>>
>>>> ----------------------------------------------------------------
>>>> Heiko Stübner (1):
>>>>        drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper present
>>>>
>>>> Mark Yao (6):
>>>>        drm/rockchip: import dma_buf to gem
>>>>        drm/rockchip: vop: optimize virtual stride calculate
>>>>        drm/rockchip: vop: fix yuv plane support
>>>>        drm/rockchip: vop: support plane scale
>>>>        drm/rockchip: vop: switch cursor plane to window 3
>>>>        drm/rockchip: default enable win2/3 area0 bit
>>> Has this series been reviewed properly? I can see that at least
>>> "drm/rockchip: vop: support plane scale" is kind of "controversial".
>> I don't see any discussion of this patch at all on dri-devel, where's this
>> controversy?
> Well, it adds a lot of seemingly complex, hard to read code with
> obvious style issues. I'll review the series later this week.
>
> Best regards,
> Tomasz
>
>
Hi Tomasz

     Thanks, those compute code you can found from RK3288 TRM->"27.3.3 
Win Scaling", too complex.
I had do some clean for the code, but for full function and little bug, 
hard to cleanup.

Best regards,

-- 
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

On 2015年07月01日 16:03, Tomasz Figa wrote:
> Hi Mark,
>
> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>> Hi Dave.
>>
>>      Some fixes and some new features. I'd like you can pull them.
>>
>> The following changes since commit c5fd936e992dd2829167d2adc63e151675ca6898:
>>
>>    drm/nouveau: Pause between setting gpu to D3hot and cutting the power (2015-06-26 10:26:37 +1000)
>>
>> are available in the git repository at:
>>
>>    https://github.com/markyzq/kernel-drm-rockchip.git drm-rockchip-2015-06-30
>>
>> for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>>
>>    drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10 +0800)
>>
>> ----------------------------------------------------------------
>> Heiko Stübner (1):
>>        drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper present
>>
>> Mark Yao (6):
>>        drm/rockchip: import dma_buf to gem
>>        drm/rockchip: vop: optimize virtual stride calculate
>>        drm/rockchip: vop: fix yuv plane support
>>        drm/rockchip: vop: support plane scale
>>        drm/rockchip: vop: switch cursor plane to window 3
>>        drm/rockchip: default enable win2/3 area0 bit
> Has this series been reviewed properly? I can see that at least
> "drm/rockchip: vop: support plane scale" is kind of "controversial".

Sorry for that, can you review those patches, and give me some advices?

https://lkml.org/lkml/2015/6/18/77
v2: https://lkml.org/lkml/2015/6/26/192

> By the way, if we're using window 3 for cursor plane, because the
> cursor window needs special handling, is it okay to expose the cusor
> window as an overlay plane to userspace, as we do currently?

special handling? what means? "switch cursor plane to window 3" patch 
only switch cursor
  windows from win1 to win3. tag window 3 as DRM_PLANE_TYPE_CURSOR, 
userspace only
can found window 3 is a cursor plane.

>
> Best regards,
> Tomasz
>
>
>

Best regards,
Ｍark

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Re: [GIT PULL] drm/rockchip: fixes and new features

[Tomasz Figa]

On Wed, Jul 1, 2015 at 5:32 PM, Mark yao <mark.yao@rock-chips.com> wrote:
> On 2015年07月01日 16:03, Tomasz Figa wrote:
>>
>> Hi Mark,
>>
>> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>>>
>>> Hi Dave.
>>>
>>>      Some fixes and some new features. I'd like you can pull them.
>>>
>>> The following changes since commit
>>> c5fd936e992dd2829167d2adc63e151675ca6898:
>>>
>>>    drm/nouveau: Pause between setting gpu to D3hot and cutting the power
>>> (2015-06-26 10:26:37 +1000)
>>>
>>> are available in the git repository at:
>>>
>>>    https://github.com/markyzq/kernel-drm-rockchip.git
>>> drm-rockchip-2015-06-30
>>>
>>> for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>>>
>>>    drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10
>>> +0800)
>>>
>>> ----------------------------------------------------------------
>>> Heiko Stübner (1):
>>>        drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper
>>> present
>>>
>>> Mark Yao (6):
>>>        drm/rockchip: import dma_buf to gem
>>>        drm/rockchip: vop: optimize virtual stride calculate
>>>        drm/rockchip: vop: fix yuv plane support
>>>        drm/rockchip: vop: support plane scale
>>>        drm/rockchip: vop: switch cursor plane to window 3
>>>        drm/rockchip: default enable win2/3 area0 bit
>>
>> Has this series been reviewed properly? I can see that at least
>> "drm/rockchip: vop: support plane scale" is kind of "controversial".
>
>
> Sorry for that, can you review those patches, and give me some advices?
>
> https://lkml.org/lkml/2015/6/18/77
> v2: https://lkml.org/lkml/2015/6/26/192
>

Yes, will do that.

By the way, please feel free to ping patches on the lists if they idle
without any comments or tags for while.

>> By the way, if we're using window 3 for cursor plane, because the
>> cursor window needs special handling, is it okay to expose the cusor
>> window as an overlay plane to userspace, as we do currently?
>
>
> special handling? what means? "switch cursor plane to window 3" patch only
> switch cursor
>  windows from win1 to win3. tag window 3 as DRM_PLANE_TYPE_CURSOR, userspace
> only
> can found window 3 is a cursor plane.
>

Ah, this was a question slightly unrelated to that patch, but I just
noticed in that patch that the hardware cursor window is still exposed
to the userspace as overlay plane, even if it's not quite suitable for
being such.

Best regards,
Tomasz
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

On 2015年07月01日 16:42, Tomasz Figa wrote:
> On Wed, Jul 1, 2015 at 5:32 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>> On 2015年07月01日 16:03, Tomasz Figa wrote:
>>> Hi Mark,
>>>
>>> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>>>> Hi Dave.
>>>>
>>>>       Some fixes and some new features. I'd like you can pull them.
>>>>
>>>> The following changes since commit
>>>> c5fd936e992dd2829167d2adc63e151675ca6898:
>>>>
>>>>     drm/nouveau: Pause between setting gpu to D3hot and cutting the power
>>>> (2015-06-26 10:26:37 +1000)
>>>>
>>>> are available in the git repository at:
>>>>
>>>>     https://github.com/markyzq/kernel-drm-rockchip.git
>>>> drm-rockchip-2015-06-30
>>>>
>>>> for you to fetch changes up to 5295c05eb30d743987172853179333c80b8242bc:
>>>>
>>>>     drm/rockchip: default enable win2/3 area0 bit (2015-06-30 14:24:10
>>>> +0800)
>>>>
>>>> ----------------------------------------------------------------
>>>> Heiko Stübner (1):
>>>>         drm/rockchip: only call drm_fb_helper_hotplug_event if fb_helper
>>>> present
>>>>
>>>> Mark Yao (6):
>>>>         drm/rockchip: import dma_buf to gem
>>>>         drm/rockchip: vop: optimize virtual stride calculate
>>>>         drm/rockchip: vop: fix yuv plane support
>>>>         drm/rockchip: vop: support plane scale
>>>>         drm/rockchip: vop: switch cursor plane to window 3
>>>>         drm/rockchip: default enable win2/3 area0 bit
>>> Has this series been reviewed properly? I can see that at least
>>> "drm/rockchip: vop: support plane scale" is kind of "controversial".
>>
>> Sorry for that, can you review those patches, and give me some advices?
>>
>> https://lkml.org/lkml/2015/6/18/77
>> v2: https://lkml.org/lkml/2015/6/26/192
>>
> Yes, will do that.
>
> By the way, please feel free to ping patches on the lists if they idle
> without any comments or tags for while.
>
>>> By the way, if we're using window 3 for cursor plane, because the
>>> cursor window needs special handling, is it okay to expose the cusor
>>> window as an overlay plane to userspace, as we do currently?
>>
>> special handling? what means? "switch cursor plane to window 3" patch only
>> switch cursor
>>   windows from win1 to win3. tag window 3 as DRM_PLANE_TYPE_CURSOR, userspace
>> only
>> can found window 3 is a cursor plane.
>>
> Ah, this was a question slightly unrelated to that patch, but I just
> noticed in that patch that the hardware cursor window is still exposed
> to the userspace as overlay plane, even if it's not quite suitable for
> being such.

Oh, I know your mean, you mean that code:
         { .base = 0x00, .phy = &cursor_data, .type = 
DRM_PLANE_TYPE_OVERLAY },

right?

That is I plan to do.

hardware cursor window have a problem that hard to resolved.
the window can't support width virtual and can't move out of left top top.
But linux desktop or chromiumos should move cursor out of left or top.

I'm considering remove it or find a another way to reuse it.

> Best regards,
> Tomasz
>
>
>


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Re: [GIT PULL] drm/rockchip: fixes and new features

[Tomasz Figa]

On Wed, Jul 1, 2015 at 6:13 PM, Mark yao <mark.yao@rock-chips.com> wrote:
>>>> By the way, if we're using window 3 for cursor plane, because the
>>>> cursor window needs special handling, is it okay to expose the cusor
>>>> window as an overlay plane to userspace, as we do currently?
>>>
>>>
>>> special handling? what means? "switch cursor plane to window 3" patch
>>> only
>>> switch cursor
>>>   windows from win1 to win3. tag window 3 as DRM_PLANE_TYPE_CURSOR,
>>> userspace
>>> only
>>> can found window 3 is a cursor plane.
>>>
>> Ah, this was a question slightly unrelated to that patch, but I just
>> noticed in that patch that the hardware cursor window is still exposed
>> to the userspace as overlay plane, even if it's not quite suitable for
>> being such.
>
>
> Oh, I know your mean, you mean that code:
>         { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY
> },
>
> right?
>
> That is I plan to do.
>
> hardware cursor window have a problem that hard to resolved.
> the window can't support width virtual and can't move out of left top top.
> But linux desktop or chromiumos should move cursor out of left or top.
>
> I'm considering remove it or find a another way to reuse it.

I think we should remove it for now, because I believe this breaks
applications that enumerate all available planes and use them for
hardware compose. Otherwise they will try to use the hardware cursor
window and will fail, because hardware cursor window has quite strict
requirements.

Best regards,
Tomasz
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Re: [GIT PULL] drm/rockchip: fixes and new features

[Mark yao]

On 2015年07月01日 16:32, Mark yao wrote:
> On 2015年07月01日 16:03, Tomasz Figa wrote:
>> Hi Mark,
>>
>> On Tue, Jun 30, 2015 at 3:50 PM, Mark yao <mark.yao@rock-chips.com> 
>> wrote:
>>> Hi Dave.
>>>
>>>      Some fixes and some new features. I'd like you can pull them.
>>>
>>> The following changes since commit 
>>> c5fd936e992dd2829167d2adc63e151675ca6898:
>>>
>>>    drm/nouveau: Pause between setting gpu to D3hot and cutting the 
>>> power (2015-06-26 10:26:37 +1000)
>>>
>>> are available in the git repository at:
>>>
>>>    https://github.com/markyzq/kernel-drm-rockchip.git 
>>> drm-rockchip-2015-06-30
>>>
>>> for you to fetch changes up to 
>>> 5295c05eb30d743987172853179333c80b8242bc:
>>>
>>>    drm/rockchip: default enable win2/3 area0 bit (2015-06-30 
>>> 14:24:10 +0800)
>>>
>>> ----------------------------------------------------------------
>>> Heiko Stübner (1):
>>>        drm/rockchip: only call drm_fb_helper_hotplug_event if 
>>> fb_helper present
>>>
>>> Mark Yao (6):
>>>        drm/rockchip: import dma_buf to gem
>>>        drm/rockchip: vop: optimize virtual stride calculate
>>>        drm/rockchip: vop: fix yuv plane support
>>>        drm/rockchip: vop: support plane scale
>>>        drm/rockchip: vop: switch cursor plane to window 3
>>>        drm/rockchip: default enable win2/3 area0 bit
>> Has this series been reviewed properly? I can see that at least
>> "drm/rockchip: vop: support plane scale" is kind of "controversial".
>
> Sorry for that, can you review those patches, and give me some advices?
>
> https://lkml.org/lkml/2015/6/18/77
> v2: https://lkml.org/lkml/2015/6/26/192
>
>> By the way, if we're using window 3 for cursor plane, because the
>> cursor window needs special handling, is it okay to expose the cusor
>> window as an overlay plane to userspace, as we do currently?
>
> special handling? what means? "switch cursor plane to window 3" patch 
> only switch cursor
>  windows from win1 to win3. tag window 3 as DRM_PLANE_TYPE_CURSOR, 
> userspace only
> can found window 3 is a cursor plane.

switch cursor win1 to win3 because we want to use win1 as a overlay for 
yuv image, win3 not
support yuv format.  not for special handling.

By the way, win3 power power consume less than win1, cursor use win3 
would save power.

>
>>
>> Best regards,
>> Tomasz
>>
>>
>>
>
> Best regards,
> Ｍark
>
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