[Qemu-devel] Adding secondary ARM processor

[Qemu-devel] Adding secondary ARM processor

[mar.krzeminski]

Hello,

I have board with A9 processor (playing with vexpress model),
for test I want to also add to this setup M3 processor.
The problem is that secondary CPU sees the same device (eg. UART) with 
different address.
I can not figure out, how should I do that. Is it possible in qemu?
If yes, could you point me where I should start to look at it?

Regards,
Marcin

Re: [Qemu-devel] Adding secondary ARM processor

[Peter Crosthwaite]

On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski
<mar.krzeminski@gmail.com> wrote:
> Hello,
>
> I have board with A9 processor (playing with vexpress model),
> for test I want to also add to this setup M3 processor.
> The problem is that secondary CPU sees the same device (eg. UART) with
> different address.

How far into the boot are you? Does A9 have MMU turned on?

info mtree from the monitor should show the view of the address maps.
Anything weird there?

> I can not figure out, how should I do that. Is it possible in qemu?

Yes it should be possible.

> If yes, could you point me where I should start to look at it?
>

xlnx-zynqmp board, which does something similar with A53 and R5. It is
mixed with a combo of MMU and no-MMU capable CPUs.

Regards,
Peter

> Regards,
> Marcin
>

Re: [Qemu-devel] Adding secondary ARM processor

[mar.krzeminski]

W dniu 01.09.2015 o 19:45, Peter Crosthwaite pisze:
> On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski
> <mar.krzeminski@gmail.com> wrote:
>> Hello,
>>
>> I have board with A9 processor (playing with vexpress model),
>> for test I want to also add to this setup M3 processor.
>> The problem is that secondary CPU sees the same device (eg. UART) with
>> different address.
> How far into the boot are you? Does A9 have MMU turned on?
>
> info mtree from the monitor should show the view of the address maps.
> Anything weird there?
I mess my question, sorry.
I meant that address seen from M3 are different by design,
eg. UART0 seen from M3 has base address 0x100, but same UART0 from A9 is 
mapped at 0x200 and I want to emulate this.
This required some remapping at sysbus level (I think), and I do not 
know how to do that - even where to start, that is why I need your help.
>> I can not figure out, how should I do that. Is it possible in qemu?
> Yes it should be possible.
>
>> If yes, could you point me where I should start to look at it?
>>
> xlnx-zynqmp board, which does something similar with A53 and R5. It is
> mixed with a combo of MMU and no-MMU capable CPUs.
I saw this board, but my basic problem is with address mapping.
>
> Regards,
> Peter
>
>> Regards,
>> Marcin
>>

Re: [Qemu-devel] Adding secondary ARM processor

[Peter Crosthwaite]

On Tue, Sep 1, 2015 at 11:27 AM, mar.krzeminski
<mar.krzeminski@gmail.com> wrote:
> W dniu 01.09.2015 o 19:45, Peter Crosthwaite pisze:
>>
>> On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski
>> <mar.krzeminski@gmail.com> wrote:
>>>
>>> Hello,
>>>
>>> I have board with A9 processor (playing with vexpress model),
>>> for test I want to also add to this setup M3 processor.
>>> The problem is that secondary CPU sees the same device (eg. UART) with
>>> different address.
>>
>> How far into the boot are you? Does A9 have MMU turned on?
>>
>> info mtree from the monitor should show the view of the address maps.
>> Anything weird there?
>
> I mess my question, sorry.
> I meant that address seen from M3 are different by design,
> eg. UART0 seen from M3 has base address 0x100, but same UART0 from A9 is
> mapped at 0x200 and I want to emulate this.
> This required some remapping at sysbus level (I think), and I do not know
> how to do that - even where to start, that is why I need your help.

You need the have multiple address spaces, on the machine level.
Create an alternate address space for you M3 and assign it as the cpu
address space (.as field) for that CPU.

sysbus-mmio-map maps things into the default address space. To map
into this non-default AS you need to sysbus_mmio_get_region +
memory_region_add_subregion (to the AS root Memory Region). But you
can only map the original MR once, so you need an alias. Overall
something like this:

ARMCPU m3 = ...
AddressSpace m3as = ...
MemoryRegion uart_m3_alias
CPU(m3)->as = m3as //This is more complex than this but the general idea.

sysbus_mmio_map(uart ...); // as normal, handles A9 via default
memory_region_init_alias(uart_m3_alias, sysbus_mmio_get_region(uart ...));
memory_region_add_subregion(m3as->root, uart_m3_alias,
M3_UART_ALTERNATE_ADDRESS);

This will leave you with an M3 that can see only the UART (at the new
address). You also probably want to map other things from the default
address (RAM etc). Have a look at memory region priorities which can
make lighter work of this, with a big background region and some
overlaying higher prio regions to do your specifics.

HTH.

Regards,
Peter

>>>
>>> I can not figure out, how should I do that. Is it possible in qemu?
>>
>> Yes it should be possible.
>>
>>> If yes, could you point me where I should start to look at it?
>>>
>> xlnx-zynqmp board, which does something similar with A53 and R5. It is
>> mixed with a combo of MMU and no-MMU capable CPUs.
>
> I saw this board, but my basic problem is with address mapping.
>>
>>
>> Regards,
>> Peter
>>
>>> Regards,
>>> Marcin
>>>
>

Re: [Qemu-devel] Adding secondary ARM processor

[Marcin Krzemiński]

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Thanks Peter,

Now I am know where I need to start digging and reading so it really helped!

Regards,
Marcin

2015-09-01 22:12 GMT+02:00 Peter Crosthwaite <crosthwaitepeter@gmail.com>:

> On Tue, Sep 1, 2015 at 11:27 AM, mar.krzeminski
> <mar.krzeminski@gmail.com> wrote:
> > W dniu 01.09.2015 o 19:45, Peter Crosthwaite pisze:
> >>
> >> On Tue, Sep 1, 2015 at 10:19 AM, mar.krzeminski
> >> <mar.krzeminski@gmail.com> wrote:
> >>>
> >>> Hello,
> >>>
> >>> I have board with A9 processor (playing with vexpress model),
> >>> for test I want to also add to this setup M3 processor.
> >>> The problem is that secondary CPU sees the same device (eg. UART) with
> >>> different address.
> >>
> >> How far into the boot are you? Does A9 have MMU turned on?
> >>
> >> info mtree from the monitor should show the view of the address maps.
> >> Anything weird there?
> >
> > I mess my question, sorry.
> > I meant that address seen from M3 are different by design,
> > eg. UART0 seen from M3 has base address 0x100, but same UART0 from A9 is
> > mapped at 0x200 and I want to emulate this.
> > This required some remapping at sysbus level (I think), and I do not know
> > how to do that - even where to start, that is why I need your help.
>
> You need the have multiple address spaces, on the machine level.
> Create an alternate address space for you M3 and assign it as the cpu
> address space (.as field) for that CPU.
>
> sysbus-mmio-map maps things into the default address space. To map
> into this non-default AS you need to sysbus_mmio_get_region +
> memory_region_add_subregion (to the AS root Memory Region). But you
> can only map the original MR once, so you need an alias. Overall
> something like this:
>
> ARMCPU m3 = ...
> AddressSpace m3as = ...
> MemoryRegion uart_m3_alias
> CPU(m3)->as = m3as //This is more complex than this but the general idea.
>
> sysbus_mmio_map(uart ...); // as normal, handles A9 via default
> memory_region_init_alias(uart_m3_alias, sysbus_mmio_get_region(uart ...));
> memory_region_add_subregion(m3as->root, uart_m3_alias,
> M3_UART_ALTERNATE_ADDRESS);
>
> This will leave you with an M3 that can see only the UART (at the new
> address). You also probably want to map other things from the default
> address (RAM etc). Have a look at memory region priorities which can
> make lighter work of this, with a big background region and some
> overlaying higher prio regions to do your specifics.
>
> HTH.
>
> Regards,
> Peter
>
> >>>
> >>> I can not figure out, how should I do that. Is it possible in qemu?
> >>
> >> Yes it should be possible.
> >>
> >>> If yes, could you point me where I should start to look at it?
> >>>
> >> xlnx-zynqmp board, which does something similar with A53 and R5. It is
> >> mixed with a combo of MMU and no-MMU capable CPUs.
> >
> > I saw this board, but my basic problem is with address mapping.
> >>
> >>
> >> Regards,
> >> Peter
> >>
> >>> Regards,
> >>> Marcin
> >>>
> >
>

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