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From: Zhi Wang <zhi.a.wang@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: Water mark update need to wait for next VSYNC?
Date: Sun, 06 Sep 2015 19:54:12 +0800	[thread overview]
Message-ID: <55EC2964.904@intel.com> (raw)
In-Reply-To: <20150906115007.GV29811@intel.com>

Thanks Ville! Learned from you guys. :)

于 09/06/15 19:50, Ville Syrjälä 写道:
> On Sun, Sep 06, 2015 at 07:30:26PM +0800, Zhi Wang wrote:
>> Hi William:
>>       There is a kind of display register marked as double-buffered. It
>> means that HW will *not* latch the value in the register all the time.
>> HW will only latch the value on the start of the vertical blank, or the
>> time when pipe/plane are enabling.
>>
>> So you will see some code pieces are waiting for frame count change
>> after updating a register.
>>
>> For WM registers, it should be double-buffered with armed attribute I
>> believe.
>
> Only since SKL. Before that WM registers weren't double buffered.
>
>> It means after writing the WM registers, you have to write
>> another register to let the WM register become into "armed" state. After
>> the register is "armed", HW will latch the value on the time point
>> mentioned above.
>>
>> So you should see in some code pieces, they write another register after
>> updating the target register, then waits for the frame count change.
>>
>> i.e update WM register -> update PLANE SURF register -> wait for frame
>> count change
>>
>> 于 09/03/15 06:42, Xie, William 写道:
>>> Hi all,
>>>
>>>    Can anyone educate me if water mark update need to wait for next VSYNC?
>>>
>>> In other words, if we flip a frame to overlay for the first time,
>>>
>>> it will be showed in the next VBlank as water mark update needs to wait
>>> for that?
>>>
>>> Is this true or a bug?
>>>
>>> Thanks
>>>
>>> William
>>>
>>>
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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  reply	other threads:[~2015-09-06 11:54 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-02 22:42 Water mark update need to wait for next VSYNC? Xie, William
2015-09-06 11:30 ` Zhi Wang
2015-09-06 11:50   ` Ville Syrjälä
2015-09-06 11:54     ` Zhi Wang [this message]
2015-09-08 15:19     ` Xie, William

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